AK8140A
-Preliminary-
AK8140A
Programmable Clock Generator
Description
AK8140A is AKM’s High-performance programmable clock generator.
AK8140A generates up to four output clocks from a single input frequency with two fractional-N PLLs.
Each output can be programmed for any frequency up to 230MHz.
AK8140A is available in a 24-pin ETSSOP package.
Features
In-system programmability
serial programmable Register via I2C interface
Supply Voltage:
- Device power supply
VDD1-4: 3.0 - 3.6V
High accuracy Clock Generator
- Output buffer supply
VDDO1, 2：1.7 - 3.6V
Flexible Input Clock Source
- Crystal Unit:
16M-60MHz
- External Clock: 4M-100MHz
Operating Temperature Range:
-40 to +85℃
Free Programmable Clock Frequencies
- LVCMOS:
- LVDS:
Package:
up to 160MHz (CLK1-3)
up to 230MHz (CLK4)
24-pin ETSSOP (Lead free)
Low Jitter Performance
- Period Jitter (1):
8.3 ps(max.)
- Cycle to Cycle jitter (1)：
12.8 ps(max.)
- Long Term Jitter (1000cycle, 1)： 41.7 ps(max.)
draft-E-06
Sep -12
-1-
AK8140A
Block Diagram
VDD1
VDD2
VDD3
VDD4
VSSO1 VDDO1
Ext-IN
XIN
XOUT
M
U
X
0
Crystal
OSC
M
U
X
1
M
U
X
5
ODIV
1
CLK1
ODIV
2
CLK2
ODIV
3
CLK3
Fractional-N
PLL1
M
U
X
2
M
U
X
3
PD_N
S0
Register
Fractional-N
S1/SCL
M
PLL2
U
S2/SDA
X
4
ODIV
4
CLK4n
CLK4p
GND
VSS1
VSS2
VSS3
VSS4
VSSO2 VDDO2
Figure 1: AK8140A Programmable Clock Generator
Sep -12
draft-E-06
-2-
AK8140A
Pin Descriptions
XIN
1
24
S1/SCL
XOUT
2
23
S2/SDA
VDD1
3
22
CLK3
VSS1
4
21
VSSO2
GND
5
20
VDDO2
S0
6
19
CLK4n
VSS2
7
18
CLK4p
VDD2
8
17
PD_N
VDD3
9
16
CLK2
VSS3
10
15
VDDO1
VSS4
11
14
VSSO1
VDD4
12
13
CLK1
Figure 2: AK8140A Programmable Clock Generator
24-Pin ETSSOP (Top View)
Pin No.
Pin Name
Pin Type
1
XIN
2
XOUT
AI
AO
Description
3
4
5
6
7
VDD1
VSS1
GND
S0
VSS2
PWR
PWR
AI
AO
PWR
Device power supply
Ground
Connect to Ground
Programmable Control Pin0
Ground
8
VDD2
PWR
Device power supply
9
VDD3
PWR
Device power supply
10
VSS3
PWR
11
VSS4
PWR
Ground
Ground
12
VDD4
PWR
Device power supply
13
CLK1
DIO
LVCMOS output pin1
14
VSSO1
PWR
15
VDDO1
PWR
16
CLK2
DO
17
PD_N
DI
Ground for output buffer.
Output Buffer power supply1
Voltage supply for CLK1 and CLK2
LVCMOS output pin2
Power Down control pin
L：Device is powered down, all outputs are low.
H：output Clock and PLL is normal operation.
Crystal connection or External Clock signal input
Crystal connection
Please leave open when external clock signal input.
draft-E-06
Sep -12
-3-
AK8140A
Pin No.
Pin Name
Pin Type
18
CLK4p
DO
19
CLK4n
DO
20
VDDO2
PWR
21
VSSO2
PWR
22
CLK3
DO
23
S2/SDA
DIO
24
S1/SCL
DI
Description
LVCMOS/LVDS output pin4
Output level programmed Register(Address:)
CLK4p and CLK4n output is opposite when LVCMOS
output.
Output buffer power supply2
Voltage supply for CLK3 and CLK4
Ground for output buffer.
LVCMOS output pin3
Dual function pin
-S2:Programmable control pin2
-SDA: Serial Data input/output
Internal pull-up 500k
Dual function pin
-S1:Programmable control pin1
-SCL: Serial Clock input
Internal pull-down 500k
Ordering Information
Part Number
Marking
Shipping Packaging
Package
Temperature Range
AK8140A
AK8140A
TBD
24-pin ETSSOP
-40 to 85℃
Sep -12
draft-E-06
-4-
AK8140A
Absolute Maximum Rating
Over operating free-air temperature range unless otherwise noted
Items
(1)
Symbol
Ratings
Unit
Supply voltage
VDD
-0.3 to 4.6
V
Input voltage
VIN
VSS-0.3 to VDD+0.3
V
Input current (any pins except supplies)
IIN
±10
mA
Tstg
-55 to 130
C
Storage temperature
Note
(1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating
conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
ESD Sensitive Device
This device is manufactured on a CMOS process, therefore, generically susceptible to
damage by excessive static voltage. Failure to observe proper handling and
installation procedures can cause damage. AKM recommends that this device is handled with
appropriate precautions.
Recommended Operation Conditions
Parameter
Symbol
Operating temperature
Conditions
Ta
VDD
Supply voltage
(1)
VDDO2
Typ
-40
Pin: VDD1-4
C
1.7
1.8
1.9
3.0
3.3
3.6
Pin：VDDO2
1.7
1.8
1.9
Supply voltage for CLK3/4 output
buffer
2.3
2.5
2.7
3.0
3.3
3.6
Supply voltage for CLK1/2 output
buffer
Pin:CLK1,2,3
Cplclk
85
3.6
Output frequency: up to 50MHz
(2)
Unit
3.3
Pin:CLK1,2,3
Output Load Capacitance
Max
3.0
Pin：VDDO1
VDDO１
Min
Output frequency: 50M to 120MHz
Pin:CLK1,2,3
Output frequency: 120M to 160MHz
Pin:CLK4 LVCMOS output
Output frequency: up to 160MHz
V
25
15
pF
10
10
Note:
(1) Power to VDD1-4 requires to be supplied from a single source. A decoupling capacitor for power supply line
should be installed close to each VDD pin.
(2) Output load capacitance for CLK4p/n pin at LVDS output is descripted on page 9 for details.
draft-E-06
Sep -12
-5-
AK8140A
Device Characteristics
over VDD1-4: 3.0 to 3.6V, VDDO1-2:1.7 to 3.6V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX
Unit
Overall Parameter
High Level Input Voltage
VIH
Pin:S0, PD_N, S1/SCL,
S2/SDA, XIN
0.7*VDD
VDD
V
Low Level Input Voltage
VIL
Pin:S0, PD_N, S1/SCL,
S2/SDA, XIN
VSS
0.3*VDD
V
Input Leak Current 1
IL 1
Pin:S0, PD_N, VIN
-1
+1
A
Input Leak Current 2
IL 2
Pin:S2/SCL
-1
+20
A
IL 3
Pin:S1/SDA
-20
+1
A
Input Leak Current 3
No load, all outputs on,
with setting:
Current Consumption 1
IDD1
XIN input freq:100MHz
58
mA
15
mA
0.5
A
CLK1-3:160MHz
CLK4: 230MHz
No load, all outputs OFF,
with setting:
Current Consumption 2
IDD2
XIN input freq:100MHz
CLK1, 2, 3: “L” output
CLK4: “L” output
No load, Power Down mode,
Power Down mode
Current Consumption
SIDD
Crystal Clock Frequency
Fosc
Pin: XI, XO
16
60
MHz
External Clock Input
Frequency
Fin
Pin: XI
When input external input.
4
100
MHz
External Clock Input
Duty Cycle
Findc
Pin: XI
When input external input.
at 1/2*VDD
30
Output Clock Frequency
(1)
Accuracy
Output Lock Time
(2)
PD_N pin =’L’
Faccuracy
Tlock
50
-30
Pin:CLK1-4
70
+30
3
%
ppm
ms
Note
(1) Additional value through IC. This value is guaranteed only when using AKM’s suggested crystal unit on
page 42.
(2) Time to settle output into 0.1% of specified frequency from the point that PD_N pin is changed “0” to “1”.
Sep -12
draft-E-06
-6-
AK8140A
over VDD1-4: 3.0 to 3.6V, VDDO1-2:1.7 to 3.6V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX
Unit
230
460
MHz
6.75
13.5
MHz
PLL1 Characteristics
VCO frequency1
fVCO1
Phase Comparison Frequency1
fcmp1
Period Jitter1
(1)(2)(3)(4)(7)
Cycle to Cycle Jitter1
(1)(2)(3)(5)(7)
(1)(2)(3)(6)(7)
Long Term Jitter1
Jit_period
Jit_C2C
Jit_long
VCO frequency range of
PLL1
Jitter of Output clock from
PLL1
1
Jitter of Output clock from
PLL1
1
Jitter of Output clock from
PLL1
1000 cycle delay, 1
8.3
ps
12.8
ps
40
ps
PLL2 Characteristics
VCO frequency2
fVCO2
Phase Comparison Frequency2
fcmp2
Period Jitter2
(1)(2)(3)(4)(7)
Cycle to Cycle Jitter2
(1)(2)(3)(5)(7)
(1)(2)(3)(6)(7)
Long Term Jitter2
Jit_period
Jit_C2C
Jit_long
VCO frequency range of
PLL2
Jitter of Output clock from
PLL2
1
Jitter of Output clock from
PLL2
1
Jitter of Output clock from
PLL2
1000 cycle delay, 1
80
230
MHz
2.5
14.375
MHz
8.3
ps
12.8
ps
41.7
ps
Note
(1) Design Value
(2) With the load describes on page5.
(3) When only one side is taking out operation or the same frequency among the output buffers which share a power
supply pin (VDDO1, 2).
(4) Jitter depends on configuration. Jitter data is for input frequency = 48MHz, output frequency = 27M/48M/50MHz.
(5) Jitter depends on configuration. Jitter data is for input frequency = 25M/30M/50MHz,
output frequency = 27M/50MHz.
(6) Jitter depends on configuration. Jitter data is for input frequency = 27MHz, output frequency = 25M/148.5MHz.
(7) 10000 sampling or more
draft-E-06
Sep -12
-7-
AK8140A
over VDD1-4: 3.0 to 3.6V, VDDO1-2:1.7 to 3.6V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX
Unit
LVCMOS output parameter
Output Frequency
fout
High Level Output Voltage
VOH
Low level Output Voltage
VOL
Output Clock Rise Time
Output Clock Fall Time
(1)(2)(3)(4)
(1)(2)(3)(4)
Output Clock Duty Cycle
(1)
(2)
(3)
(4)
(1)(2)
T_rise
T_fall
Pin:CLK1-4
MHz
160
Pin: CLK1-4
0.8*VDDO1, 2
IOH=-4mA
V
Pin: CLK1-4
IOL=+4mA
Pin:CLK1-3
with Load cplclk=10pF(upper),
25pF(lower)
0.2*VDDO1, 2 → 0.8*VDDO1, 2
Pin:CLK4, VDDO2=3.3V
with Load Cplclk=10pF
0.2*VDDO2 → 0.8*VDDO2
Pin:CLK1-3
with Load Cplclk=10pF(upper),
25pF(lower)
0.2*VDDO1, 2 → 0.8*VDDO1, 2
Pin:CLK4, VDDO2=3.3V
with Load Cplclk=10pF
0.2*VDDO2 → 0.8*VDDO2
Pin:CLK1, 2, 3, 4
When ODIVn divides the PLL1/2
clock.
Pin:CLK1, 2, 3, 4
When ODIVn divides the Input
Bypass clock by even dividing
value.
Pin:CLK1, 2, 3, 4
When ODIVn divides the Input
Bypass clock by odd dividing
value.
0.2*VDDO1, 2
V
0.7
1.2
Ns
0.3
0.7
1.2
Ns
0.3
45
50
55
45
50
55
20
%
80
Design Value
With the load describes on page5.
When VDDO1/2=1.8V :CLKnMOD(n=1-3)=‘0’，when VDDO1/2=3.3V, CLKnMOD(n=1-3) =‘1’.
When VDDO1/2=3.3V :CLK4MOD=‘1’.
Sep -12
draft-E-06
-8-
AK8140A
over VDD1-4: 3.0 to 3.6V, VDDO1-2:1.7 to 3.6V, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX
Unit
230
MHz
mVpp
CLK4 LVDS Output Parameter
Output Frequency
fout
Output Differential Voltage
Offset Voltage
(1)(2)
(1)(2)
Vos
(1)(2)
Output Clock Rise Time
(1)(2)
Output Clock Fall Time
Output Clock Duty Cycle
(1)
(2)
Vod
(1)(2)
T_rise
T_fall
VDDO2=:2.3 to 3.6V,
CLK4MOD=”1”
VDDO2=:1.7 to 1.9V,
CLK4MOD=”0”
0.2*VDDO2 → 0.8*VDDO2
0.2*VDDO2 → 0.8*VDDO2
When ODIV4 divides the
PLL1/2 clock
When ODIV4 divides the
Input Bypass clock by even
dividing value
When ODIV4 divides the
Input Bypass clock by odd
dividing value
250
350
450
1.125
1.240
1.375
0.685
0.800
0.935
V
0.2
0.2
ns
ns
45
50
55
%
45
50
55
%
80
%
20
Design Value
LVDS clock measured at the circuit shown in Figure.4
CLK4p
Z0=100 Differential
CLK4n
OUTP
100
OUTN
AK8140A
Figure.4 CLK4 LVDS Clock measurement circuit
draft-E-06
Sep -12
-9-
AK8140A
Frequency setting procedure
When set the CLKn* output frequency to the same as the XIN input frequency (fin), set MUXn* to
‘XIN’ by the Register (address:0Ch). *n=1-4
-PLL1 Setting Procedure-
fin1
MDIV1
fcmp1
NDIV1
PFD/CP/LPF/
VCO
fvco1
ODIVn
foutn
(INT+FRAC)
Figure.5 PLL1 Block Diagram
Output frequency from PLL1 is determined by PLL1 parameter: REFCLK Dividing value (MDIV1),
Fractional-N1 Dividing value (INT, FRAC), and OUTPUT Dividing value (ODIV1-4).
These parameters should be set as described below.
Step1. Deciding VCO1 target frequency.
This frequency (fvco1) is decided from CLKn Output frequency (foutn) and Output dividing value
(ODIVn, set by address: 0Dh~13h).Set fVCO1 frequency between 230MHz to 460MHz.
230MHz≦fVCO1≦460MHz
(fVCO1=foutn×ODIVn)
Step2. Deciding Phase comparison frequency.
Set MDIV1 divider as this frequency (fcmp1) becomes between 6.75MHz to 13.5MHz.
6.75MHz≦fcmp1≦13.5MHz
(fcmp1 = Fin1 / MDIV1)
Step3. Deciding Feedback dividing value.
This value is decided by VCO1 frequency (fvco1) and Phase comparison frequency (fcmp1).
7 bits integral part and 18 bits fractional part (signed 2’s complement) is necessary to be set.
Integral part (INT)
Fractional part (FRAC)
= round ( fvco1 / fcmp1 )
18
= round ( ( fvco1 / fcmp1 ) – INT ) x 2 )
Sep -12
draft-E-06
- 10 -
AK8140A
Example1) input 27MHz, output 123.75MHz
1. fVCO1
VCO1 frequency:
247.5MHz
2. fcmp1
Phase comparison frequency1:
3. NDIV1
Feedback dividing value:
ODIV = 2
9MHz
MDIV = 3
27MHz / 3 = 9MHz
27.5
INT = 28d, FRAC =-131072d
INT = round (247.5 / 9) = round(27.5) = 28d
18
FRAC = round (( 27.5 – 28 ) x 2 ) = -131072d
Output frequency error: 0ppm
Example2) input 16MHz, output 24.576MHz
1. fVCO1
VCO frequency:
294.912MHz
2. fcmp1
Phase comparison frequency:
3. NDIV1
Feedback dividing value:
ODIV = 12
8MHz
MDIV = 2
16MHz / 2 = 8MHz
36.864
INT = 37d, FRAC = -35652d
INT = round (294.912/ 8 ) = round(36.864) = 37d
18
FRAC = round (( 36.864 – 37 ) x 2 ) = -35652d
Output frequency error: 0.043ppm (1.06Hz)
draft-E-06
Sep -12
- 11 -
AK8140A
-PLL2 Setting ProcedureOutput frequency from PLL2 is determined by PLL2 parameter: REFCLK Dividing value (MDIV2),
Fractional-N2 Dividing value (INT, FRAC), and OUTPUT Dividing value (ODIV1-4).
These parameters should be set as described below.
fin2
MDIV2
fcmp2
NDIV2
PFD/CP/LPF/
VCO
fvco2
ODIVn
foutn
(INT+FRAC)
Figure.6 PLL2 Block Diagram
Step1. Deciding VCO2 target frequency.
This frequency (fvco2) is decided from CLKn Output frequency (foutn) and Output dividing value
(ODIVn, set by address: 0Dh~13h). Set fVCO2 frequency between 80MHz to 230MHz.
Where
80MHz≦fVCO2≦230MHz
(fVCO2=foutn×ODIVn)
Step2. Deciding MDIV2 and NDIV2 value when PLL2 is assumed to be Integer PLL.
Set MDIV2 and NDIV2 divider as fcmp2 becomes the highest common measure of fin2 and fvco2.
Where
6.75MHz≦fcmp2≦13.5MHz
MDIV2 (M2):1 to 511
NDIV2 (N2): 1 to 4095
M2 ≦ N2
(fcmp2= fin2 / MDIV2)
Step3. Calculating MDIV2 and NDIV2 values of fractional-N PLL.
Calculate the dividing value of fractional divider, as follows.
MDIV 2 2P
NDIV 2 N INT
N NUME
N DENO
N2
P 4 int log 2
M2
*{if P < 0 then P = 0}
N 2 2P
N INT int
M2
N NUME N 2 2P M 2 N INT
N DENO M 2
Sep -12
draft-E-06
- 12 -
AK8140A
Example1) input 27MHz, output 54MHz
1. fVCO2:
108MHz
ODIVn = 2
2. M2: 1
N2: 4
As the highest common measure of fin2 and fvco2 is 27MHz
3. P:
N INT:
NNUME:
NDEMO：
2
16
0
1
={4-int(log24)}
={int(4×22)/1 }
={4×22-1×16}
={M=1}
∴MDIV = 22= 4， NDIV = 16 + (0/1) = 16
Example2) input 27MHz, output 24.576MHz
1. fVCO2:
221.184MHz ODIVn = 9
2. M2: 125
N2: 1024
As the highest common measure of fin2 and fvco2 is 0.216MHz
3. P:
N INT:
NNUME:
NDEMO：
1
16
0
125
={4-int(log2 (1204/125))}
={int(1024×21)/125 }
={1024×21-125×16}
={M=125}
∴MDIV = 21= 2， NDIV = 16 + (48/125)
draft-E-06
Sep -12
- 13 -
AK8140A
Programmable control pin setting
AK8140A has three user-definable control terminals (S0, S1, and S2) which allow external
control of device settings. The user can define up to eight different control settings shown in Table.
They can be programmed to any of the following functions:
-PLL1/2 frequency:
select from two variation of fVCO frequency set by the applicable register.
-CLK1-4 output state:
select from four states: enable/Hi-z/disable to L/ disable to H.
Programmable
Control Pin
S2
S1
S0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Address Offset
PLL1
PLL2
frequency
frequency
PLL1_0 or
PLL1_1
PLL1_0 or
PLL1_1
PLL1_0 or
PLL1_1
PLL1_0 or
PLL1_1
PLL1_0 or
PLL1_1
PLL1_0 or
PLL1_1
PLL1_0 or
PLL1_1
PLL1_0 or
CLK1
CLK2
CLK3
CLK4
Output
Output
Output
Output
State
State
State
State
PLL2_0 or Enable or Enable or Enable or Enable or
PLL2_1
Disable
Disable
Disable
Disable
PLL2_0 or Enable or Enable or Enable or Enable or
PLL2_1
Disable
Disable
Disable
Disable
PLL2_0 or Enable or Enable or Enable or Enable or
PLL2_1
Disable
Disable
Disable
Disable
PLL2_0 or Enable or Enable or Enable or Enable or
PLL2_1
Disable
Disable
Disable
Disable
PLL2_0 or Enable or Enable or Enable or Enable or
PLL2_1
Disable
Disable
Disable
Disable
PLL2_0 or Enable or Enable or Enable or Enable or
PLL2_1
Disable
Disable
Disable
Disable
PLL2_0 or Enable or Enable or Enable or Enable or
PLL2_1
Disable
Disable
Disable
Disable
PLL2_0 or Enable or Enable or Enable or Enable or
PLL1_1
PLL2_1
Disable
Disable
Disable
Disable
20h
30h
04h, 05h
06h, 07h
08h, 09h
0Ah, 0Bh
Sep -12
draft-E-06
- 14 -
AK8140A
Function Description
Power up sequence
Step1 : Supplying proper voltage to the power pins with PD_N pin =”L”.
*Note: VDD1-4 must be supplied simultaneously.
The assumption power start time to reach 90 % of VDD is within 20 ms.
Step2 : Set the PD_N pin to “H”1 second after the point that the power supply reaches 90% of VDD.
Step3 : SCL / SDA are acceptable min 2ms later.
90% of VDD1-4
VDD1-4
Max 20ms
PD_N
Min 1s
Min 2ms
SDA / SCL input acceptable
SDA / SCL
CLK1-3
CLK4p
CLK4n
draft-E-06
Sep -12
- 15 -
AK8140A
Serial interface （I2C：slave mode） Characteristics
All specifications at VDD1: 3.3V, VDD2/VDD3: 1.8V, Ta: -30 to +85℃, unless otherwise noted.
Design value.
Parameter
Symbol
Conditions
MIN
Typ
MAX
Unit
400
kHz
SCL clock frequency
fSCL
SCL Clock Low Period
tLOW
1.3
us
SCL Clock High Period
tHIGH
0.6
us
Pulse width of spikes which must
be suppressed
tI
SLC Low to SDA Data Out
50
ns
tAA
0.3
us
tBUF
1.3
us
Start Condition Hold Time
tHD.STA
0.6
us
Start Condition Setup Time
(for a Repeated Start condition)
tSU.STA
0.6
ms
Data in Hold Time
tHD.DAT
0
us
Data in Setup Time
tSU.DAT
100
ns
SDA and SCL Rise Time
tR
-
1.0
us
SDA and SCL Fall Time
tF
-
0.3
us
tSU.STO
0.6
Cb
-
Bus free time between a STOP
and START condition
Stop Condition Setup Time
Input Capacitance at SCL/SDA
tF
us
200
pF
tR
SCL (IN)
tSU.STA
tLOW
tHIGH
tHD.DAT
tHD.STA
tSU.STO
tSU.DAT
SDA (IN)
tAA
tDH
tBUF
SDA (OUT)
Sep -12
draft-E-06
- 16 -
AK8140A
Serial interface
Read/Write performance of serial interface is explained as below. The device address of
AK8140A is Device Address#1:1100, Device Address#2:1 A1 0.
A1 is set by the register bit “” (Address:03h).
1
1
0
0
1
Device Adress#1
R:1
W:0
0
A1
Device Adress#2
Write operation
Write operation is described below. Data must be sent after sending 8 bits address and receiving ACK.
It is possible to write next address sequentially by sending next data instead of stop condition.
The address which is written after “13h/15h/2Bh” becomes “14h/20h/30h”.
Write operation
S
T
A
R
T
SDA
Slave
Address
Register
Address(n)
Data(n)
S
T
Data(n+x) O
P
Data(n+1)
S
P
A1 W A
C
K
A
C
K
A
C
K
A
C
K
Current address read
Current address read operation is described below. The data that is read by this operation is obtained
as “last accessed address + 1”. Therefore, it is consequent to return “1111 1110” after accessing the
address “1111 1111”.
Current address read
S
T
A
R
T
SDA
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
S
P
A1 R A
C
K
A
C
K
A
C
K
draft-E-06
A
C
K
Sep -12
- 17 -
AK8140A
Random read
Random read operation is described below. It is necessary to operate “dummy write” before sending
read command. Dummy write is to send the address to read. It is possible to read next address
sequentially by sending ACK instead of stop condition.
Random read
S
T
A
R
T
SDA
Slave
Address
S
T
A
R
T
Word
Address(n)
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
S
A1 W A
C
K
A
C
K
P
A1 R A
C
K
A
C
K
A
C
K
Change data
Change data operation is described below. It is available when SCL is Low.
Change data
SCL
SDA
DATA STABLE
DATA
CHANGE
Start / Stop timing
Start / Stop timing is described below. The sequence is started when SDA goes from high to low
during SCL is high. The sequence is stopped when SDA goes from low to high during SCL is high.
Start / Stop timing
SCL
SDA
START
STOP
Sep -12
draft-E-06
- 18 -
AK8140A
●Register Configuration
AK8140A has Register can be programmed via the serial SDA/SCL interface.
The following tables and explanations describe the programmable functions of Ak8140A.
・Default register state is all ‘0’.
The default setting appears after power is supplied or after power-down/up sequence until it
is reprogrammed to a different setting.
・All data transferred with the MSB first.
・When a Certain Setting is set by two or more Address, please write the data to all Address.
・Write ‘0’ to Reserved bits.
Table AK8140A Register Configuration
Address
Offset
Register
Remarks
Device Setting
・Device Setting (S0/S1/S2)
for Serial Programming mode
・Device Input clock(Crystal or Ext-in)
・Slave Address A1
00h
Generic Configuration
Register
20h
PLL1 Configuration
Register
30h
PLL2 Configuration
Register
Page
p.21
CLK1 to 4 Setting
・CLK1 to 4 Output State
（CLK enabled / Disabled to L /Disabled to H /
Hi-Z）
・MUX1 to 4
(PLL1 fVCO1/ PLL2 fVCO2/ Input Bypass)
・ODIV1 to 4 Parameter
・CLK1 to 4 Output Buffer Drivability
・CLK4 Output Level LVDS or CMOS
PLL1 Setting
p.33
（Input CLK of PLL1,
MDIV1, NDIV1, fVCO1 range）
p.39
PLL2 Setting
（MDIV2,NDIV2,fVCO2 range）
draft-E-06
Sep -12
- 19 -
AK8140A
■Generic Configuration Register
Generic Configuration Register(Address：00h～12h)
Data
Addres
s
D7
D6
D5
D4
D3
D2
Remarks
D1
D0
Reserved
Reserved
Reserved
Reserved
Reserved
S[2]
S[1]
S[0]
00h
Device Control
Setting for
－
－
－
－
－
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SDA/SCL mode
01h
0
0
0
0
0
0
0
0
RID[1]
RID[0]
OSC_DIS
Reserved
R/W
R/W
R/W
R/W
0
0
0
0
－
－
－
－
02h
Device overall
SLV_
PWDN
0
0
0
0
0
0
0
0
CLK1_0
CLK1_0
CLK1_1
CLK1_1
CLK1_2
CLK1_2
CLK1_3
CLK1_
[1]
[0]
［1]
［0]
［1]
［0]
［1]
［0]
0
0
0
0
0
0
0
0
CLK1_4
CLK1_4
CLK1_5
CLK1_5
CLK1_6
CLK1_6
CLK1_7
CLK1_7
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
0
0
0
0
0
0
0
0
CLK2_0
CLK2_0
CLK2_1
CLK2_1
CLK2_2
CLK2_2
CLK2_3
CLK2_3
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
CMOS
SPICON
SPICON_S
Reserved
ADD1
Reserved
CLK4_
Reserved
Setting
ET
03h
04h
CLK1
Output State
Setting
05h
06h
CLK2
Output State
0
0
0
0
0
Sep -12
0
0
0
Setting
draft-E-06
- 20 -
AK8140A
CLK2_4
CLK2_4
CLK2_
CLK2_5
CLK2_6
CLK2_6
CLK2_
CLK2_7
［1]
［0]
5［1]
［0]
［1]
［0]
7［1]
［0]
0
0
0
0
0
0
0
0
CLK3_0
CLK3_0
CLK3_1
CLK3_1
CLK3_2
CLK3_2
CLK3_3
CLK3_3
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
0
0
0
0
0
0
0
0
07h
08h
CLK3
Output State
CLK3_4
CLK3_4
CLK3_5
CLK3_5
CLK3_6
CLK3_6
CLK3_7
CLK3_7
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
0
0
0
0
0
0
0
0
CLK4_0
CLK4_0
CLK4_1
CLK4_1
CLK4_2
CLK4_2
CLK4_3
CLK4_3
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
0
0
0
0
0
0
0
0
Setting
09h
0Ah
CLK4
Output State
CLK4_4
CLK4_4
CLK4_5
CLK4_
CLK4_6
CLK4_6
CLK4_7
CLK4_7
［1]
［0]
［1]
5［0]
［1]
［0]
［1]
［0]
0
0
0
0
0
0
0
0
MUX1
MUX1
MUX2
MUX2
MUX3
MUX3
MUX4
MUX4
[1]
[0]
[1]
[0]
[1]
[0]
[1]
0]
Setting
0Bh
MUX1～4
0Ch
Selection
0
0
0
0
Reserved
Reserved
Reserved
Reserved
0
0
0
0
CLK1
DIV2_
ODIV_1
ODIV_1
MOD
BYPASS1
[9]
[8]
Output Buffer1
Drivability
0Dh
－
－
－
－
0
draft-E-06
0
0
0
ODIV1 Setting
Sep -12
- 21 -
AK8140A
OEh
ODIV_1
ODIV_1
ODIV_1
ODIV_1
ODIV_1
ODIV_1
[7]
[6]
[5]
[4]
[3]
[2]
ODIV_1
0
0
0
0
0
0
0
0
Reserved
Reserved
CLK3
CLK2
DIV2_
DIV2_
ODIV_2
ODIV_2
MOD
MOD
BYPASS3
BYPASS2
[9]
[8]
－
－
0
0
0
0
0
0
[1]
ODIV_1
[0]
0Fh
Output Buffer2/3
Drivability
ODIV_2
ODIV_2
ODIV_2
ODIV_2
ODIV_2
ODIV_2
ODIV_2
ODIV_1
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
ODIV_3
ODIV_3
ODIV_3
ODIV_3
ODIV_3
ODIV_3
ODIV_3
ODIV_3
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
ODIV2 Setting
10h
11h
ODIV3 Setting
0
0
0
0
Reserved
Reserved
Reserved
Reserved
－
－
－
－
0
0
0
0
CLK4
DIV2_
ODIV_4
ODIV_4
MOD
BYPASS4
[9]
[8]
0
0
0
0
12h
Output Buffer4
Drivability
ODIV_4
ODIV_4
ODIV_4
ODIV_4
ODIV_4
ODIV_4
ODIV_4
ODIV_4
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
ODIV4 Setting
13h
Sep -12
draft-E-06
- 22 -
AK8140A
■ Generic Configuration Register
●Address：00h Device Control Setting for Serial Programming mode*
*Valid only when Serial Programming mode (Address：03h SPICON=’0’)
Data
Addres
s
D7
D6
D5
D4
D3
D2
00h
Reserved
Reserved
Reserved
Reserved
S[2]
Reserved
D1
D0
S[1]
S[0]
S[2:0] ： Device Control Setting for Serial Programming mode
When SPICON bit is set to‘0’, pin23/24 has SDA/SCL function and S[2:0] bits select the
Device Control Setting predefined as the table on page 14).
Table below explains the corresponding Device Control Setting defined in the Table on
page14.
S[2:0]:Device Control Setting for Serial Programming mode
Device Control Setting
S[2:0]
(see on page14)
000
[S2:S0]=000
001
[S2:S0]=001
010
[S2:S0]=010
011
[S2:S0]=011
100
[S2:S0]=100
101
[S2:S0]=101
110
[S2:S0]=110
111
[S2:S0]=111
●Address ： 01h
Address
01h
D7
D6
D5
Reserved
Reserved
Reserved
Data
D4
Reserved
D3
D2
D1
D0
Reserved
Reserved
Reserved
Reserved
●Address ： 02h
Address
02h
Data
D7
D6
D5
D4
D3
D2
D1
D0
RID[1]*
RID[0]*
OSC_DIS
Reserved
R/W
R/W
R/W
R/W
RID[1:0]: Device Identification *read only
RID[1:0]
Device Identification
00
AK8140A
01
10
11
draft-E-06
Sep -12
- 23 -
AK8140A
OSC_DIS ： Crystal Oscillator Circuit Enable/Disable Setting（MUX0）
Set the register followed by ICLK source, as explained in the following table.
OSC_DIS
Crystal Oscillator Circuit State
0
Enable（ICLK=Crystal）
1
Disable（ICLK=Ext-in）
R/W ： User arbitrarily programmable bits（D3～D0）
User can freely program these bits if necessary.
●Address：03h
Address
03h
Data
D7
Reserved
D6
D5
D4
D3
D2
D1
D0
Reserved
PWDN
SLV_ADD1
Reserved
CLK4_CMOS
SPICON
EEWRITE
PWDN ： Device Power Down control
.
When set PWDN bit to ’1’, only PLL1/2, ODIVn, is powered down. Register settings are
unchanged.
CLKn output state is followed by CLKn output state selection(Address:04h-0Bh) when the
device is powered down by this bit. *1
PWDN
Device Setting
0
Device Active
1
Device Powered down*1
*1 It becomes CLKn=L, when CLKn output state is set to ‘01’ as “CLK
enabled”.
SLV_ADD1 ： Slave Address Bits A1 Selection
SLV_ADD1 sets the A1 of the Slave Receiver Address.
*The default setting SLV_ADD1= ‘0’ appears after power is supplied or after power-down/up
sequence until it is reprogrammed to a different setting.
* See page 25 for more information about Slave Address setting.
SLV_ADD1
Device Setting
0
A1 of Slave Address ：0
1
A1 of Slave Address ：1 *1
* 1 Default state is A1=’0’
Sep -12
draft-E-06
- 24 -
AK8140A
CLK4_CMOS ： CLK4 Output Level Selection LVDS/CMOS
CLK4_CMOS bit sets CLK4 output level, LVDS or LVCMOS.
CLK4_CMOS
0
1
CLK4 Output Setting
LVDS output
LVCMOS output
SPICON ： Operation mode selection for pin 23/24
SPICON bit selects the operational mode of a dual functional pin 23/24.
If '1' is written, pin 23/24 become “Programmable Control pin S1/S2”, and impossible to
use it as a serial programming terminal. *1
However, S1/S2 pins can be temporarily used as a serial programming terminal,
SDA/SCL by connecting VDDO1 to VSS.
These are the bits of the Control Terminal Register. The user can predefine up to eight
different control settings. These settings then can be selected by the external control
pins, S0, S1, and S2.
*1 the setup of SPICON= "1" becomes effective by writing ’1’ to “SPICON_SET” bit.
SPICON
0
1
Pin 23/24 operation
Serial programming interface*2
Pin 23:SDA
Pin24:SCL
Programmable control pin*3
Pin 23:S2
Pin24:S1
*2 Address：00h,01h becomes effective.
*3 Pin 23/24 can control the Device Setting defined in the table on page
14.
SPICON_SET ：SPICON Validation
“SPICON_SET” validates a setup of” SPICON" bit .
A setup written in SPICON by writing '1' in this bit becomes effective.
* When Set “SPICON_SET” =’1’, “SPICON_SET” bit should be written last.
SPICON_SET
SPICON Setting
0
1
SPICON bit is Effective *1
*1 “SPICON_SET” bit should be written last.
Setup of “SPICON” bit is validated by the rising edge of a “SPICON_SET”
bit.
draft-E-06
Sep -12
- 25 -
AK8140A
●Address：04h～0Bh
Address
04h
05h
06h
07h
08h
09h
0Ah
0Bh
Data
D7
D6
D5
D4
D3
D2
D1
D0
CLK1_0
CLK1_0
CLK1_1
CLK1_1
CLK1_2
CLK1_2
CLK1_3
CLK1_3
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
CLK1_4
CLK1_4
CLK1_5
CLK1_5
CLK1_6
CLK1_6
CLK1_7
CLK1_7
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
CLK2_0
CLK2_0
CLK2_1
CLK2_1
CLK2_2
CLK2_2
CLK2_3
CLK2_3
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
CLK2_4
CLK2_4
CLK2_5
CLK2_5
CLK2_6
CLK2_6
CLK2_7
CLK2_7
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
CLK3_0
CLK3_0
CLK3_1
CLK3_1
CLK3_2
CLK3_2
CLK3_3
CLK3_3
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
CLK3_4
CLK3_4
CLK3_5
CLK3_5
CLK3_6
CLK3_6
CLK3_7
CLK3_7
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
CLK4_0
CLK4_0
CLK4_1
CLK4_1
CLK4_2
CLK4_2
CLK4_3
CLK4_3
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
CLK4_4
CLK4_4
CLK4_5
CLK4_5
CLK4_6
CLK4_6
CLK4_7
CLK4_7
［1]
［0]
［1]
［0]
［1]
［0]
［1]
［0]
CLKn_x [1:0] ： CLK1～4 Output State Definition
CLKn_x [1:0] bit set output state(CLKn_x) defined in the table on page 15 can be set up.
The output frequency at the time CLKn_x is set to “CLK Enabled” (CLKn_x[1:0] ='00')
follows MUXn/ODIVn setting.
* ODIVn function is stopped, when CLKn state is set to Disable (CLKn_x[1:0]
='01'/'10'/'11').
* When CLK4 state is set to Disable, CLK4p/4n each pin will be the following state.
CLK4_x[1:0]＝‘01’/‘10’/‘11’：CLK4ｐ/4n ＝ ‘L’/‘L’，‘H’/‘H’，‘Hi-Z’/‘Hi-Z
CLKn_x [1:0]
CLKn Output State
00
CLK Enabled
01
Disable to Low
10
Disable to High
11
Disable to Hi-z
(n=1～4、x=0～7)
Sep -12
draft-E-06
- 26 -
AK8140A
●Address：0Ch
Address
0Ch
Data
D7
D6
D5
D4
D3
D2
D1
D0
MUX1[1]
MUX1[0]
MUX2[1]
MUX2[0]
MUX3[1]
MUX3[0]
MUX4[1]
MUX4[0]
MUXn [1:0] ： CLK1～4 Output Clock Source Selection
Select output clock signal source of CLK1-4.
MUXn [1:0]
CLKn Output Clock Source
00
-
*1
01
Input Bypass
10
PLL1 output（fvco1）
11
PLL2 output (fvco2)
(n=1～4)
*1 This setting(MUXn=’00’) is prohibited.
●Address：0Dh～13h
Address
0Dh
0Eh
0Fh
10h
11h
12h
13h
Data
D7
D6
D5
D4
Reserved
Reserved
Reserved
Reserved
D3
D2
D1
D0
CLK1
DIV2_
ODIV_1
ODIV_1
MOD
BYPASS1
[9]
[8]
ODIV_1
ODIV_1
ODIV_1
ODIV_1
ODIV_1
ODIV_1
ODIV_1
ODIV_1
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Reserved
Reserved
CLK3
CLK2
DIV2_
DIV2_
ODIV_2
ODIV_2
MOD
MOD
BYPASS3
BYPASS2
[9]
[8]
ODIV_2
ODIV_2
ODIV_2
ODIV_2
ODIV_2
ODIV_2
ODIV_2
ODIV_2
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
ODIV_3
ODIV_3
ODIV_3
ODIV_3
ODIV_3
ODIV_3
ODIV_3
ODIV_3
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Reserved
Reserved
Reserved
Reserved
CLK4
DIV2_
ODIV_4
ODIV_4
MOD
BYPASS4
[9]
[8]
ODIV_4
ODIV_4
ODIV_4
ODIV_4
ODIV_4
ODIV_4
ODIV_4
ODIV_4
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
draft-E-06
Sep -12
- 27 -
AK8140A
ODIVn Dividing Value Setting （ODIV_n/DIV2_BYPASSn）
The Dividing value of ODIVn is decided by “Frequency setting procedure” on page 10.
(1)The case ODIVn divides the clock signal of Input Bypass. (MUXn = ‘01’)
Set ODIVn dividing value according to explanation below, when ODIVn divides a clock signal
of Input Bypass.
ODIVn configuration is as the following Figure.
ODIVn
-2Divider
CLKn
ODIV_n
*ODIVn is calculated number by “Frequency setting procedure” on page 10.
・When set ODIVn dividing Value = 2 or odd number：
→Bypass ODIVn_2 Divider ,ODIV_n is the same number as ODIVn
Example1：ODIVn=3
Bypass ODIVn_2 Divider (DIV2_BYPASSn = ‘1’)
ODIV_n = ODIVn=3
・When set ODIVn dividing Value even number beyond 4
→Using ODIVn_2 Divider, ODIV_n = ODIVn/2
DIV2_Bypassn
ODIV_n
Example1：ODIVn=10
(0Dh-13h)
(0Dh-13h)
Bypass ODIVn_2 Divider (DIV2_BYPASSn = ‘0’)
ODIV_n = ODIVn/2 =5
（2）The case ODIVn divides clock signal of PLL1 or PLL2 (MUXn =’10’ or ‘11’)
Set ODIVn dividing value according to explanation below, when ODIVn divides clock signal
of PLL1 or PLL2
・When ODIVn divides fvco1 （MUXn=’10’）：
→ODIVn = ODIVn (calculated value )/2
・When ODIVn divides fvco2 （MUXn=’10’）：
→ODIVn = ODIVn (calculated value )
Sep -12
draft-E-06
- 28 -
AK8140A
ODIV_n[9:0] ： ODIV_n dividing value Control
(n=1,2,4)
Set ODIV_n（n=1,2,4）dividing value of ODIV1,2,4 as blow.
ODIV_n[9:0]
(n=1,2,4)
Dividing Value
00 0000 0000
1
00 0000 0001
2
00 0000 0010
3
：
11 1111 1111
1024
ODIV_3[7:0] ： ODIV_3 dividing value Control
Set ODIV_3 dividing value of ODIV3 as blow
ODIV_3[7:0]
Dividing Value
0000 0000
1
0000 0001
2
0000 0010
3
：
1111 1111
256
DIV2_BYPASSn (n=1～4)
DIV2_BYPASSn selects whether ODIVn_2divider used.（n=1-4）
DIV2_BYPASSn
ODIVn_2Divider
0
Use the 2divider
1
Bypass the
2 divider
※ Effective only when MUXn(n=1～4)=‘00’/‘01’
draft-E-06
Sep -12
- 29 -
AK8140A
CLKnMOD ： CLKn(n=1-3) Output Buffer Drivability Setting
“CLKnMOD” set the drivability of Output Buffer of CLKn as the following table. (n=1～3)
CLKnMOD
CLKn Drivability
High
0
Recommended when VDDO1,2=1.8V
Low
1
Recommended when VDDO1,2=3.3V
(n=1～3)
CLK4MOD ： CLK4 Output Buffer Drivability Setting
“CLK4MOD” set the drivability of Output Buffer of CLK4 as the following table.
CLK4MOD
CLK4 Drivability
High
0
Recommended when VDDO2=1.8V
Low
1
Recommended when VDDO2=3.3V
Sep -12
draft-E-06
- 30 -
AK8140A
■PLL1 Configuration Register
Data
Address
Remarks
20h
D7
D6
D5
D4
D3
D2
D1
D0
FS1_0
FS1_1
FS1_2
FS1_3
FS1_4
FS1_5
FS1_6
FS1_7
0
0
0
Reserved
Reserved
Reserved
－
－
FRAC0
FRAC0
[17]
[16]
0
0
0
0
0
INPUT
VCO1_
VCO1_
VCO1_
VCO1_
_CK1
RANG0[1]
RANG0[0]
RANG1[1]
RANG1[0]
0
0
0
0
0
－
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
－
－
－
－
－
－
0
0
FRAC0
FRAC0
FRAC0
FRAC0
FRAC0
FRAC0
FRAC0
FRAC0
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
0
0
0
0
0
0
0
0
FRAC0
FRAC0
FRAC0
FRAC0
FRAC0
FRAC0
FRAC0
FRAC0
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
Reserved
INT0[6]
INT0[5]
INT0[4]
INT0[3]
INT0[2]
INT0[1]
INT0[0]
－
0
0
0
0
0
0
0
MDIVC0
MDIVC0
MDIVC0
MDIVC0
MDIVP0
MDIVP0
MDIVP0
MDIVP0
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FRAC1
FRAC1
[17]
[16]
－
－
－
－
－
－
0
0
FRAC1
FRAC1
FRAC1
FRAC1
FRAC1
FRAC1
FRAC1
FRAC1
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
0
0
0
0
0
0
0
0
FRAC1
FRAC1
FRAC1
FRAC1
FRAC1
FRAC1
FRAC1
FRAC1
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0
0
0
0
0
0
0
0
Reserved
INT1[6]
INT1[5]
INT1[4]
INT1[3]
INT1[2]
INT1[1]
INT1[0]
－
0
0
0
0
0
0
0
MDIVC1
MDIVC1
MDIVC1
MDIVC1
MDIVP1
MDIVP1
MDIVP1
MDIVP1
[3]
[2]
[1]
[0]
[3]
[1]
[0]
0
0
0
0
0
0
0
21h
23h
24h
26h
27h
28h
29h
2Ah
PLL1 Input Clock
Selection
fVCO1 Range
22h
25h
PLL1 Frequency
Selection
2Bh
draft-E-06
[2]
0
PLL1_0
NDIV1 Fractional
Part Setting
PLL1_0
NDIV1 Integral Part
Setting
PLL1_0
MDIV1 Setting
PLL1_1
NDIV1 Fractional
Part Setting
PLL1_1
NDIV1 Integral Part
Setting
PLL1_1
MDIV1 Setting
Sep -12
- 31 -
AK8140A
PLL1 Configuration Register
PLL1 Block Diagram is as the following Figure.
Please set PLL１ parameter according to .
PLL1 has two Frequency mode predefined as PLL1_0 or PLL1_1 and selected by S0/S1/S2 pin
or S[2:0] bits (Address:00h). Refer to Programmable Control pin setting on page 14 for more
information about Frequency selection.
PLL1
Input CLK
(21h)
MDIV1 Setting
NDIV1 Setting
fVCO1 range
(26h/28h)
(22h-25h, 27h-2Ah)
(21h)
Figure PLL1 Block Diagram
●Address：20h
Address
20h
PLL１Output Frequency selection
Data
D7
D6
D5
D4
D3
D2
D1
D0
FS1_0
FS1_1
FS1_2
FS1_3
FS1_4
FS1_5
FS1_6
FS1_7
FS1_x（x=0～7） ： PLL１Output Frequency selection
The output frequency of PLL is chosen from two setups ，PLL1_0 and PLL1_1.
FS1_x
0
1
PLL1 Frequency
PLL1_0
Predefined by address:21h, 22h～26h
PLL1_1
Predefined by address:21h, 27h～2Bh
Sep -12
draft-E-06
- 32 -
AK8140A
●Address：2１h
Address
21h
PLL１ Input Clock Selection/ fVCO1 range
Data
D7
D6
D5
D4
D3
INPUT
VCO1
VCO1
VCO1
VCO1
_CK1
_RANG0[1]
_RANG0[0]
_RANG1[1]
_RANG1[0]
D2
D1
D0
－
－
－
INPUT_CK1 ： PLL1Input Clock Selection (MUX5)
INPUT_CK1
PLL1Input Clock
Input Clock
（Crystal Oscillation
or
External clock input）
fvco2
PLL2 output clock
0
1
VCO1_RANGEn[1:0] ： fVCO1 range selection
n=0/1
“VCO1_RANGEn[1:0]” selects the fVCO1 frequency range. fVCO1 frequency can be set
according to Frequency Setting Procedure on page 10.
VCO1_RANGEn[1:0]
00
01
10
11
fVCO1 range
fVCO1 < 300MHz
300MHz <= fvco1 <
370MHz
370MHz <= fvco1
370MHz <= fvco1
●Address：22h/28h、23h/29h、24h/2Ah
Address
22h
27h
23h
28h
24h
29h
D7
D6
NDIV1 fractional part setting
Data
D5
D4
D3
D2
D1
D0
FRACn[17]
FRACn[16]
FRACn[15]
FRACn[14]
FRACn[13]
FRACn[12]
FRACn[11]
FRACn[10]
FRACn[9]
FRACn[8]
FRACn[7]
FRACn[6]
FRACn[5]
FRACn[4]
FRACn[3]
FRACn[2]
FRACn[1]
FRACn[0]
FRACn[17:0] settings are updated after writing register 24h/20h.
Setting procedure should be (1)22h/27h ,( 2)23h/28h, and then (3)24h/29h
FRACn [17:0] ： NDIV1 fractional part setting n=0/1
NDIV1 fractional part can be set according to Frequency Setting Procedure on page 10.
Fractional part of N is expressed by A/218. Here, the numerator A is defined by FRAC bits. FRAC
is treated as 2’s Complement which is able to set from -217 up to +217. Consequently, it is
possible to set from -0.5 to +0.5 for fractional part of N.
draft-E-06
Sep -12
- 33 -
AK8140A
FRACn [17:0]
●Address：25h/2Ah
Address
25h
2Ah
A
Fractional Part
01 1111 1111 1111 1111
01 1111 1111 1111 1110
+131071
+131070
0.49999619..
01 0000 0000 0000 0000
+65536
0.25
00 0000 0000 0000 0001
00 0000 0000 0000 0000
11 1111 1111 1111 1111
11 1111 1111 1111 1110
+1
0
-1
-2
0.00000381..
0
-0.00000381..
11 0000 0000 0000 0000
-65536
-0.25
10 0000 0000 0000 0001
10 0000 0000 0000 0000
-131071
-131072
-0.49999619..
-0.5
NDIV1 integral part settings
*n=0/1
Data
D7
D6
D5
D4
D3
D2
D1
D0
－
INTn[6]
INTn[5]
INTn[4]
INTn[3]
INTn[2]
INTn[1]
INTn[0]
INTn [6:0] ： NDIV1 integral part settings
n=0/1
NDIV1 Integral part can be set according to Frequency Setting Procedure on page 10.
* Do not set any value except ”17”～”68”
INTn [6:0]
integral part
Prohibited
17
18
000 0000～001 0000
001 0001
001 0010
100 0011
100 0100
100 0101～111 1111
67
68
-*1
Sep -12
draft-E-06
- 34 -
AK8140A
●Address：26h/2C MDIV1 Setting
Address
26h
2Bh
*n=0/1
Data
D7
D6
D5
D4
D3
D2
D1
D0
MDIVCn[3]
MDIVCn[2]
MDIVCn[1]
MDIVCn[0]
MDIVPn[3]
MDIVPn[2]
MDIVPn[1]
MDIVPn[0]
MDIV1 Dividing Value Settings（MDIVCn， MDIVPn）
MDIV1Configuration is as the following Figure.
MDIV1 Dividing Value can be set according to Frequency Setting Procedure on page 10.
MDIVCn[2]
MDIV1
PLL1
Input CLK
SEL
1/2
1/2
1/3 or 1/4
SEL
1/2
Phase
Comparator
Programmable
Div.
MDIVCn[3:0]
MDIVPn[3:0]
MDIVCn[1:0]
Figure MDIV1Configuration
*n=0/1
MDIVCn[3] ： Programmable divider input selection
MDIVCn[3]
Input of Programmable divide
0
PLL1 Input CLK
1
PLL1 Input CLK 1/2
MDIVCn[2] ： 3or4 divider selection
MDIVCn[2]
0
1
*n=0/1
Selected divider
3 divider
4 divider
*n=0/1
MDIVCn[1:0] ： Input of Phase comparator selection
MDIVCn[1:0]
Input of Phase comparator
00
PLL1 Input CLK
01
PLL1 Input CLK 1/2
10
3 or4 divider output
11
Programmable divider Output
※Set MDIVCn[1:0]=‘11’, when INPUT_CK1 is set to‘1’(Address=21h)
draft-E-06
Sep -12
- 35 -
AK8140A
*n=0/1
MDIVPn[3:0] ： Programmable divider control
MDIVPn[3:0] Programmable Divider dividing value
0000
prohibited
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
10
1010
11
1011
12
1100
13
1101
14
1110
15
1111
16
Sep -12
draft-E-06
- 36 -
AK8140A
PLL2 Configuration Register
Data
Address
30h
Remarks
D7
D6
D5
D4
D3
D2
D1
D0
FS2_0
FS2_1
FS2_2
FS2_3
FS2_4
FS2_5
FS2_6
FS2_7
0
0
0
0
0
0
0
0
VCO2_RA
VCO2_RA
Reserved
Reserved
MDIV0[2]
MDIV0[1]
MDIV0[0]
31h
Reserved
NGE0[1]
NGE0[0]
PLL2 Frequency
Selection
PLL2_0
MDIV2Setting
fVCO2 Range
32h
33h
34h
35h
0
0
0
0
0
0
0
0
NINT0[5]
NINT0[4]
NINT0[3]
NINT0[2]
NINT0[1]
NINT0[0]
NUME0[8]
NUME0[7]
0
0
0
0
0
0
0
0
NUME0[6]
NUME0[5]
NUME0[4]
NUME0[3]
NUME0[2]
NUME0[1]
NUME0[0]
DENO0[8]
0
0
0
0
0
0
0
0
DENO0[7]
DENO0[6]
DENO0[5]
DENO0[4]
DENO0[3]
DENO0[2]
DENO0[1]
DENO0[0]
0
0
0
0
0
0
0
0
VCO2_RA
VCO2_RA
Reserved
Reserved
MDIV1[2]
MDIV1[1]
MDIV1[0]
Reserved
NGE1[1]
NGE1[0]
PLL2_0
NDIV2 Setting
PLL2_1
MDIV2Setting
fVCO2 Range
36h
0
0
0
0
0
0
0
0
NINT1[5]
NINT1[4]
NINT1[3]
NINT1[2]
NINT1[1]
NINT1[0]
NUME1[8]
NUME1[7]
0
0
0
0
0
0
0
0
NUME1[6]
NUME1[5]
NUME1[4]
NUME1[3]
NUME1[2]
NUME1[1]
NUME1[0]
DENO1[8]
0
0
0
0
0
0
0
0
DENO1[7]
DENO1[6]
DENO1[5]
DENO1[4]
DENO1[3]
DENO1[2]
DENO1[1]
DENO1[0]
0
0
0
0
0
0
0
0
37h
PLL2_1
NDIV2 Setting
38h
draft-E-06
Sep -12
- 37 -
AK8140A
PLL2 Configuration Register
PLL2 Block Diagram is as the following Figure.
Please set PLL2 parameter according to. Frequency Setting Procedure on page 10.
PLL2 has two Frequency mode predefined as PLL2_0 or PLL2_1 and selected by S0/S1/S2 pin or
S[2:0] bits (Address:00h). see on page 10more information about Frequency selection.
fin2
MDIV2 Setting
NDIV2 Setting
fVCO2 range
(31h/35h)
(32h-34h/36h-38h)
(31h/35h)
Figure PLL2 Block Diagram
●Address：30h
Address
30h
PLL2 Output Frequency selection
Data
D7
D6
D5
D4
D3
FS2_0
FS2_1
FS2_2
FS2_3
FS2_4
D2
D1
D0
FS2_5
FS2_6
FS2_7
FS2_x (x=0～7)： PLL１Output Frequency selection
The output frequency of PLL2 is chosen from two setups，PLL2_0 or PLL2_1.
FS2_x
0
1
PLL2 Frequency
PLL2_0
Predefined by address:31h～34h
PLL2_1
Predefined by address:35h～38h
Sep -12
draft-E-06
- 38 -
AK8140A
●Address：31h/35h
Address
31h
35h
MDIV2 and fVCO2 frequency range Setting
Data
D6
D5
D4
D3
D2
D7
Reserved
Reserved
MDIVn[2]
MDIVn[1]
MDIVn[0]
VCO2_RANGEn[1]
MDIVn[2:0] ：MDIV2Dividing Value Settings
*n=0/1
D1
D0
VCO2_RANGEn[0]
－
*n=0/1
MDIV1Configuration is as the following Figure.
MDIV1 Dividing Value can be set according to Frequency Setting Procedure on page 10.
MDIV2
SEL
XIN input
Phase
Comparator
力
MDIVn[2:0]
Figure MDIV2 configuration
MDIVn[2:0]
000
001
010
011
100
Except
the above
MDIV2 Dividing Value
1
2
4
8
16
prohibited
（Device is Reseｔ）
VCO2_RANGEn[1:0] ： fVCO2 range selection
*n=0/1
“VCO2_RANGEn[1:0]” selects the fVCO2 frequency range. fVCO2 frequency can be set
according to Frequency Setting Procedure on page 10.
VCO2_RANGEn[1:0]
00
01
10
11
fVCO2 range
fvco < 117.5MHz
117.5MHz <= fvco <
155MHz
155MHz <= fvco <
192.5MHz
192.5MHz <= fvco
draft-E-06
Sep -12
- 39 -
AK8140A
●Address：32h～34h、36h～38h
*n=0/1
Address
NDIV2 Dividing Value
Data
D7
D6
D5
D4
D3
D2
D1
D0
NINTn[5]
NINTn[4]
NINTn[3]
NINTn[2]
NINTn[1]
NINTn[0]
NUMEn[8]
NUMEn[7]
NUMEn[6]
NUMEn[5]
NUMEn[4]
NUMEn[3]
NUMEn[2]
NUMEn[1]
NUMEn[0]
DENOn[8]
DENOn[7]
DENOn[6]
DENOn[5]
DENOn[4]
DENOn[3]
DENOn[2]
DENOn[1]
DENOn[0]
32h
36h
33h
37h
34h
38h
After writing register 34h, 32h～34h data settings are updated.
After writing register 38h, 36h～38h data settings are updated.
NDIV2 Dividing Value （NINTn， NUMEn， DENOn）
NDIV2 dividing value can be set according to Frequency Setting Procedure on page 10.
NINTn[5:0] ： NDIV2 integral part settings
*n=0/1
NINTn[5:0]
000000 ～
001111
010000
NDIV2 Integral Part
：
：
100011
35
100100
100101
36
37
：
111001
111010 ～
111111
：
57
prohibited
16
prohibited
NUMEn[8:0] ： NDIV2 Numerator of fractional part setting
NUMEn[8:0]
*n=0/1
NDIV2 Numerator of
fractional part setting
000000000
0（fractional-part=0）
000000001
1
：
：
111111110
510
111111111
511
Sep -12
draft-E-06
- 40 -
AK8140A
DENOn[8:0] ： NDIV2 Denominator of fractional part setting
DENOn[8:0]
*n=0、1
NDIV2 Denominator of
fractional part setting
000000000
prohibited
000000001
1
：
：
111111110
510
111111111
511
draft-E-06
Sep -12
- 41 -
AK8140A
Crystal Unit
DAISHINKU Corp. DSX321G
Item
Symbol
MIN.
TYP.
MAX.
Unit
Remark
MHz
CL=8pF
Nominal frequency
f0
25.000
Equivalent resistance
R1
18.2
Shunt capacitance
C0
1.22
pF
Motional capacitance
C1
4.724
fF
Motional inductance
L1
8.585
mH
30
uW
Drive Level
L1
60
R1
Ω
±2 uW
C1
Crystal unit
C0
Load capacitance CL
CL
Figure Equivalent parameter and load
capacitance
Sep -12
draft-E-06
- 42 -
AK8140A
Package Information
7.8±0.10
0.15±0.05
13
1
6.40±0.15
4.40±0.10
0.6±0.10
24
12
0.25±0.05
0.65
0°～8°
S
0.10±0.05
0.10
S
12
(2.74)
1
1.10 MAX
0.90±0.05
24
13
(4.54)
draft-E-06
Sep -12
- 43 -
AK8140A
Marking
a: #1 Pin Index
b: Part number
c: Date code (6 digits)
24
13
b
AK8140A
xxxxxx
c
a
12
1
Sep -12
draft-E-06
- 44 -
AK8140A
RoHS Compliance
All integrated circuits form Asahi Kasei Microdevices Corporation (AKM)
assembled in “lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKM are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
IMPORTANT NOTICE
These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales
office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current
status of the products.
Descriptions of external circuits, application circuits, software and other related information
contained in this document are provided only to illustrate the operation and application
examples of the semiconductor products. You are fully responsible for the incorporation of
these external circuits, application circuits, software and other related information in the design
of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for
infringement of any patent, intellectual property, or other rights in the application or use of
such information contained herein.
Any export of these products, or devices or systems containing them, may require an export
license or other official approval under the law and regulations of the country of export
pertaining to customs and tariffs, currency exchange, or strategic materials.
AKM products are neither intended nor authorized for use as critical components Note1) in any
safety, life support, or other hazard related device or systemNote2), and AKM assumes no
responsibility for such use, except for the use approved with the express written consent by
Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it,
and which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to
function or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of,
or otherwise places the product with a third party, to notify such third party in advance of the
above content and conditions, and the buyer or distributor agrees to assume any and all
responsibility and liability for and hold AKM harmless from any and all claims arising from the
use of said product in the absence of such notification.
draft-E-06
Sep -12
- 45 -