AKM AK8181D

AKD8181D
AKD8181D
AK8181D Evaluation Board
The AKD8181D is an evaluation board for AK8181D. Therefore, it is easy to evaluate DC/AC
characteristics and confirm product functions.
-
SMA terminal of the differntial input
Enable to construct input load circuit for interface
Enable to construct three types of output load circuit
Preparing terminal and land pattern for VDD/VSS/VDD-2V
CLK_SEL and CLK_EN control switch
Power
There are the foll
※If you have con
-
Clock input
Input
CLK_EN
SW
CLK_SEL
SW
VSS
Pattern
VDD
VDD-2V
PCLK0p/n
Input
Output
Load
PCLK1p/n
Input
Input
Interface
Load
AKD8181D-E-00
Output pin
Pattern
Q0-3/Q0n-3n
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2012/12
AKD8181D
Power
There are the following three power supplies.
※If you have configured a termination circuit with resistor only (Pattern B or C), it becomes possible to
evaluate even without applying power to the VDD-2V terminal.
- VDD
The core power supply of AK8181D (3.3V)
- VSS
The core power supply of AK8181D (GND)
- VDD-2V
Power supply for the end of the output load resistor (=VDD-2V)
Note) GND of the SMA terminal is connected to the VSS inside the substrate.
Clock input
AK8181D inputs the clock selected by CLK_SEL switch. (Differential input or LVPECL)
The clock input signal can terminate if needed.
Input load circuit for interface
It can construct interface load circuit for input differential clock.
Examples are shown below.
The state of initial shipment is 【Pattern c】.
Pattern a
Zo=50Ω
NC:No components
VSS
Zo=50Ω
VSS
Pattern b
Zo=50Ω
VSS
Zo=50Ω
VSS
AKD8181D-E-00
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2012/12
AKD8181D
Pattern c
Zo=50Ω
VSS
0Ω
Zo=50Ω
VSS
Pattern d
Zo=50Ω
VSS
0Ω
Zo=50Ω
VSS
Pattern e
Zo=50Ω
VSS
50Ω
Zo=50Ω
VSS
AKD8181D-E-00
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2012/12
AKD8181D
Output load circuit
It can terminate by the following three methods. (Pattern A/B/C)
The state of initial shipment is 【Pattern A】.
Pattern A
Q0,1,2,3
※with applying power to the VDD-2V terminal
Zo=50Ω
short
Q0N,1N, Zo=50Ω
2N,3N
Pattern B
Q0,1,2,3
Zo=50Ω
short
※without applying power to the VDD-2V terminal
0Ω
0Ω
Q0N,1N, Zo=50Ω
2N,3N
Pattern C
Q0,1,2,3
Zo=50Ω
0Ω
※without applying power to the VDD-2V terminal
0Ω
RTT
0.1uF
Q0N,1N, Zo=50Ω
2N,3N
0Ω
※  =
AKD8181D-E-00
1

(( + )/( − 2)) 0
4
2012/12
1
2
AK8181D_Evaluation_Board
3
4
5
5mm x 5mm
T P1
CLK_EN
P6
TP
CLK_EN
H
L
1
2
3
Zo=50
Open
49.9
TP
1
R11
P11
Zo=50
49.9
1
TP
R19
Open
Zo=50
Open
5
4
3
2
1
Zo=50
R23
P4
TP
R24
Open
VDD
Q0
Q0N
VDD
Q1
Q1N
Q2
Q2N
VDD
Q3
Q3N
C1
C2
0.01u
0.1u
C5
R34
49.9
0.01u
P24
VDD-2V
5mm x 5mm
1
P14
VDD
R25
0
P22
C3
0.01u
C4
Zo=50
R26
R29
Open
C9
0.1u
R27
Open
P16
Open
TP
C12 Open
R30
R31
Open
49.9
R32
TP
VDD
Open
P17
1
1
Zo=50
1
R28
C6
0.1u
P15
Zo=50
49.9
0.1u
VDD
R35 0
TP
Zo=50
1
5
4
3
2
R33
Open
B
P13
1
TP
1
Zo=50
Open
VSS
CLK_EN
CLK_SEL
PCLK0p
PCLK0n
PCLK1p
PCLK1n
NC
NC
VDD
20
19
18
17
16
15
14
13
12
11
R16
Open
49.9
TP
TP
R22
AK8181D
TP
IC1
1
2
3
4
5
6
7
8
9
10
R17
VDD
Open
R15
Open
TP
C11 Open
R21
49.9
0.1u
1
VDD
P3
Open
C8
P12
VDD
0
R14
R13
Open
1
5
4
3
2
R18
49.9
1
TP
1
Zo=50
R12
1
P9
1
P10
P2
R20
SMA4
PCLK1p
R7
R6
0
B
SMA3
PCLK0n
R5
Open
Open
CLK_SEL
Zo=50
1
SMA2
PCLK0p
VDD
Zo=50
TP
3
1
2
3
R3
Open
R10
CLK_SEL
1
P23
VDD-2V
TP
0.1u
TP
5
4
3
2
R9
T P2
CLK_SEL
SW2
VDD
Zo=50
R8
49.9
H:PCLK1p,PCLK1n
L:PCLK0p,PCLK0n
1
A
TP
Zo=50
R2
Open
Open
C7
P8
1
1
P7
Zo=50
49.9
R4
P1
A
SMA1
CLK_EN
R1
CLK_EN
1
VDD
H:ON
L:OFF
1
TP
1
SW1
TP
Zo=50
C
1
Zo=50
Open
R37
49.9
5
4
3
2
SMA5
PCLK1n
R36
1
TP
P5
C
TP
P18
R38
49.9
R39
R41
SW3
P20
3
1
2
3
OE
Zo=50
R44
VDD
Open
0.1u
R42
Open
TP
OE
1
TP
R40
Open
Open
1
49.9
R43
Open
P21
1
1
VDD
C10
P19
Zo=50
1
Zo=50
Zo=50
TP
P25
VDD-2V
T P3
OE
D
5mm x 5mm
D
1
TP
H:EN
L:DIS
T itle
AK8181D_Evaluation_Board
Size
A3
Date:
1
2
3
4
Document Number
Rev
1.0
AK8181D
T uesday, February 26, 2013
Sheet
5
1
of
2
5
4
3
2
1
D
D
P26
VDD-2V
P27
5mm x 5mm
1
1
VDD
TP
5mm x 5mm
C
5mm x 5mm
1
TP
TP
VDD-2V
C
P28
VSS
VDD
TP4
VDD-2V
TP5
C13
C14
22u
TP6
VDD
VSS
C15
22u
1u
B
B
A
A
Title
AK8181D_Evaluation_Board
Size
A
Date:
5
4
3
Document Number
Rev
1.0
Power
Monday, December 03, 2012
2
Sheet
2
of
1
2