AKM AKD7719

[AK7719B]
AK7719B
Low Power DSP for Voice and Audio Processing
1. General Description
The AK7719B is a highly integrated digital signal processor (DSP) with five digital interface ports.
The built-in asynchronous sample rate converter (SRC) enables flexible connectivity in various
system configurations. AKM’s DSP core is optimized for both narrowband and wideband voice
processing, as well as full bandwidth digital audio processing. An integrated clock generator for the
DSP master clock eliminates the need for external clocks. The RAM-based DSP can be
programmed for user requirements. The AK7719B is housed in a 30-pin CSP package. It is a very
low power device, suitable for mobile applications.
2. Features
□ Embedded DSP
- Flexible programming with built-in program and data memories
- Hardware accelerator
- Word length: 24-bits (Data RAM 24-bit floating point)
- Multiplier 20 x 20  40-bits (double precision available)
- Divider 20 / 20  20-bits
- ALU: 44-bit arithmetic operation (with 4-bit overflow margin)
24-bit floating point arithmetic and logic operation
- Program RAM: 4096w x 36-bits
- Coefficient RAM: 2048w x 20-bits
- Data RAM: 2048w x 24-bits (24-bit floating point)
- Offset Register: 32w x 15-bits
- Delay RAM: 16384w x 24-bits(24-bit floating point)
- 5625 steps at 16kHz sampling rate, 1875 steps at 48kHz sampling rate
- Internal clock generator
□ Audio Interface Format
- Left justified, PCM, I2S,
- 16/24bit linear
- Sampling rate 8kHz ~ 48kHz
- Up/Down Sampling Rate Converter: Port#1 (8kHz ↔ 16kHz)
□ Asynchronous Sample Rate Converters
□ μC I/F: I2C-Compatible, SPI
□ Operational, Sleep and Power-down Modes
□ Power Supply
VDD (DSP Core): 1.2V ±0.1V
TVDD (PCM I/F): 1.6V ~ 3.6V
□ Operating Temperature Range: -40C ~ 85C
□ Package: 30-Pin WL-CSP (2.94mm x 3.14mm, 0.5mm pitch)
□ Power Consumption: 9.2mA (11mW) typ. (Narrowband Handset mode operation)
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[AK7719B]
3. Table of Contents
1. General Description........................................................................................................................................1
2. Features ..........................................................................................................................................................1
3. Table of Contents............................................................................................................................................2
4. Block Diagram................................................................................................................................................3
■ Block Diagram...........................................................................................................................................3
■ DSP Block Diagram ..................................................................................................................................4
5. Pin Configurations and Functions ..................................................................................................................5
■ Ordering Guide ..........................................................................................................................................5
■ Pin Layout .................................................................................................................................................5
■ Pin Function ..............................................................................................................................................6
■ Handling of Unused Pins ...........................................................................................................................7
■ Pin States in Power-down Mode ...............................................................................................................7
6. Absolute Maximum Ratings ...........................................................................................................................8
7. Recommended Operation Condition ..............................................................................................................8
8. SRC Characteristics........................................................................................................................................9
9. DC Characteristics..........................................................................................................................................9
10. Power Consumption ...................................................................................................................................10
11. Filter Characteristics .................................................................................................................................. 11
■ SRC Block ...............................................................................................................................................11
12. Switching Characteristics ...........................................................................................................................12
■ System Clock ...........................................................................................................................................12
■ Reset and Power-down ............................................................................................................................12
■ Serial Data Interface ................................................................................................................................12
■ Timing Diagram ......................................................................................................................................13
■ μP Interface (SPI Mode) ..........................................................................................................................15
■ I²C Bus Interface .....................................................................................................................................17
15. Package .......................................................................................................................................................18
■ Material & Lead Finish ...........................................................................................................................18
16. Marking ......................................................................................................................................................19
17. Revision History .........................................................................................................................................19
IMPORTANT NOTICE .................................................................................................................................20
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4. Block Diagram
FILTER
■ Block Diagram
VSS
PDN
MUX1
UPDN
Rete
Conv.
UPDN
Rete
Conv.
[AK7719B]
TVDD
VDD
TEST
Slave
Port#1
SYNC5
BCLK5
SYNC1
SYNC
SDOUT5
SYNC
BCLK
BCLK
BCLK1
DIN2
SDIN1
SDOUT1
SRCAO
DIN1
SRCAI
DOUT2
SDOUT4/
GP1/STO/
RDY
SDIN5
DOUT1
SYNC2
BCLK2
DOUT4/GP1
WDT/CRC
SELSRC bit = “0”
SDOUT2
SDIN2
SYNC
BCLK
PCM Interface4
(Port#4)
Through
DOUT3/GP0
Slave
SDOUT3/GP0
DIN3
SYNC4
SYNC
BCLK
BCLK4
DIN4
SRCBI
SYNC3/JX1
JX0
BCLK3/JX0
AKM
DSP
Core
CGU
(CLK
Gen
Unit)
SDIN3
JX1
Control
Interface
DSPCLK
MUX1
Master (Port#1 domain)
Figure 1. Block Diagram (SELSRC bit = “0”)
VSS
PDN
TVDD
SCLK/CAD0
STO/RDY
SI/CAD1
CSN/SCL
Memory
SYNC1 domain
VDD
SO/SDA
SYNC1 domain
TEST
Port#2 SYNC domain
Port#1 SYNC domain
When MASTER port
Port#2/5
SYNC5
Port#1 SYNC domain
Slave
Port#1
BCLK5
UPDN
Conv
SYNC1
BCLK1
SDIN1
SDOUT1
SYNC
SDOUT5
BCLK
SYNC
BCLK
DIN2
DOUT1
SDIN5
Through
DIN1
DOUT2
SDOUT4/
GP1/STO/
RDY
SYNC4
SDIN4
SRCBI
1/6 or 1/3
48K→16K/8K
DOUT3/GP0
DIN4
DIN3
SDIN2
Port#3
SYNC3/JX1
BCLK3/JX0
SRCAO
SDOUT3/GP0
SRCAI
SDIN3
SELSRC
WDT/CRC
AKM
DSP
Core
CGU
(CLK
Gen
Unit)
M
(Outpu
SDOUT2
SELSRC bit = “1”
SYNC
BCLK
SYNC
BCLK
BCLK4
SYNC2
M
/Slav
BCLK2
DOUT4/GP1
WDT/CRC
Port#4
Slave
SELSRC
I2C
MUX2
SDIN4
(Port#3)
Port#3 SYNC domain
UPDN
Conv
Port#3 SYNC domain
Port#1 SYNC domain
Slave
1/6 or 1/3
48K→16K/8K
Port#2 SYNC domain
Port#1 SYNC domain
When MASTER port
Port#2/5
I2C
Control
Interface
DSPCLK
SCLK/CAD0
SI/CAD1
CSN/SCL
Memory
SO/SDA
Figure 2. Block Diagram (SELSRC bit = “1”)
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STO/RDY
[AK7719B]
■ DSP Block Diagram
Pointer
CP0, CP1
DP0, DP1
Coefficient RAM
Data RAM
Delay RAM
16384w x 24-Bit
2048w x 24-Bit
2048w x 20-Bit
Offset Reg
32w x 15-Bit
DLP0, DLP1
CBUS(20-Bit)
DBUS(24-Bit)
MPX20
Micon I/F
MPX20
X
Control
PRAM
DEC
Y
Serial I/F
4096w x 36-Bit
Multiply
20 x 20  40-Bit
PC
Stack: 5 levels(max)
24-Bit
40-Bit
TMP 12 x 24-Bit
PTMP(LIFO) 6 x 24-Bit
MUL
DBUS
2 x 16/24-Bit
DIN4
2 x 16/24-Bit
DIN3
2 x 16/24-Bit
DIN2
2 x 16/24-Bit
DIN1
ALU
2 x 16/24-Bit
DOUT4
44-Bit
2 x 16/24-Bit
DOUT3
2 x 16/24-Bit
DOUT2
2 x 16/24-Bit
DOUT1
SHIFT
44-Bit
40-Bit
A
B
Overflow Margin: 4-Bit
40-Bit
DR0  3
40-Bit
Coefficie
(ACR
1024w x
1024w x
Accelerator
Over Flow Data
Generator
Division 202020
Peak Detector
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[AK7719B]
5. Pin Configurations and Functions
■ Ordering Guide
-40  +85C
30-pin CSP (0.5mm pitch) Black type
Evaluation board for AK7719B
AK7719BECB
AKD7719
■ Pin Layout
Top View
6
6
5
5
4
4
3
3
2
INDEX
MARK
2
1
1
A
B
C
D
Bottom View
E
E
BCLK1
D
C
6
PDN
SDIN1
SDOUT1
5
VDD
BCLK3/
JX0
SDIN3
SDOUT3/
SYNC2
GP0
4
VSS
SYNC3/
JX1
TEST
SDOUT5
BCLK2
3
TVDD
I2C
SDIN4
SDOUT 4
/GP1/STO/
RDY
SDIN2
2
SI/CAD1
SCLK/
CAD0
CSN/
SCL
SO/SDA SDOUT2
1
BCLK4
SYNC4
SDIN5
BCLK5
SYNC5
A
B
C
D
E
B
A
SYNC1
TOP View
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[AK7719B]
■ Pin Function
No.
A5
A3
A4
Pin Name
VDD
TVDD
VSS
A6
PDN
E6
SYNC1
D6
BCLK1
B6
C6
SDIN1
SDOUT1
SDOUT4
GP1
STO
RDY
D3
E5
SYNC2
E4
BCLK2
E3
E2
B1
A1
C3
SDIN2
SDOUT2
SYNC3
JX1
BCLK3
JX0
SDIN3
SDOUT3
GP0
SYNC4
BCLK4
SDIN4
E1
SYNC5
D1
BCLK5
C1
E4
B3
SDIN5
SDOUT5
I2C
SCLK
CAD0
CSN
SCL
SO
SDA
SI
CAD1
TEST
B4
B5
C5
D5
B2
C2
D2
A2
C4
I/O
Function
- Core Power Supply Pin 1.2V
- I/O power Supply Pin 1.63.6V
- Ground Pin 0V
Power-Down Mode Pin
I
“H”: Power-up, “L”: Power-down, reset the control register.
The AK7719B must be reset once upon power-up.
I Frame Sync 1 pin
Serial Data Clock 1 Pin
I
AK7719B goes into stanby state when BCLK1 is not present.
I Serial Data Input 1 Pin
O Serial Data Output 1 Pin
O
I
O
I
O
I
O
I
I
I
O
I
I
I
I
O
I
O
I
O
I
I
I
Serial Data Output 4 Pin
(SELDO4[1:0] bits = “00”)
DSP Programmable output 1 Pin
(SELDO4[1:0] bits = “01”)
Status Output Pin (Active High)
(SELDO4[1:0] bits = “10”)
Data Write Ready output pin for control I/F
(SELDO4[1:0] bits = “11”)
Frame Sync 2 Pin (Internal Pull-down pin)
(PT25N bit = “0”)
Frame Sync 2 Pin
(PT25N bit = “1”)
Serial Data Clock 2 Pin (Internal Pull-down pin)
(PT25N bit = “0”)
Serial Data Clock 2 Pin
(PT25N bit = “1”)
Serial Data Input 2 Pin
Serial Data Output 2 Pin
(“L” output at PORTSEL25 bit= “1”)
Frame Sync 3 pin
(SELSRC bit = “1”)
Conditional Jump 1 Pin
(SELSRC bit = “0”)
Serial Data Clock 3 Pin
(SELSRC bit = “1”)
Conditional Jump 0 Pin
(SELSRC bit = “0”)
Serial Data Input 3 Pin
Serial Data Output 3 Pin
(SELDO3 bit = “0”)
DSP Programmable output 0 Pin
(SELDO3 bit = “1”)
Frame Sync 4 Pin
Serial Data Clock 4 Pin
Serial Data Input 4 Pin
Frame Sync 5 Pin (Internal Pull-down pin)
(PT25N bit = “0”)
Frame Sync 5 Pin
(PT25N bit = “1”)
Serial Data Clock 5 Pin (Internal Pull-down pin)
(PT25N bit = “0”)
Serial Data Clock 5 Pin
(PT25N bit = “1”)
Serial Data Input 5 Pin
Serial Data Output 5 Pin
( “L” output at PORTSEL25 bit= “0”)
Control Interface Mode Select Pin
Serial Clock Input pin
Slave Address 0 Input pin
Chip select pin
Control Interface clock input pin
Serial data output pin
“H”: I2C, “L”: SPI
SPI (I2C pin = “L”)
I 2C (I2C pin = “H”)
SPI (I2C pin = “L”)
I 2C (I2C pin = “H”)
SPI (I2C pin = “L”)
O
I/O Control Interface input/output acknowledge pin
I 2C (I2C pin = “H”)
Serial data input pin
SPI (I2C pin = “L”)
I
Slave Address 1 Input pin
I 2C(I2C pin = “H”)
I Test pin (pull-down resistor) must be connected to VSS.
Note 1. All input pins must not be allowed to float.
Note 2. I2C and CAD0/1 pins must be fixed to “L” (VSS) or “H” (TVDD).
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[AK7719B]
■ Handling of Unused Pins
Unused I/O pins must be connected appropriately:
Pin Name
,SDOUT3/GPO, SDOUT4/GP1/STO/RDY,
SDOUT5
SYNC2, BCLK2, SYNC5, BCLK5
SYNC3/JX1, BCLK3/JX0, SDIN3, TEST
SYNC4, BCLK4, SDIN4,
SYNC5, BCLK5, SDIN5,
Setting
Leave Open
Connect to VSS.
■ Pin States in Power-down Mode
The table below shows pin states when the PDN pin= “L”.
No.
C6
E5
E4
E1
D1
E2
D5
Pin Name
I/O (Note 3)
Power Down Pin State
SDOUT1
O
“L” Output
SYNC2
I/O
Input (internal pull-down)
BCLK2
I/O
Input (internal pull-down)
SYNC5
I/O
Input (internal pull-down)
BCLK5
I/O
Input (internal pull-down)
SDOUT2
O
“L” Output
SDOUT3
O
“L” Output
GP0
SDOUT4
GP1
D3
O
“L” Output
STO
RDY
D4
SDOUT5
O
“L” Output
SPI (I2C pin = “L”) “L” Output
SO
O
D2
SDA
I/O
I2C (I2C pin = “H”) Hi-z
Note 3. Indicates the pin attribute.
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[AK7719B]
6. Absolute Maximum Ratings
(VSS=0V; All voltages are with respect to ground.)
Parameter
Symbol
Power Supply Voltage (DSP Core)
VDD
Power Supply Voltage (Digital I/O)
TVDD
Input Current (except for power supply pins)
IIN
Input Voltage
VIND
Operating Ambient Temperature
Ta
Storage Temperature
Tstg
min
0.3
0.3
0.3
40
65
max
1.6
4.1
10
TVDD+0.3
85
150
Unit
V
V
mA
V
C
C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operation Condition
(VSS=0V; All voltages are with respect to ground.)
Parameter
Symbol
min
typ
max
Unit
Supply Voltage Range (DSP core)
VDD
1.1
1.2
1.3
V
Supply Voltage Range (I/Os)
TVDD
1.6
1.8
3.6
V
Note 4. The power-up sequence with VDD and TVDD is not critical. The PDN pin should be held “L” when
power is supplied. The PDN pin is allowed to be “H” after all power supplies are applied and settled.
Note 5. The external pull-up resistors at the SDA and SCL pins should be connected to TVDD voltage or less.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
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[AK7719B]
8. SRC Characteristics
(Ta= -40°C~85°C; VDD=1.2V, TVDD=1.8V; VSS=0V; Signal Frequency = 1kHz, data = 24bit;
Measurement Bandwidth = 20Hz~FSO/2kHz; unless otherwise specified.)
Parameter
Symbol
min
typ
max
Resolution
24
Input Sample Rate
FSI
8
48
Output Sample Rate
FSO
8
48
THD+N
(Input= 1kHz, 0dBFS)
FSO/FSI=48kHz/8kHz
-111
-103
FSO/FSI=16kHz/48kHz
-113
FSO/FSI=8kHz/48kHz
-113
Dynamic Range (Input= 1kHz, -60dBFS)
FSO/FSI=48kHz/8kHz
108
113
FSO/FSI=16kHz/48kHz
113
FSO/FSI=8kHz/48kHz
111
Dynamic Range (Input= 1kHz, -60dBFS, A-weighted)
FSO/FSI=8kHz/48kHz
110
Ratio between Input and Output Sample Rate
FSO/FSI
0.167
6
Unit
Bits
kHz
kHz
dB
dB
dB
dB
dB
dB
dB
dB
-
9. DC Characteristics
(Ta=-40ºC~85ºC; VDD=1.2V, TVDD =1.6V~3.6V; VSS =0V)
Parameter
Symbol
min
typ
max
Unit
2.2VTVDD3.6V
High level input
70%TVDD
VIH
V
voltage
1.6VTVDD<2.2V
VIH
80%TVDD
2.2VTVDD3.6V
Low level input
30%TVDD
VIL
V
voltage
1.6VTVDD<2.2V
VIL
20%TVDD
VOH
TVDD-0.2
V
High level inptu voltage Iout=-200A (Note 6)
VOL
0.2
Low level input voltage Iout= 200A (Note 6)
V
SDA low level output
TVDD ≥ 2.0V
0.4
V
VOL
voltage Iout=3mA
TVDD < 2.0V
20%TVDD
V
Input leak current
Iin
±10
A
Pull down resistance (Note 7)
Rpd
40
kΩ
Note 6. Except for the SDA pin.
Note 7. The SYNC2, BCLK2, SYNC5 and BCLK5 pins are internally pulled-down (PDS2 bit = PDS5 bit= “0”
(default)).
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[AK7719B]
10. Power Consumption
(Ta=25ºC; VSS =0V, unless otherwise specified.)
Parameter
min
typ
max
Unit
Power Supplies:
Power-Up (PDN pin = “H”)
Loopback mode (DSP reset mode, SRCA, B: Powe-down) Port1(fs=8kHz, I2S fin=1kHz, slave mode) to
Port2(master mode)
VDD
0.8
mA
VDD=1.2V
TVDD=1.8V
TVDD
0.6
mA
Power Consumption
2.1
mW
All Circuit Power-up (Note 9) (DSP, SRC power-up running at Port#1: fs=8kHz, Port#2/4: fs=48kHz)
VDD
36
mA
VDD=1.3V
TVDD=3.6V
TVDD
2
mA
Power Consumption
54
mW
Power-Down state (PDN pin = “L”), (Note 8)
VDD
2.4
8
A
VDD=1.2V
TVDD=1.8V
TVDD
0.2
1
A
Note 8. All digital input pins are fixed to TVDD or VSS.
Note 9. The current of VDD, TVDD changes depending on the system frequency and contents of the DSP
program.
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[AK7719B]
11. Filter Characteristics
■ SRC Block
(Ta= -40°C~85°C, VDD=1.1V~1.3V, TVDD=1.6~3.6V, VSS =0V)
Parameter
Symbol
min
typ
max
Unit
Passband -0.01dB 0.980≦FSO/FSI≦6.000
PB
0
0.4583FSI kHz
PB
0
0.4167FSI kHz
0.900≦FSO/FSI＜0.990
PB
0
0.2182FSI kHz
0.533≦FSO/FSI＜0.909
PB
0
0.2177FSI kHz
0.490≦FSO/FSI＜0.539
PB
0
0.1948FSI kHz
0.450≦FSO/FSI＜0.495
PB
0
0.1312FSI kHz
0.225≦FSO/FSI＜0.455
Passband -0.50dB 0.167≦FSO/FSI＜0.227
PB
0
0.0658FSI kHz
Stopband
SB
0.5417FSI
kHz
0.980≦FSO/FSI≦6.000
SB
0.5021FSI
kHz
0.900≦FSO/FSI＜0.990
SB
0.2974FSI
kHz
0.533≦FSO/FSI＜0.909
SB
0.2812FSI
kHz
0.490≦FSO/FSI＜0.539
SB
0.2604FSI
kHz
0.450≦FSO/FSI＜0.495
SB
0.1802FSI
kHz
0.225≦FSO/FSI＜0.455
SB
0.0970FSI
kHz
0.167≦FSO/FSI＜0.227
Passband Ripple
PR
±0.01
dB
0.225≦FSO/FSI≦6.000
PR
±0.50
dB
0.167≦FSO/FSI＜0.227
Stopband
0.450≦FSO/FSI≦6.000
SA
95.2
dB
Attenuation
SA
90.0
dB
0.167≦FSO/FSI＜0.455
Group Delay
52.5×Tsi
GD
Sec
(Note 10)
+ 9.5×Tso
Note 10. Group delay is a calculated time from a rising edge of SYNC at the input to a rising edge of SYNC at
the output.
SYNCI
SDTI
Tsi
SRC Block
SYNCO
SDTO
52.5×Tsi + 9.5×Tso
SYNCI
Lch
Rch
SDTI
SYNCO
Tso
Lch
Rch
SDTO
Figure 3. SRC Filter Group Delay (Left Justified)
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[AK7719B]
12. Switching Characteristics
■ System Clock
(Ta= -40ºC ~ 85ºC, VDD=1.2V, TVDD= 1.6V ~ 3.6V, VSS=0V); CL=20pF (except SDA pin) or 400pF (SDA
pin); unless otherwise specified)
Parameter
Symbol
min
typ
max
Unit
Normal Operation mode: SYNCx, BCLKx (x=1~5) Input Timing (Note 11)
Input Timing
SYNCx frequency
fs
8
48
kHz
BCLKx Input Timing (Note 12)
fBCLK
256
4096
kHz
BCLKx Pulse width Low
tBCKL
0.4 x tBCLK
ns
BCLKx Pulse width High
tBCKH
ns
0.4x tBCLK
Note 11. SYNCx and BCLKx (x=1~5) should be synchronized and their sampling rates (fs) should be stable
for each port.
Note 12. Required to meet the following expression: fBCLK ≥ 2 (Data length) × SYNCx frequency.
■ Reset and Power-down
(Ta= -40ºC ~ 85ºC, VDD=1.2V, TVDD= 1.6V ~ 3.6V, VSS=0V)
Parameter
Symbol
min
typ
PDN
(Note 13)
tPDN
600
Note 13. The AK7719B can be reset by bringing the PDN pin = “L” upon power-up.
max
Unit
ns
■ Serial Data Interface
(Ta= -40ºC ~ 85ºC, TVDD= 1.6V ~ 3.6V, VSS=0V, CL=20pF)
Parameter
Symbols
min
SDINx, SDOUTx (x = 1~5) (x=2, 5: slave mode)
Delay Time from BCLKx “↑” to SYNCx “↑” (Note 14)
tBSYD
20
Delay Time from SYNCx “↓” to BCLKx “↑” (Note 14)
tSYBD
100
Serial Data Input Latch Setup Time
tB1IDS
40
Serial Data Input Latch Hold Time
tB1IDH
40
Delay Time from SYNC1 to Serial Data Output
tSY1OD
Delay Time from BCLK1 “↓” to Serial Data Output (Note 15) tB1OD
SDIN2/5, SDOUT2/5 (master mode)
SYNC2 Duty cycle
Serial Data Input Latch Setup Time
tB2IDS
40
Serial Data Input Latch Hold Time
tB2IDH
40
Delay Time from SYNC2 to Serial Data Outputs
tSY2OD
Delay Time from BCLK2 “↓”to Serial Data Output (Note 16) tB2OD
SDIN1 → SDOUT2/5, SDIN2/5 → SDOUT1
Delay Time in Loopback Mode (Note 17)
tIOD
Note 14. When the polarity of BCLK1 is inverted, delay time is from BCLK1 “”
Note 15. When the polarity of BCLK1 is inverted, delay time is from BCLK1 “↑”.
Note 16. When the polarity of BCLK2 is inverted, delay time is from BCLK2 “↑”.
Note 17. When LPDO1 bit = “0”, LPDO2 bit = “0”
MS1565-E-00-PB
typ
max
Unit
40
40
ns
ns
ns
ns
ns
ns
40
40
%
ns
ns
ns
ns
60
ns
50
2013/11
12
[AK7719B]
■ Timing Diagram
1/fs
ts=1/fs
1/fs
SYNCx
VIH
VIL
1/fBCLK
1/fBCLK
tBCLK=1/fBCLK
VIH
BCLKx
VIL
Figure 4. System Clock (x=1~5)
PDN
tPDN
VIL
Figure 5. Power-down
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[AK7719B]
VIH
VIL
D
SYNCx
tBSYD
D
tSYBD
D
BCLKx
VIH
VIL
D
tB1IDS
D
tB1IDH
VIH
VIL
D
SDINx
tSY1OD
SDOUTx
D
D
tB1OD
D
50%TVDD
D
tIOD
D
SDINx
VIH
VIL
D
D
Figure 6. Serial Data Interface (x=1~5) (x=2, 5: slave mode)
SYNC2/5
50%TVDD
BCLK2/5
50%TVDD
tB2IDS
tB2IDH
VIH
VIL
D
SDIN2/5
tSY2OD
D
D
tB2OD
D
SDOUT2/5
50%TVDD
D
tIOD
D
SDIN1
VIH
VIL
D
D
Figure 7. Serial Data Interface (SDIN2/5, SDOUT2/5 master mode)
SDOUTy
50%TVDD
D
tIOD
D
SDINx
VIH
VIL
D
D
Figure 8. Serial Data Interface (x=1, y=2/5 or x=2/5, y=1: loopback mode)
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[AK7719B]
■ μP Interface (SPI Mode)
(Ta= -40ºC ~ 85ºC, VDD=1.2V; TVDD=1.6~3.6V, VSS =0V; CL=20pF)
Parameter
Symbol
min
μP Interface Timing (SPI mode)
SCLK Fall Time
tSF
SCLK Rise Time
tSR
SCLK Frequency
fSCLK
SCLK Low Level Width
tSCLKL
120
SCLK High Level Width
tSCLKH
120
CSN High Level Width
tWRQH
500
From CSN “↑” to PDN “↑”
tRST1
600
From PDN “↑” to CSN “↓”
tIRRQ
100
tWSC
500
From CSN “↓” to SCLK “↓”
From SCLK “↑” to CSN “↑”
tSCW
800
SI Latch Setup Time
tSIS
100
SI Latch Hold Time
tSIH
100
AK7719B → μP
Delay Time from SCLK “↓”to SO Output
tSOS
Hold Time from SCLK “↑” to SO Output (Note 18)
tSOH
100
Note 18. Except when input the eighth bit of the command code.
typ
max
Unit
30
30
4.0
ns
ns
MHz
ns
ns
ns
ns
s
ns
ns
ns
ns
100
ns
ns
tSR
tSF
VIH
SCLK
VIL
tSCLKL
tSCLKH
1/fSCLK
1/fSCLK
VIH
PDN
VIL
VIH
CSN
VIL
tRST1
tIRRQ
Figure 9. μP Interface 1 (SPI)
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[AK7719B]
VIH
CSN
tWRQH
VIL
VIH
SI
VIL
tSIH
tSIS
VIH
SCLK
VIL
tWSC
tSCW
tWSC
tSCW
Figure 10. μP Interface 2 (SPI)
VIH
SCLK
VIL
VIH
SO
VIL
tSOH
tSOS
Figure 11. μP Interface 3 (SPI)
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[AK7719B]
■ I²C Bus Interface
(Ta=-40ºC~85ºC, VDD=1.2V, VDD=1.6~3.6V, VSS =0V, CL=20pF)
Parameter
Symbol
min
I²C Timing
SCL clock frequency
fSCL
30
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first Clock pulse)
Clock Low Time
1.3
tLOW
Clock High Time
0.6
tHIGH
Setup Time for Repeated Start Condition
0.6
tSU:STA
SDA Hold Time from SCL Falling
0
tHD:DAT
SDA Setup Time from SCL Rising
0.1
tSU: DAT
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
0.6
tSU:STO
Pulse Width of Spike Noise Suppressed
tSP
0
by Input Filter
Capacitive load on bus
Cb
Note 19. I2C-bus is a trademark of NXP B.V.
typ
max
Unit
400
kHz
s
s
s
s
s
s
s
s
s
s
0.9
0.3
0.3
50
ns
400
pF
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
Figure 12. I2C Bus Interface
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[AK7719B]
13. Package
30pin CSP (Unit: mm)
30 -0.285 
 0.05 M C
0.03
Top View
(0.040±0.004)
 0.15 M
A
C
A B
3
4
7719B
3.14±0.03
5
6
B
1
E
A
D
C
B
0.5
1
2
XXXX
A
0.565±0.059
0.345±0.025
0.5
2.94±0.03
0.075 C
0.18±0.03
C
■ Material & Lead Finish
Package: Epoxy, Halogen (Br and Cl) free
Solder ball material: SnAgCu
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[AK7719B]
14. Marking
7719B
XXXX
1
A
XXXX: Date code (4 digit)
15. Revision History
Date (Y/M/D) Revision Reason
13/11/01
00
First Edition
Page
Contents
MS1565-E-00-PB
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19
[AK7719B]
Thank you for your access to AKM product information.
More detail product information is available, please contact our
sales office or authorized distributors.
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application of
AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants any
license to any intellectual property rights or any other rights of AKM or any third party with respect
to the information in this document. You are fully responsible for use of such information contained
in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR
ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF
SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including
but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry,
medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic
signaling equipment, equipment used to control combustions or explosions, safety devices, elevators
and escalators, devices related to electric power, and equipment used in finance-related fields. Do
not use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and safeguards
for your hardware, software and systems which minimize risk and avoid situations in which a
malfunction or failure of the Product could cause loss of human life, bodily injury or damage to
property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and
regulations. The Products and related technology may not be used for or incorporated into any
products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or
foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation,
the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth
in this document shall immediately void any warranty granted by AKM for the Product and shall not
create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
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