ADVANCED LINEAR DEVICES, INC. ALD1105 DUAL N-CHANNEL AND DUAL P-CHANNEL MATCHED MOSFET PAIR GENERAL DESCRIPTION APPLICATIONS The ALD1105 is a monolithic dual N-channel and dual P-channel complementary matched transistor pair intended for a broad range of analog applications. These enhancement-mode transistors are manufactured with Advanced Linear Devices' enhanced ACMOS silicon gate CMOS process. It consists of an ALD1116 N-channel MOSFET pair and an ALD1117 P-channel MOSFET pair in one package. The ALD1105 is a low drain current, low leakage current version of the ALD1103. • • • • • • • • • • The ALD1105 offers high input impedance and negative current temperature coefficient. The transistor pair is matched for minimum offset voltage and differential thermal response, and it is designed for precision signal switching and amplifying applications in +2V to +12V systems where low input bias current, low input capacitance and fast switching speed are desired. Since these are MOSFET devices, they feature very large (almost infinite) current gain in a low frequency, or near DC, operating environment. When used in complementary pairs, a dual CMOS analog switch can be constructed. In addition, the ALD1105 is intended as a building block for differential amplifier input stages, transmission gates, and multiplexer applications. The ALD1105 is suitable for use in precision applications which require very high current gain, beta, such as current mirrors and current sources. The high input impedance and the high DC current gain of the Field Effect Transistors result in extremely low current loss through the control gate. The DC current gain is limited by the gate input leakage current, which is specified at 30pA at room temperature. For example, DC beta of the device at a drain current of 3mA at 25°C is = 3mA/30pA = 100,000,000. Precision current mirrors Complementary push-pull linear drives Analog switches Choppers Differential amplifier input stage Voltage comparator Data converters Sample and Hold Analog inverter Precision matched current sources PIN CONFIGURATION DN1 1 14 DN2 GN1 2 13 GN2 SN1 3 12 SN2 V- 4 11 V+ DP1 5 10 DP2 GP1 6 9 GP2 SP1 7 8 SP2 TOP VIEW SBL, PBL, DB PACKAGES FEATURES • Thermal tracking between N-channel and P-channel pairs • Low threshold voltage of 0.7V for both N-channel & P-channel MOSFETS • Low input capacitance • Low Vos -- 10mV • High input impedance -- 1013Ω typical • Low input and output leakage currents • Negative current (IDS) temperature coefficient • Enhancement mode (normally off) • DC current gain 109 • Matched N-channel and matched P-channel in one package • RoHS compliant BLOCK DIAGRAM N GATE 1 (2) N SOURCE 1 (3) N DRAIN 1 (1) SUBSTRATE (4) N SOURCE 2 (12) N DRAIN 2 (14) N GATE 2 (13) ORDERING INFORMATION (“L” suffix denotes lead-free (RoHS)) P GATE 1 (6) Operating Temperature Range* 0°C to +70°C 0°C to +70°C -55°C to +125°C 14-Pin Small Outline Package (SOIC) 14-Pin Plastic Dip Package 14-Pin CERDIP Package ALD1105SBL ALD1105PBL ALD1105DB * Contact factory for leaded (non-RoHS) or high temperature versions. P SOURCE 1 (7) P DRAIN 1 (5) SUBSTRATE (11) P DRAIN 2 (10) P SOURCE 2 (8) P GATE 2 (9) Rev 2.0 ©2012 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, CA 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286 www.aldinc.com ABSOLUTE MAXIMUM RATINGS Drain-source voltage, VDS Gate-source voltage, VGS Power dissipation Operating temperature range SBL, PBL packages DB package Storage temperature range Lead temperature, 10 seconds CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment. 10.6V 10.6V 500mW 0°C to +70°C -55°C to +125°C -65°C to +150°C +260°C OPERATING ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise specified N - Channel Parameter Symbol Min Typ Max Gate Threshold VT 0.4 0.7 1.0 Voltage Offset Voltage VGS1 - VGS2 VOS 2 Gate Threshold Temperature TCVT Drift 10 -1.2 Unit V Test Conditions IDS = 1µA VGS = VDS mV IDS = 10µA VGS = VDS P - Channel Min Typ Max -0.4 -0.7 -1.0 2 mV/°C -1.3 On Drain Current IDS (ON) 3 4.8 mA VGS = VDS = 5V -1.3 -2 Trans-. conductance Gfs 1 1.8 mmho VDS = 5V IDS= 10mA 0.25 0.67 Mismatch ∆Gfs 0.5 % Output Conductance GOS 200 µmho Drain Source ON Resistance RDS(ON) 350 Drain Source ON Resistance ∆RDS(ON) Mismatch 0.5 Drain Source Breakdown Voltage BVDSS 500 12 Test Conditions IDS = -1µA VGS = VDS mV IDS = -10µA VGS = VDS mV/°C mA VGS = VDS = -5V mmho VDS = -5V IDS= -10mA 0.5 % VDS = 5V IDS = 10mA 40 µmho VDS = -5V IDS = -10mA Ω VDS = 0.1V VGS = 5V 1200 Ω VDS = -0.1V VGS = -5V % VDS = 0.1V VGS = 5V 0.5 % VDS = -0.1V VGS = -5V V IDS = 1µA VGS =0V V IDS = -1µA VGS =0V Off Drain Current IDS(OFF) 10 400 4 pA nA VDS =12V IGS = 0V TA = 125°C Gate Leakage Current IGSS 0.1 30 1 pA nA VDS = 0V VGS =12V TA = 125°C Input Capacitance CISS 1 3 pF ALD1105 10 Unit V 1800 -12 Advanced Linear Devices 10 400 4 pA nA VDS = -12V VGS = 0V TA = 125°C 1 30 1 pA nA VDS = 0V VGS =-12V TA = 125°C 1 3 pF 2 of 9 TYPICAL P-CHANNEL PERFORMANCE CHARACTERISTICS LOW VOLTAGE OUTPUT CHARACTERISTICS OUTPUT CHARACTERISTICS -10 VGS = -12V VBS = 0V TA = 25°C -7.5 DRAIN SOURCE CURRENT (µA) DRAIN SOURCE CURRENT (mA) 500 -10V -8V -5.0 -6V -2.5 -4V VGS = -12V VBS = 0V TA = 25°C 250 -6V -4V -2V 0 -250 -2V -500 0 0 -2 -4 -6 -8 -10 -320 -12 -160 DRAIN SOURCE VOLTAGE (mV) DRAIN SOURCE VOLTAGE (V) TRANSFER CHARACTERISTIC WITH SUBSTRATE BIAS -20 1.0 IDS = -5mA VBS = 0V f = 1KHz 0.5 0.2 0.1 TA = +125°C TA = +25°C 0.05 VBS = 0V DRAIN SOURCE CURRENT (µA) FORWARD TRANSCONDUCTANCE (mmho) FORWARD TRANSCONDUCTANCE vs. DRAIN SOURCE VOLTAGE IDS = -1mA 0.02 -10 -5 VGS = VDS TA = 25°C 0 -2 -4 -6 -8 0 -12 -10 -0.8 DRAIN SOURCE ON RESISTANCE RDS (ON) vs. GATE SOURCE VOLTAGE -2.4 -3.2 -4.0 OFF DRAIN CURRENT vs. AMBIENT TEMPERATURE OFF DRAIN SOURCE CURRENT (pA) 100 VDS = 0.4V VBS = 0V 10 -1.6 GATE SOURCE VOLTAGE (V) DRAIN SOURCE VOLTAGE (V) DRAIN SOURCE ON RESISTANCE (KΩ) 4V 6V 8V 10V 12V 2V -15 0.01 0 TA = +125°C 1 TA = +25°C 1000 VDS = -12V VGS = VBS = 0V 100 10 1 0.1 0 -2 -4 -6 -8 -10 -12 -50 -25 0 +25 +50 +75 +100 +125 AMBIENT TEMPERATURE (°C) GATE SOURCE VOLTAGE (V) ALD1105 320 160 0 Advanced Linear Devices 3 of 9 TYPICAL N-CHANNEL PERFORMANCE CHARACTERISTICS OUTPUT CHARACTERISTICS LOW VOLTAGE OUTPUT CHARACTERISTICS VGS = 12V VBS = 0V TA = 25°C DRAIN SOURCE CURRENT (µA) DRAIN SOURCE CURRENT (mA) 1000 20 10V 15 8V 10 6V 5 4V 2V 0 4 6 8 10 4V 2V 0 -500 -80 0 80 160 DRAIN SOURCE VOLTAGE (V) DRAIN SOURCE VOLTAGE (mV) FORWARD TRANSCONDUCTANCE vs. DRAIN SOURCE VOLTAGE TRANSFER CHARACTERISTIC WITH SUBSTRATE BIAS 20 IDS = 10mA 5 TA = +25°C TA = +125°C VGS = VDS TA = 25°C DRAIN SOURCE CURRENT (µA) VBS = 0V f = 1KHz 10 2 1 0.5 15 VBS = 0V 2 4 6 -6V -8V -10V 5 -12V 0 8 10 12 0 0.8 1.6 2.4 3.2 DRAIN SOURCE VOLTAGE (V) GATE SOURCE VOLTAGE (V) DRAIN SOURCE ON RESISTANCE RDS (ON) vs. GATE SOURCE VOLTAGE OFF DRAIN CURRENT vs. AMBIENT TEMPERATURE 100 VDS = 0.2V VBS = 0V 10 TA = +125°C 1 TA = +25°C 0.1 -4V -2V 10 IDS = 1mA 0.2 0 2 4.0 1000 VDS = +12V VGS = VBS = 0V 100 10 1 4 6 8 10 12 -50 -25 0 +25 +50 +75 +100 +125 AMBIENT TEMPERATURE (°C) GATE SOURCE VOLTAGE (V) ALD1105 6V -1000 -160 12 VGS = 12V 500 20 0 DRAIN SOURCE ON RESISTANCE (KΩ) 2 OFF DRAIN SOURCE CURRENT (pA) FORWARD TRANSCONDUCTANCE (mmho) 0 VBS = 0V TA = 25°C Advanced Linear Devices 4 of 9 TYPICAL APPLICATIONS CURRENT SOURCE MIRROR CURRENT SOURCE WITH GATE CONTROL V+ = +5V V+ = +5V V+ = +5V Q3 ISET Q4 Q3 Q4 RSET ISET I SOURCE ISOURCE RSET Digital Logic Control of Current Source Q1 Q2 Q1, Q2: N - Channel MOSFET Q3, Q4: P - Channel MOSFET Q1 ON I SOURCE = ISET = V+ -Vt RSET ~ = 4 RSET OFF : N - Channel MOSFET Q1 Q3,Q4 : P - Channel MOSFET CURRENT SOURCE MULTIPLICATION DIFFERENTIAL AMPLIFIER V+ V+ = +5V PMOS PAIR Q3 VIN+ Q4 Q1 ALD1105 Q2 NMOS PAIR RSET ISOURCE = ISET x N VIN- Q1 QSET Q2 Q3 QN Current Source Q1, Q2: N - Channel MOSFET Q3, Q4: P - Channel MOSFET ALD1105 ISET VOUT QSET, Q1..QN: ALD 1106 or ALD 1105 N - Channel MOSFET Advanced Linear Devices 5 of 9 TYPICAL APPLICATIONS (cont.) BASIC CURRENT SOURCES P-CHANNEL CURRENT SOURCE N-CHANNEL CURRENT SOURCE V+ = +5V V+ = +5V ISET RSET 1/2 ALD1105 ISOURCE Q2 Q3 Q1 Q4 I SOURCE ISET 1/2 ALD1105 ISOURCE = ISET = V+ - Vt RSET V+ - 1.0 ~ ~ = = RSET RSET 4 RSET Q1, Q2 : N - Channel MOSFET Q3, Q4: P - Channel MOSFET CASCODE CURRENT SOURCES V+ = +5V V+ = +5V ISET RSET ISOURCE Q4 Q2 Q1 Q2 Q3 Q4 Q3 Q1 ISET ISOURCE = ISET = Q1, Q2, Q3, Q4: N - Channel MOSFET (1/2 ALD1105 + ALD1116) ALD1105 ISOURCE RSET V+ - 2Vt RSET ~ = 3 RSET Q1, Q2, Q3, Q4: P - Channel MOSFET (1/2 ALD1105 + ALD1117) Advanced Linear Devices 6 of 9 SOIC-14 PACKAGE DRAWING 14 Pin Plastic SOIC Package Millimeters E S (45°) Dim A Min 1.35 Max 1.75 Min 0.053 Max 0.069 A1 0.10 0.25 0.004 0.010 b 0.35 0.45 0.014 0.018 C 0.18 0.25 0.007 0.010 D-14 8.55 8.75 0.336 0.345 E 3.50 4.05 0.140 0.160 1.27 BSC e D A Inches 0.050 BSC H 5.70 6.30 0.224 0.248 L 0.60 0.937 0.024 0.037 ø 0° 8° 0° 8° S 0.25 0.50 0.010 0.020 A1 e b S (45°) H L ALD1105 C ø Advanced Linear Devices 7 of 9 PDIP-14 PACKAGE DRAWING 14 Pin Plastic DIP Package Millimeters E E1 D S A2 A1 A L Inches Dim A Min Max Min 3.81 5.08 0.105 Max 0.200 A1 0.38 1.27 0.015 0.050 A2 1.27 2.03 0.050 0.080 b 0.89 1.65 0.035 0.065 b1 0.38 0.51 0.015 0.020 c 0.20 0.30 0.008 0.012 D-14 17.27 19.30 0.680 0.760 E 5.59 7.11 0.220 0.280 E1 7.62 8.26 0.300 0.325 e 2.29 2.79 0.090 0.110 e1 7.37 7.87 0.290 0.310 L 2.79 3.81 0.110 0.150 S-14 1.02 2.03 0.040 0.080 ø 0° 15° 0° 15° e b b1 c e1 ALD1105 ø Advanced Linear Devices 8 of 9 CERDIP-14 PACKAGE DRAWING 14 Pin CERDIP Package Millimeters E E1 D A1 s A L L1 L2 b b1 e Inches Dim A Min Max Min Max 3.55 5.08 0.140 0.200 A1 1.27 2.16 0.050 0.085 b 0.97 1.65 0.038 0.065 b1 0.36 0.58 0.014 0.023 C 0.20 0.38 0.008 0.015 D-14 -- 19.94 -- 0.785 E 5.59 7.87 0.220 0.310 E1 7.73 8.26 0.290 0.325 e 2.54 BSC 0.100 BSC e1 7.62 BSC 0.300 BSC L 3.81 5.08 0.150 0.200 L1 3.18 -- 0.125 -- L2 0.38 1.78 0.015 0.070 S -- 2.49 -- 0.098 Ø 0° 15° 0° 15° C e1 ALD1105 ø Advanced Linear Devices 9 of 9