A3968 Dual Full-Bridge PWM Motor Driver Features and Benefits Description ▪ ±650 mA continuous output current ▪ 30 V output voltage rating ▪ Internal fixed-frequency PWM current control ▪ Satlington® sink drivers ▪ Brake mode ▪ User-selectable blanking window ▪ Internal ground-clamp and flyback diodes ▪ Internal thermal-shutdown circuitry ▪ Crossover-current protection and UVLO protection The A3968 bidirectionally controls two DC motors. The device includes two full-bridges capable of continuous output currents of ±650 mA and operating voltages to 30 V. Motor winding current can be controlled by the internal fixed-frequency, pulse-width modulated (PWM), current-control circuitry. The peak load current limit is set by user selection of a reference voltage and current-sensing resistors. The fixed-frequency pulse duration is set by a user-selected external RC timing network. The capacitor in the RC timing network also determines a user-selectable blanking window that prevents false triggering of the PWM current-control circuitry during switching transitions. To reduce on-chip power dissipation, the full-bridge power outputs have been optimized for low saturation voltages. The sink drivers feature the Allegro® patented Satlington® output structure. The Satlington outputs combine the low voltage drop of a saturated transistor and the high peak current capability of a Darlington. Package: 16 pin SOIC (suffix LB) For each bridge, the INPUTA and INPUTB terminals determine the load-current polarity by enabling the appropriate source and sink driver pair. When a logic low is applied to both INPUTs Continued on the next page… Not to scale Typical Application MOTOR 1 MOTOR 2 16 1 V INPUT1A 2 INPUT1B 3 4 LOGIC BB LOGIC 15 INPUT2A 14 INPUT2B 13 0.5 Ω 0.5 Ω 5 12 +5 V VREF RC Dwg. EP-047-6 29319.29G V CC + 47 μF BB +5 V 10 9 680 pF 7 8 10 kΩ 11 V 56 kΩ 39 kΩ 6 +24 V A3968 Dual Full-Bridge PWM Motor Driver with Brake Description (continued) of a bridge, the braking function is enabled. In brake mode, both source drivers are turned off and both sink drivers are turned on, thereby dynamically braking the motor. When a logic high is applied to both INPUTs of a bridge, all output drivers are disabled. and flyback diodes, and crossover-current protection. Special power-up sequencing is not required. Internal circuit protection includes thermal shutdown with hysteresis, ground-clamp pins are at ground potential and need no electrical isolation. The The A3968 is supplied in a 16-lead plastic SOIC with two pins internally fused to the die pad for enhanced thermal dissipation. These device is lead (Pb) free, with 100% matte tin leadframe plating. Selection Guide Part Number A3968SLBTR–T Packing Ambient Temperature Range (°C) 1000 pieces / reel –20 to 85 Absolute Maximum Ratings Characteristic Symbol Notes Rating Units Load Supply Voltage VBB 30 V Logic Supply Voltage VCC 7.0 V Input Voltage VIN –0.3 to VCC + 0.3 V Sense Voltage VS 1.0 V ±750 mA ±650 mA 1.8 W Range E –40 to 85 ºC Range S Peak Output Current* IOUT Continuous Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or TJ(max) TA = 25°C; per SEMI G42-88 Specification, Thermal Test Board Standardization for Measuring Junction-to-Ambient Thermal Resistance of Semiconductor Packages. Package Power Dissipation PD Operating Ambient Temperature TA –20 to 85 ºC Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC Storage Temperature Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 Dual Full-Bridge PWM Motor Driver with Brake FUNCTIONAL BLOCK DIAGRAM LOAD SUPPLY OUTB OUTA LOGIC SUPPLY (One Half of Circuit Shown) V CC INPUTA + CONTROL LOGIC V BB UVLO & TSD INPUTB SOURCE ENABLE PWM LATCH BLANKING GATE CURRENT-SENSE COMPARATOR SENSE + – R Q TO OTHER BRIDGE TO OTHER BRIDGE S ÷4 GROUND RS OSC RC RT TO OTHER BRIDGE REFERENCE A3968 CT Dwg. FP-036-4 TRUTH TABLE INPUTA L L H H INPUTB L H L H OUTA L L H Z OUTB L H L Z Description Brake mode “Forward” “Reverse” Disable Z = High impedance Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Copyright © 1998, 2003 Allegro MicroSystems, Inc. 3 A3968 Dual Full-Bridge PWM Motor Driver with Brake ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V, VS = 0 V, 56 kΩ & 680 pF RC to Ground (unless noted otherwise) Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units VCC — 30 V Output Drivers Load Supply Voltage Range VBB Operating, IOUT = ±650 mA, L = 3 mH Output Leakage Current ICEX VOUT = 30 V — <1.0 50 μA VOUT = 0 V — <-1.0 -50 μA Source Driver, IOUT = -400 mA — 1.7 2.0 V Source Driver, IOUT = -650 mA — 1.8 2.1 V Sink Driver, IOUT = +400 mA, VS = 0.5 V — 0.3 0.5 V Sink Driver, IOUT = +650 mA, VS = 0.5 V — 0.7 1.3 V IF = 400 mA — 1.1 1.4 V IF = 650 mA — 1.4 1.6 V IBB(ON) Both bridges ON (forward or reverse) — 3.0 5.0 mA IBB(OFF) All INPUTs = 2.4 V — <1.0 200 μA 4.75 — 5.50 V Output Saturation Voltage Clamp Diode Forward Voltage Motor Supply Current (No Load) VCE(SAT) VF Control Logic Logic Supply Voltage Range VCC Operating Logic Input Voltage VIN(1) 2.4 — — V VIN(0) — — 0.8 V IIN(1) VIN = 2.4 V — <1.0 20 μA IIN(0) VIN = 0.8 V — <-20 -200 μA Reference Input Volt. Range VREF Operating 0.1 – 2.0 V Reference Input Current IREF -2.5 0 1.0 μA Reference Divider Ratio VREF/VTRIP 3.8 4.0 4.2 — Logic Input Current Current-Sense Comparator Input Offset Voltage VIO VREF = 0.1 V -6.0 0 6.0 mV Current-Sense Comparator Input Voltage Range VS Operating -0.3 — 1.0 V Sense-Current Offset ISO IS – IOUT, 50 mA ≤ IOUT ≤ 650 mA 12 18 24 mA NOTES:1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A3968 Dual Full-Bridge PWM Motor Driver with Brake ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 30 V, VCC = 4.75 V to 5.5 V, VREF = 2 V, VS = 0 V, 56 kΩ & 680 pF RC to Ground (unless noted otherwise) (cont.) Limits Characteristic Symbol Test Conditions Min. Typ. Max. Units CT = 680 pF, RT = 56 kΩ 22.9 25.4 27.9 kHz Comparator Trip to Source OFF — 1.0 1.4 μs Cycle Reset to Source ON — 0.8 1.2 μs Control Logic (continued) PWM RC Frequency PWM Propagation Delay Time fosc tPWM Cross-Over Dead Time tcodt 1 kΩ Load to 25 V 0.2 1.8 3.0 μs Propagation Delay Times tpd IOUT = ±650 mA, 50% to 90%: Disable OFF to Source ON Disable ON to Source OFF Disable OFF to Sink ON Disable ON to Sink OFF Brake Enable to Sink ON Brake Enable to Source OFF — — — — — — 100 500 200 200 2200 200 — — — — — — ns ns ns ns ns ns TJ — 165 — °C ΔTJ — 15 — °C — 4.1 4.6 V 0.1 0.6 — V Thermal Shutdown Temp. Thermal Shutdown Hysteresis UVLO Enable Threshold UVLO Hysteresis Logic Supply Current VT(UVLO)+ Increasing VCC VT(UVLO)hys ICC(ON) Both bridges ON (forward or reverse) — — 50 mA ICC(OFF) All INPUTs = 2.4 V — — 9.0 mA ICC(BRAKE) All INPUTs = 0.8 V — — 95 mA NOTES:1. Typical Data is for design information only. 2. Negative current is defined as coming out of (sourcing) the specified device terminal. Typical output saturation voltages showing Satlington sink-driver operation. OUTPUT SATURATION VOLTAGE IN VOLTS 2.5 TA = +25°C 2.0 SOURCE DRIVER 1.5 1.0 0.5 SINK DRIVER 0 200 300 400 500 600 7 00 OUTPUT CURRENT IN MILLIAMPERES Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A3968 Dual Full-Bridge PWM Motor Driver with Brake FUNCTIONAL DESCRIPTION Internal PWM Current Control. The A3968 dual full-bridges bidirectionally control two DC motors. An internal fixed-frequency PWM control circuit controls the the load current in each motor. The current-control circuitry works as follows: when the outputs of the full-bridge are turned on, current increases in the motor winding. The load current is sensed by the current-control comparator via an external sense resistor. RS. Load current continues to increase until it reaches the predetermined value, set by the selection of external current-sensing resistors and reference input voltage (VREF) according to the equation: ITRIP = IOUT + ISO = VREF/(4 RS) where ISO is the sense-current error (typically 18 mA) due to the base-drive current of the sink driver transistor. At the trip point, the comparator resets the source-enable latch, turning off the source driver of that full-bridge. The source turn-off of one full-bridge is independent of the other full-bridge. Load inductance causes the current to recirculate through the sink driver and ground-clamp diode. The current decreases until the internal clock oscillator sets the source-enable latches of both Full-bridges, turning on the source drivers of both bridges. Load current increases again, and the cycle is repeated. The frequency of the internal clock oscillator is set by the external timing components RTCT. The frequency can be approximately calculated as: fosc = 1/(RT CT + tblank) where tblank is defined below. The range of recommended values for RT and CT are 20 to 100 k and 470 to 1000 pF respectively. Nominal values of 56 k and 680 pF result in a clock frequency of 25.4 kHz. Current-Sense Comparator Blanking. When the source driver is turned on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the current-control comparator output is blanked for a short period of time when the source driver is turned on. The blanking time is set by the timing component CT according to the equation: tblank = 1900 CT (μs). A nominal CT value of 680 pF will give a blanking time of 1.3 μs. The current-control comparator is also blanked when the load current changes polarity (direction or phase change). This internally generated blank time is approximately 1.8 μs. V BB V PHASE See Enlargement A BRIDGE ON + I OUT BRIDGE ON ALL OFF 0 SOURCE OFF – ALL OFF BRIDGE ON I TRIP Enlargement A SOURCE OFF td t INTERNAL OSCILLATOR R TC T RS blank Dwg. WM-003-2 Dwg. EP-006-16 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A3968 Dual Full-Bridge PWM Motor Driver with Brake FUNCTIONAL DESCRIPTION (continued) Load Current Regulation. Due to internal logic and switching delays, td , the actual load current peak will be slightly higher than the ITRIP value. These delays, plus the blanking time, limit the minimum value the current control circuitry can regulate. To produce zero current in a winding, the INPUTA and INPUTB terminals should be held high, turning off all output drivers for that full-bridge. Output Drivers. To minimize on-chip power dissipation, the sink drivers incorporate a Satlington structure. The Satlington output combines the low VCE(sat) features of a saturated transistor and the high peak-current capability of a Darlington (connected) transistor. A graph showing typical output saturation voltages as a function of output current is on page 5. Logic Inputs. The direction of current in the motor winding is determined by the state of the INPUTA and INPUTB terminals of each bridge (see Truth Table). An internally generated dead time, tcodt , of approximately 1.8 μs prevents cross-over current spikes that can occur when switching the motor direction. Miscellaneous Information. Thermal protection circuitry turns off all output drivers should the junction temperature reach 165 °C typical. This is intended only to protect the device from failures due to excessive junction temperatures and should not imply that output short circuits are permitted. Normal operation is resumed when the junction temperature has decreased about 15°C. A logic high on both INPUTs turns off all four output drivers of that full-bridge. This results in a fast current decay through the internal ground clamp and flyback diodes. The A3968 current control employs a fixed-frequency, variable duty cycle PWM technique. As a result, the current-control regulation may become unstable if the duty cycle exceeds 50%. The appropriate INPUTA or INPUTB can be pulse-width modulated for applications that require a fast current-decay PWM. If external current-sensing circuitry is used, the internal current-control logic can be disabled by connecting the RTCT terminal to ground. To minimize current-sensing inaccuracies caused by ground trace IR drops, each current-sensing resistor should have a separate return to the ground terminal of the device. For low-value sense resistors, the I x R drops in the printedwiring board can be significant and should be taken into account. The use of sockets should be avoided as their contact resistance can cause variations in the effective value of RS. A logic low on the INPUTA and the INPUTB terminals will place that full-bridge in the brake mode. Both source drivers are turned off and both sink drivers are turned on. This has the effect of shorting the DC motor back-EMF voltage, resulting in a current flow that dynamically brakes the motor. Note that, during braking, the internal current-control circuitry is disabled. Therefore, care should be taken to ensure that the motor current does not exceed the absolute maximum rating of the A3968. The REFERENCE input voltage is typically set with a resistor divider from VCC. This reference voltage is internally divided down by 4 to set up the current-comparator trip-voltage threshold. The reference input voltage range is 0 to 2 V. The LOAD SUPPLY terminal, VBB, should be decoupled with an electrolytic capacitor (47 μF recommended) placed as close to the device as physically practical. To minimize the effect of system ground I x R drops on the logic and reference input signals, the system ground should have a low-resistance return to the load supply voltage. The frequency of the clock oscillator will determine the amount of ripple current. A lower frequency will result in higher current ripple, but reduced heating in the motor and driver IC due to a corresponding decrease in hysteretic core losses and switching losses respectively. A higher frequency will reduce ripple current, but will increase switching losses and EMI. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A3968 Dual Full-Bridge PWM Motor Driver with Brake Package LB, 16-pin SOICW 10.30±0.20 4° ±4 16 1.27 0.65 16 +0.07 0.27 –0.06 10.30±0.33 7.50±0.10 9.50 A +0.44 0.84 –0.43 2.25 1 2 1 2 0.25 B 16X SEATING PLANE 0.10 C 0.41 ±0.10 1.27 C PCB Layout Reference View SEATING PLANE GAUGE PLANE 2.65 MAX 0.20 ±0.10 For Reference Only Pins 4 and 13 internally fused Dimensions in millimeters (reference JEDEC MS-013 AA) Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Reference pad layout (reference IPC SOIC127P1030X265-16M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances Copyright ©1997–2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Satlington® is a registered trademark of Allegro MicroSystems, Inc. (Allegro), and Satlington devices are manufactured under U. S. Patent No. 5,684,427. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8