A4915 3-Phase MOSFET Driver Description Features and Benefits • 5 to 50 V supply voltage • Latched TSD with fault output • Drives six N-channel high current MOSFETs • Internally controlled synchronous rectification • Speed voltage input enables internal PWM duty cycle control of full bridge • Center aligned PWM • Internal UVLO and crossover current protection • Hall switch inputs • Adjustable dead time protection • Low power sleep mode for battery-powered applications The A4915 is designed for pulse width modulated (PWM) current control of 3-phase brushless DC motors. The A4915 is capable of high current gate drive for 6 all N-channel power MOSFETs. An internal charge pump ensures gate drive down to 7 V supply and provides limited gate drive down to 5 V. A bootstrap capacitor is used to generate a supply voltage greater than the source voltage of the high side MOSFET, required for N-channel MOSFETs. Internal synchronous rectification control circuitry is provided to improve power dissipation in the external MOSFETs during PWM operation. Internal circuit protection includes latched thermal shutdown, dead time protection, and undervoltage lockout. Special power up sequencing is not required. Packages: 28-pin TSSOP with exposed thermal pad (LP package) The A4915 is supplied in a 28-pin TSSOP with an exposed thermal pad (suffix LP) and a 28-contact 5 × 5 mm QFN with an exposed thermal pad (suffix ET). These packages are lead (Pd) free, with 100% matte-tin leadframe plating. 28-contact QFN 5 mm × 5 mm × 0.90 mm (ET package) Not to scale VDD Comm Logic HA HB 0.47 μF CP1 CP2 Functional Block Diagram Charge Pump Regulator A4915 VBB VIN CREG VREG 47 V TVS CVBB1 CVBB2 HC VDD VDD TDEAD Control Logic Voltage to Duty VRESET FAULT A4915-DS, Rev. 1 RGATE SB SC GLA GLB OSC SPEED R3 HA HB HC CBOOTA SA VREG VDD CA CB CC GHA GHB GHC DIR ENABLE R2 R1 High Side Driver BRAKEn Rdead Phase A Bootstrap Monitor CVDD1 Low Side Driver RGATE To Phase B To Phase C GLC One of three phases shown LSS GND A4915 3-Phase MOSFET Driver Selection Guide Part Number Package Packing* A4915METTR-T 28-contact QFN with exposed thermal pad 1500 pieces per 7-in. reel A4915MLPTR-T 28-pin TSSOP with exposed thermal pad 4000 pieces per 13-in. reel Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit Load Supply Voltage VBB –0.3 to 50 V Logic Supply Voltage VDD –0.3 to 6 V VREG Pin VREG –0.3 to 16 V CP1 Pin VCP1 –0.3 to 16 V CP2 Pin VCP2 VCP1 – 0.3 to VREG + 0.3 V VI –0.3 to 6 V Logic Inputs Hall Inputs VHx –0.3 to 6 V Logic Outputs VO –0.3 to 6 V SPEED Input VSPEED –0.3 to 6 V CA, CB, and CC Pins VCx –0.3 to VREG + 50 V GHA, GHB, and GHC Pins VGHx VCx – 16 to VCX + 0.3 V SA, SB, and SC Pins VSx VCx – 16 to VCx + 0.3 V GLA, GLB, GLC Pins VGLx VREG – 16 to 18 V TJ(max) 150 °C Storage Temperature Range Tstg –55 to 150 °C Operating Ambient Temperature Range TA –20 to 105 °C Maximum Continuous Junction Temperature Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* Value Unit Package ET, on 4-layer PCB based on JEDEC standard 32 ºC/W Package LP, on 4-layer PCB based on JEDEC standard 28 ºC/W *Additional thermal information available on the Allegro website. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4915 3-Phase MOSFET Driver 22 GHA 23 SA 24 CA 25 VREG 26 CP2 27 CP1 28 GND Pin-out Diagrams LSS 1 28 HC GLC 2 27 HB GHC 3 26 HA VBB 1 21 GLA SC 4 25 BRAKEn SPEED 2 20 CB CC 5 24 DIR TDEAD 3 19 SB GLB 6 VDD 4 18 GHB GHB 7 17 GLB SB 8 21 VDD CB 9 20 TDEAD GLA 10 19 SPEED GHA 11 18 VBB SA 12 17 GND CA 13 16 CP1 VREG 14 15 CP2 FAULT PAD 5 GHC 14 GLC 13 LSS 12 BRAKEn HC 11 15 SC HB 10 16 CC 7 8 6 DIR HA 9 ENABLE ET Package PAD 23 ENABLE 22 FAULT LP Package Terminal List Table Name VBB SPEED TDEAD VDD FAULT ENABLE DIR BRAKEn Function Number ET LP Name Function Number ET LP Supply voltage 1 18 SC High-side source connection 15 4 Reference voltage input 2 19 CC Bootstrap output phase C 16 5 Terminal for dead time setting 3 20 GLB Low-side gate drive 17 6 Logic supply input 4 21 GHB High-side gate drive 18 7 Fault output 5 22 SB High-side source connection 19 8 Logic input, PWM control 6 23 CB Bootstrap output phase B 20 9 Logic input, motor direction 7 24 GLA Low-side gate drive 21 10 Logic input, motor brake (active low) 8 25 GHA High-side gate drive 22 11 12 HA Hall input phase A 9 26 SA High-side source connection 23 HB Hall input phase B 10 27 CA Bootstrap output phase a 24 13 HC Hall input phase C 11 28 VREG Gate drive supply output 25 14 LSS Sense input 12 1 CP2 Charge pump capacitor terminal 26 15 GLC Low-side gate drive 13 2 CP1 Charge pump capacitor terminal 27 16 GHC High-side gate drive 14 3 GND Ground 28 17 PAD Exposed pad for enhanced thermal dissipation – – Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4915 3-Phase MOSFET Driver ELECTRICAL CHARACTERISTICS Valid at TA = 25°C, VBB = 24 V; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit 5.0 – 50 V – 10 20 mA fPWM ≈ 20 kHz, CLOAD = 10 nF – 12 24 mA VREG = 13 V, outputs disabled – 3 3.5 mA μA Supply and Reference Operating Voltage Range VBB Operating, outputs active fENB = 30 kHz, CLOAD = 10 nF Motor Supply Current IBB Sleep mode – – 1 ID = 10 mA 0.4 0.7 1.0 V ID = 100 mA 1.5 2.2 2.8 V Bootstrap Diode Forward Voltage VfBOOT Bootstrap Diode Current Limit VDBOOT 250 500 750 mA VDD 3 – 5.5 V VDD Input Voltage VDD Input Current IDDQ ENABLE = high, outputs disabled – 6 10 mA IDDS Sleep mode – – 10 μA ENABLE = low for longer than tSLEEP, SPEED = high – – 1 μA ENABLE = high, SPEED = low for longer than tSLEEP – – 1 μA – – 1 μA ENABLE Input Current Sleep Mode IENB(SLP) SPEED Input Current Sleep Mode ISPEED(SLP) BRAKEn Input Current Sleep Mode IBRAKE(SLP) ENABLE = low for longer than tSLEEP DIR Input Current Sleep Mode ENABLE Input Frequency Range Internal PWM Frequency SPEED Input Voltage Range IDIR(SLP) ENABLE = low for longer than tSLEEP – – 1 μA fENB VSPEED = VDD 1 – 100 kHz fPWM VENABLE = VDD 14 20 26 kHz 0 – VDD V VSPEED SPEED Disable Voltage VSPEED(D) Measured as VSPEED / VDD , duty cycle = 0% 10 15 20 % SPEED Enable Voltage* VSPEED(E) Measured as VSPEED / VDD , duty cycle = 100% 79 82 86 % SPEED Bias Current ISPEED(bias) VSPEED = VDD= 5 V VBB = 9 V VBB = 7.5 V VREG Output Voltage VREG –25 0 25 μA 11.8 13 13.75 V 11.5 13 13.75 V 2 × VBB – 3.5 V – – V VBB = 5.5 V 8.0 9.5 – V VBB = 6 V Protection Thermal Shutdown Temperature VREG Undervoltage VREG Undervoltage Hysteresis TTSD FAULT rising 155 170 185 °C VREGON VREG rising 7.0 7.8 8.6 V VREGOFF VREG falling 6.39 7.1 7.81 V – 700 – mV VREGhys Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4915 3-Phase MOSFET Driver ELECTRICAL CHARACTERISTICS (continued) Valid at TA = 25°C, VBB = 24 V; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit Protection (continued) Bootstrap Undervoltage Bootstrap Undervoltage Hysteresis VDD Undervoltage VDD Undervoltage Hysteresis Sleep Wake-up Delay VBOOTUV Measured as a percentage of VREG 55 – 65 % VBOOTUVhys Measured as a percentage of VREG – 20 – % VDD rising – 2.75 2.95 V VDD falling 2.45 2.6 – V VDDUVhys 50 100 150 mV tWAKE – – 3 ms VDDUV Gate Drive High-Side Gate Drive Output VGHx Low-Side Gate Drive Output VGLx CBOOTx fully charged, CLOAD = 10 nF IGHx < 10 μA VREG = 13 V, CLOAD = 10 nF VCx – 0.2 – – V – – VSx + 0.3 V VREG – 0.2 – – V IGLx < 10 μA – – 0.3 V TJ = 25°C, IGHx = –150 mA 6 9 12 Ω TJ = 125°C, IGHx = –150 mA – 17 – Ω TJ = 25°C, IGLx = –150 mA 2.4 3.5 4.6 Ω TJ = 125°C, IGLx = –150 mA – 5 – Ω Gate Drive Pull-Up Resistance RGHx(ON)UP Gate Drive Pull-Down Resistance RGLx(ON)DN GHx Passive Pull-Down RGHx(PPD) VGHx – VSx < 0.3 V – 5000 – Ω GLx Passive Pull-Down RGLx(PPD) VGLx – VLSS < 0.3 V – 5000 – Ω trGx 20% to 80%, CLOAD = 10 nF – 200 – ns tfGx 80% to 20%, CLOAD = 10 nF – 150 – ns 10 – – ns Output Switching Time TDEAD tied to GND Dead Time tDEAD Time delay measured from turn-off to turn-on RTDEAD = 12 kΩ – 150 – ns RTDEAD = 64 kΩ 800 925 1050 ns RTDEAD = 220 kΩ – 2.9 – μs Logic I/O Logic Input Voltage Logic Input Current VIN(H) VIN(L) BRAKEn, DIR, ENABLE, HA, HB, and HC pins 0.7 × VDD – – V – – 0.3 × VDD V IIN(H) VIN = high – 10 – μA IIN(L) VIN = low, ENABLE = low –1 0 1 μA No fault present, ISINK = 1mA – – 0.2 V ENABLE = low, SPEED = high 1 2 3 ms ENABLE = high, SPEED = low 1 2 3 ms FAULT Output Voltage VFAUlT ENABLE and SPEED Sleep Timer tSLEEP Continued on the next page… Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4915 3-Phase MOSFET Driver ELECTRICAL CHARACTERISTICS (continued) Valid at TA = 25°C, VBB = 24 V; unless otherwise specified Characteristic Symbol Test Conditions Min. Typ. Max. Unit Logic I/O (continued) SPEED Sleep Threshold Fault Latch Reset Voltage Fault Latch Reset Pulse Time Hall Input Pull-Up Resistor Hall Input Current VSPEEDSLPth SPEED = low for longer than tSLEEP – – 295 mV VRESET Fault is present, outputs latched – – 0.8 V tFAULT Fault is present, outputs latched 12 – – μs RHx(PU) Hx pins, VIN = 0 V – 100 – kΩ IHALL Hx pins, VIN = 5 V – 0 1 μA Logic Input Pull-Down Resistor RIN(PD) ENABLE, DIR, BRAKEn, VIN = 5 V – 50 – kΩ Login Input Current Sleep Mode IIN(SLP) ENABLE, DIR, BRAKEn – – 1 μA tpd(on) DIR or BRAKEn input to output change, CLOAD = 0 nF – – 1200 ns ENABLE input to output change, CLOAD = 0 nF – – 900 ns DIR or BRAKEn input to output change, CLOAD = 0 nF – – 1200 ns ENABLE input to output change, CLOAD = 0 nF – – 900 ns ENABLE – – 900 ns DIR, BRAKEn – – 1000 ns Propagation Delay tpd(off) Input Pin Glitch Reject tglitch *Output duty cycle limited by tDEAD . Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4915 3-Phase MOSFET Driver Functional Description from the supply. When coming out of sleep allow 3 ms for the charge pump regulator to stabilize. Basic Operation The A4915 is a 3-phase MOSFET driver intended to drive high current MOSFETs. It is designed for use in battery operated equipment where low-voltage operation is critical. The A4915 also features a low current sleep mode which disables the device and draws minimum supply current. The A4915 is capable of driving 6 N-channel MOSFETs. Commutation logic includes Enable, Direction, and Brake modes for external PWM control. A Speed input is provided which allows an external source to PWM the bridge at 30 kHz typical. The PWM duty cycle is controlled by applying an analog voltage to the SPEED pin from 0 V to VDD . Pin Descriptions DIR The Direction pin is used to change the commutation direc- tion of the 3 bridges. Refer to table 1 for phase commutation information. ENABLE The ENABLE input terminal allows external PWM control. Setting ENABLE high turns on the selected sink-source pair, and setting it low switches off the appropriate drivers and the load current decays. If external PWM is used, the SPEED pin must be tied to VDD. When the ENABLE input is held low for longer than tSLEEP the A4915 turns off all internal circuitry and draws minimum current SPEED The duty cycle of the internally generated carrier frequency is controlled by applying a DC voltage on the SPEED input. A plot showing the relationship of Speed to duty cycle is shown in figure 1. When SPEED is pulled directly to VDD the internal carrier is disabled and the Enable input can be used to PWM the bridge. When VSPEED < VSPEED(D) the output is guaranteed to be 0%. When VSPEED > VSPEED(E) the output is guaranteed to be 100%. BRAKEn Brake mode turns all three sink drivers on and effectively shorts out the motor generated BEMF. The BRAKEn input overrides the ENABLE and SPEED inputs except when in Sleep mode. Refer to table 2 for the logic truth table. In order to comply with Failure Mode Effects and Analysis (FMEA), the brake function is normally active (logic low). If the BRAKEn pin on the device is open due to some failure of solder joint or microprocessor failure, the device will automatically implement Brake mode, preventing the motor from turning or pumping up the supply. Applying logic high to the BRAKEn terminal deactivates Brake mode and allows normal operation. Care must be taken when applying the Brake command because large currents can be generated. The user must ensure that the maximum ratings of the MOSFETs are not exceeded under worst Table 1. Commutation Table HA HB HC DIR GLA GLB GLC GHA GHB GHC SA SB SC 1 1 0 1 1 0 0 1 1 0 0 2 1 0 0 1 0 0 1 0 1 0 High – Low – High Low 3 1 1 0 1 1 0 0 0 1 4 0 1 0 1 1 0 0 0 0 0 Low High – 1 Low – High 5 0 1 1 1 0 1 0 0 0 1 6 0 0 1 1 0 1 0 1 0 0 – Low High High Low – 1 1 0 1 0 1 0 0 0 0 1 2 1 0 0 0 0 1 0 0 0 1 Low – High – Low High 3 1 1 0 0 0 1 0 1 0 4 0 1 0 0 0 0 1 1 0 0 High Low – 0 High – Low 5 0 1 1 0 0 0 1 0 1 0 – High Low 6 0 0 1 0 1 0 0 0 1 0 Low High – Hall Fault 1 1 1 X 0 0 0 0 0 0 – – – Hall Fault 0 0 0 X 0 0 0 0 0 0 – – – Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4915 3-Phase MOSFET Driver 100 case braking conditions. Maximum motor current during Brake mode can be approximated by: 90 IBRAKEn = VBEMF / RL 80 where VBEMF is the voltage generated by the motor and RL is the resistance of the phase winding. FAULT The Fault output is active high. Under normal operation (%) low-side gate drivers and to charge the bootstrap capacitors. 60 Ton / T VREG A regulated voltage output that is used to supply the 70 50 40 the open drain output pulls the Fault output to ground. When a fault occurs the open drain output is released, and the Fault output is then pulled to a logic high through a connected external passive pullup resistor. Fault conditions are shown in table 3. The presence of an invalid Hall combination is referred to as a Hall Fault. Invalid Hall combinations are documented in table 1. When a Hall Fault is present, the outputs are disabled. Invalid Hall Faults are not latched, and do not affect the state of the FAULT pin. Latched faults that result in disabled outputs can be reset in a number of ways: • A UVLO on VDD will serve as a reset 30 20 10 10 0 20 30 40 50 60 70 80 90 100 VSPEED/VDD (%) Figure 1. Speed in relation to duty cycle Table 3. Fault Conditions • If the device is put into sleep mode the latch is reset • A microprocessor can create a reset on the FAULT pin directly by forcing VRESET on the FAULT pin when a fault is active for longer than tFAULT (that is, when the outputs are latched) LSS The LSS terminal is the low-side drain connection for the Event Fault Pin TSD High Outputs Latched Disabled Yes SLEEP High Disabled No UVLO VREG/VDD High Disabled No Invalid Hall Low Disabled No MOSFET. If an external PWM current control loop is used, a low Table 2. Input Logic Truth Table Inputs ENABLE SPEED BRAKEn Low High High Mode of Operation PWM chop slow decay synchronous rectification (center aligned) Low High Low Brake mode – All low-side gates on High High High Selected drivers onb High High Low Brake mode – All low-side gates on High VDD × VSPEED(E) to VDD × VSPEED(D) High PWM chop slow decay synchronous rectification (center aligned)c High > VDD × VSPEED(E) High Selected drivers onb High < VDD × VSPEED(D) High PWM chop slow decay synchronous rectification (center aligned) Low longer than tSLEEP High Xa Sleep mode – coast High Low longer than tSLEEP Xa Sleep mode – coast aX = don’t care. and minium duty cycle limited by boot capacitor charge management. cInternal PWM active. bMaximum Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4915 3-Phase MOSFET Driver value sense resistor can be placed from LSS to ground for current sensing purposes, otherwise LSS should be connected directly to power ground. value of tDEAD in ns can be approximated by: CA, CB, CC High-side connections for the bootstrap capacitors Current, IDEAD, can be calculated by: tDEAD = 40 + (1.28–2 × RDEAD) (CBOOTx) and positive supply for high-side gate drive. IDEAD = 1.2 / RDEAD GHA, GHB, GHC High-side gate drive outputs for N-channel MOSFETs. SA, SB, SC Motor phase connections, serve as the negative sup- As values for R increase, current offsets and resistor mismatch cause the error terms to increase. Figure 2 shows the typical expected error for a given RDEAD value. plies for the high-side gate drive. GLA, GLB, GLC Low-side gate drive outputs for N-channel MOSFETs. CP1, CP2 Connections for the charge pump switching capacitor. Typical capacitance should be 0.47 μF. Sleep Mode The A4915 has a low-current Sleep mode to limit current draw on the battery. When in low-current Sleep mode (when ENABLE = low for longer than tSLEEP and SPEED = high), current into VBB and VDD is less than 1 μA. When ENABLE is held low for longer than tSLEEP and the SPEED input is held high, the pull-up resistors on the Hall inputs and the pull-down resistor on the BRAKEn pin are open-circuited to minimize current draw into logic input terminals. Only the condition where SPEED = high and ENABLE = low for longer than tSLEEP results in low current on logic input terminals. HA, HB, HC Hall input connections from Hall switches at the motor. Thermal Shutdown If the die temperature exceeds TTSD , the FAULT output is turned off and the outputs are disabled. Thermal shutdown is a latched fault. Dead Time To prevent cross-conduction (shoot through) in any phase of the bridge, it is necessary to have a dead time, tDEAD , between a high- or low-side turn-off and the next complementary turn-on event. The dead time for all three phases is set by a single dead time resistor (RDEAD) between the TDEAD pin and ground. For RDEAD values between 12 and 220 kΩ, at 25°C the nominal Center Aligned PWM The A4915 features center aligned PWM, which improves power dissipation and helps reduce EMI. During an off-time triggered by either an internal PWM or by an external Enable chop command, current recirculation will be in either the highside FETs or the low-side FETs, depending on the state of an internal latch. On each bridge Enable command, the latch is reset and the current recirculation shifts from high-side recirculation to low-side recirculation. 4000 3500 Maximum Dead Time (ns) 3000 Typical 2500 Minimum 2000 1500 1000 500 0 10 30 50 70 90 110 130 150 170 190 210 230 250 RDEAD (kΩ) Figure 2. RDEAD versus Dead Time Error Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4915 3-Phase MOSFET Driver This method of recirculation shifts 50% of the power to the high-side drivers during the off-time, reducing the power dissipation in the sink drivers. Reducing the overall temperature of the output drivers by sharing power between the 6 FETs improves system efficiency and battery life. The regulated voltage VREG is decoupled on the VREG terminal. The decoupling capacitance is based on the bootstrap capacitor which is dependent on the MOSFET selection. Refer to the Application Information section for details on correct sizing of VREG and bootstrap capacitors. Internal/External PWM The A4915 can be pulse width modulated (PWM) to control current. There are two methods by which PWM can be applied to the device. Gate Drive and RGATE • External PWM. This method requires a PWM signal be applied to the ENABLE pin. When the SPEED pin is tied directly to VDD, the ENABLE pin can be chopped from 0 to 100%. If the ENABLE input is held low for more than sleep timer, tSLEEP , the device enters low current sleep mode. • Internal PWM. This method uses the internally generated PWM, which is controlled by applying a DC voltage to the SPEED pin. When the ENABLE pin is tied directly to VDD, the speed can be controlled from 0 to 100%. See the SPEED pin description for further information. The gate drive for the external MOSFETs is capable of providing the large current transients needed to quickly charge and discharge the gate capacitance to maintain fast switching speeds and minimal power dissipation. The low-side driver current is sourced by the capacitor on the VREG terminal. The high-side gate drive current is supplied by the respective bootstrap capacitance connected between the Cx and Sx terminals. The charge and discharge of the gate can be controlled by using an external resistor (RGATE) in series with the gate. Bootstrap Charge Management Synchronous Rectification When a PWM off-time cycle is triggered by an ENABLE chop command or by an internal PWM off-time, load current recirculates. The A4915 synchronous rectification feature will turn on the appropriate MOSFETs during the off-time and effectively short out the body diodes with the low RSD(on) driver. This will lower power dissipation significantly and eliminates the need for external Schottky diodes. In order to protect the external MOSFETs from insufficient gate drive, it is important that the bootstrap capacitor voltage be monitored. Before a high-side switch is allowed to turn on, it must have sufficient charge on the bootstrap capacitor. If the voltage on the bootstrap capacitor is below the turn-on voltage limit, the A4915 will attempt to charge the bootstrap capacitor by turning on the associated low-side driver. The bootstrap monitor stays active during the duration of the switch on-time. If the voltage falls out of compliance at any time when the high-side driver is enabled, the driver is disabled and the low-side switch is activated to charge the bootstrap capacitor. Charge Pump Regulator The gate drives for the low-side MOSFETs and the bootstrap charge for the high-side drivers is accomplished by the charge pump regulator. For VBB above 16 V, the regulator acts as a linear regulator. Below 16 V, the regulated supply is maintained by a charge pump boost converter that requires a pump capacitor between CP1 and CP2. During normal operation and in conditions where the PWM duty cycle creates short off-times, the low-side switch may be activated more often to keep sufficient charge on the bootstrap capacitor. Proper sizing of the bootstrap and VREG capacitors is critical to being able to maintain effective gate drive. Refer to the Application Information section for details on correct sizing of VREG and bootstrap capacitors. For complete description of all operating conditions, see table 2. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 A4915 3-Phase MOSFET Driver Application Information Bootstrap Capacitor Selection In order to properly size the capacitor CBOOT, the total gate charge must be known. Too large a bootstrap capacitor and the charge time will be long, resulting in maximum duty cycle limitation. Too small a capacitor and the voltage ripple will be large when charging the gate. Size the CBOOT capacitor such that the charge, QBOOT, is 20 times larger than the required charge for the gate of the MOSFET, QGATE: CBOOT = (QGATE × 20) / VBOOT where VBOOT is the voltage across the bootstrap capacitor. The voltage drop across the bootstrap capacitor as the MOSFET gate is being charged, ΔV, can be approximated by: ΔV = QGATE / CBOOT For the bootstrap capacitor, a ceramic type rated at 16 V or larger should be used. VREG Capacitor Selection VREG is responsible for providing all the gate charge for the low side MOSFETs and for providing all the charge current for the three bootstrap capacitors. For these purposes, the VREG capacitor, CREG , should be 20 times the value of CBOOT: CREG = 20 × CBOOT Layout Recommendations Careful consideration must be given to PCB layout when designing high frequency, fast-switching, high-current circuits (refer to figures 3 and 4): • The A4915 ground, GND, and the high-current return of the external MOSFETs should return separately to the negative side of the motor supply filtering capacitor. This minimizes the effect of switching noise on the A4915. • The exposed thermal pad should be connected to GND. • Minimize stray inductance by using short, wide copper traces at the drain and source terminals of all power MOSFETs. This includes motor lead connections, the input power bus, and the common source of the low-side power MOSFETs. This minimizes voltages induced by fast switching of large load currents. • Consider the use of small (100 nF) ceramic decoupling capacitors across the source and drain of the power MOSFETs, to limit fast transient voltage spikes caused by inductance in the traces. • Keep the gate discharge return connections Sx and LSS as short as possible. Any inductance on these traces causes negative transitions on the corresponding A4915 terminals, which may exceed the Absolute Maximum Ratings. If this is likely, consider the use of clamping diodes to limit the negative excursion on these terminals with respect to GND. • Supply decoupling for VBB, VREG, and VDD should be connected independently, close to the GND terminal. The decoupling capacitors should also be connected as close as possible to the relevant supply terminal. • Gate charge drive paths and gate discharge return paths may carry large transient current pulses. Therefore the traces from GHx, GLx, Sx (x = A, B, or C) and LSS should be as short as possible to reduce the inductance of the trace. • Provide an independent connection from LSS to the common point of the power bridge. This can be the negative side of the motor supply filtering capacitor or one end of a sense resistor. It is not recommended to connect LSS directly to the GND terminal, as this may increase the noise at the digital inputs. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A4915 3-Phase MOSFET Driver VBB GND R1 R7 C2 Q1 PHASE A R4 R10 C4 C7 C6 Q4 C8 GND VBB GND R24 C5 R2 C9 R15 R8 Q2 C10 PHASE B C1 R5 R11 Q5 VBB R3 R9 Q3 GND D1 PHASE C R6 R12 Q6 LSS VDD ET Package Typical PCB Layout SPEED ET Package Schematic Corresponding to Typical PCB Layout Trace (2 oz.) CA SA GHA CP2 VREG GLA CB PAD SB GHB VDD C5 Ground (1 oz.) R4 R1 R10 R7 Q1 GLB FAULT C2 Q4 A4915 Solder Signal (1 oz.) PCB TDEAD OUTA C9 R2 R8 Q2 VBB R5 R11 Q5 R15 ENABLE DIR Thermal (2 oz.) Thermal Vias BRAKEn HA HB HC LSS GLC GHC A4915 R24 CP1 VBB C4 GND C8 CC SC OUTB C10 R3 R9 Q3 C1 R6 VDD R12 Q6 OUTC Figure 3. Typical application information for ET package Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A4915 3-Phase MOSFET Driver VDD LSS Q6 R12 R6 Q3 R9 Q5 R11 R5 PHASE C D1 GND C1 R3 PHASE B C10 Q2 R8 R15 C5 C9 R2 C4 C8 GND VBB R24 GND C7 C6 Q4 R10 R4 Q1 R7 PHASE A R1 GND C2 LP Package Typical PCB Layout VDD OUTC LSS Q6 R12 R6 C1 Q3 R9 R3 CC A4915 Q5 R11 R5 VBB Q2 A4915 R8 R2 C9 OUTA Solder Trace (2 oz.) R15 FAULT GLB PAD VDD Q4 R10 R4 C5 R24 GHB SB TDEAD CB SPEED VBB Signal (1 oz.) PCB HC HB HA BRAKEn DIR ENABLE GHC SC C10 OUTB LP Package Schematic Corresponding to Typical PCB Layout GLC GLA C4 Ground (1 oz.) Thermal (2 oz.) Q1 Thermal Vias C2 R7 R1 C8 GHA SA GND CA CP1 VREG CP2 Figure 4. Typical application information for LP package Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A4915 3-Phase MOSFET Driver Input / Output Structures VBB VDD VREG FAULT CP1 VDD CP2 2 kΩ BRAKE DIR ENABLE 18V 6V 18V 18V 6V 50 kΩ 18V 14V Figure 6. Fault output Figure 5. Supplies 6V Figure 7. Charge pump 6V Figure 8. Logic inputs with pull-down: BRAKEn, DIR, ENABLE Cx 18V VDD VDD 50 kΩ HA HB HC 18V GHx VDD 18V 14V Sx 5 kΩ SPEED 2 kΩ VREG 6V 6V 6V 6V 18V 18V GLx LSS Figure 9. Hall inputs with pull-up: HA, HB, HC Figure 10. Gate drive outputs Figure 11. Speed input Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A4915 3-Phase MOSFET Driver Package ET, 28-Pin QFN with Exposed Thermal Pad 0.30 5.00 ±0.15 1.15 28 1 2 0.50 28 1 A 5.00 ±0.15 3.15 4.80 3.15 29X D SEATING PLANE 0.08 C C 4.80 C +0.05 0.25 –0.07 PCB Layout Reference View 0.90 ±0.10 0.50 For Reference Only; not for tooling use (reference JEDEC MO-220VHHD-1) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 0.73 MAX A Terminal #1 mark area B 3.15 2 1 28 3.15 B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A4915 3-Phase MOSFET Driver Package LP, 28-Pin TSSOP with Exposed Thermal Pad 0.45 9.70±0.10 8º 0º 28 0.65 28 0.20 0.09 1.65 B 3 NOM 4.40±0.10 3.00 6.40±0.20 6.10 0.60 ±0.15 A 1 2 1.00 REF 5.08 NOM 0.25 BSC Branded Face 28X SEATING PLANE 0.10 C 0.30 0.19 0.65 BSC 1 2 5.00 SEATING PLANE GAUGE PLANE C C PCB Layout Reference View For Reference Only; not for tooling use (reference MO-153 AET) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 1.20 MAX 0.15 0.00 A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A4915 3-Phase MOSFET Driver Revision History Revision Current Revision Date Rev. 1 April 1, 2013 Description of Revision Update EC table parameters Copyright ©2012-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17