A8509 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver Features and Benefits Description • Four integrated high current sinks for LED strings; can be tied together for even higher currents • Fixed frequency current mode control with integrated gate driver / boost controller; powerful gate driver to drive an external N-channel MOSFET allows significant scaling capability on the number of LEDs per string • Parallel operation with one boost controller (master) and up to three additional slave controllers; can run up to 16 strings of LEDs while populating only a single master boost regulator • Active current sharing between LED strings for 0.7% accuracy and 0.8% matching • Wide input voltage range: 9 to 40 V • Internal bias supply for single-supply operation (typically VIN = 12 or 24 V) • Separate Enable and PWM pins as interface for Enable and PWM Dimming functions • Fset / Sync function to either set the boost converter switching frequency or synchronize at up to 800 kHz • Protection Features ▫ Open or shorted LED pin protection ▫ Open Schottky protection ▫ Pulse-by-pulse current limit ▫ Overtemperature protection (OTP) The A8509 is a multi-output white LED driver for backlighting LCD panels. It integrates a current-mode boost controller and four individual current sinks. Packages The boost controller architecture allows for significant scaling of boost voltage to optimize the solution for the required number of LEDs per string. The FSET/SYNC pin either sets the required boost switching frequency or synchronizes the value in the range of 300 to 800 kHz. The LED sink current value is set by an external ISET resistor (see figure 1). The four LED sinks can also be combined to achieve even higher current per LED string. The A8509 provides protection against output shorts and overvoltage, open or shorted LED pins, and overtemperature. A dual-level, pulse-by-pulse current limit function provides soft start and protects the external current switch against high current overloads. As an option, the A8509 can drive an ¯¯T ¯ pin to disconnect the external P-FET interfaced to the ¯F¯A¯¯U¯¯L input supply from the system in the event of short-to-ground in the boost converter. Package options are 24-pin TSSOP (suffix LP) and SOICW (LB) packages. The TSSOP has an exposed thermal pad, and the SOICW has four interally-fused pins, for enhanced thermal dissipation. The Both packages are lead (Pb) free, with 100% matte tin leadframe plating. (Not to scale) 24-pin TSSOP with Exposed Thermal Pad (LP package) 24-pin SOICW with Four Internally-Fused Pins (LB package) Typical Application VIN RISET Value versus LED Current RISET (kΩ) 30.00 L1 VDD 25.00 VIN FAULT 15.00 10.00 60 100 140 180 220 260 GATE SENP ILED (mA) Figure 1. Typical application circuit showing 4 channels of LEDs; RZ-CZ optional (component list shown in the Typical Applications section) CDR CDD RFSET RISET SENN A8509 OVP MODE LED2 LED3 LED4 PAD RZ CZ CP ROVP LED1 EN VDR VDD FSET/SYNC ISET COMP 300 VOUT RSENSE PWM 5.00 A8509-DS COUT Q1 R1 20.00 D1 CIN AGND PGND Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Selection Guide Part Number Packing1 Package A8509GLPTR-T 24-pin TSSOP with exposed thermal pad A8509GLBTR-T2 24-pin SOICW with internally-fused leads 1Contact Allegro® for additional packing options. 2Contact factory for availability. 4000 pieces per 13-in. reel Contact factory Absolute Maximum Ratings* Characteristic Symbol Notes Rating Unit LEDx Pin Voltage VLEDx –0.3 to 55 V OVP Pin Voltage VOVP –0.3 to 60 V VIN Pin Voltage ¯F ¯¯A¯U¯¯L¯¯T ¯ Pin Voltage COMP, EN, FSET/SYNC, ISET, MODE, PWM, SENN, SENP, and VDD Pin Voltage VIN –0.3 to 40 V VFAULT –0.3 to 40 V – –0.3 to 5.5 V GATE, VDR Pin Voltage – Operating Ambient Temperature TA Maximum Junction Temperature Storage Temperature –0.3 to 8 V –40 to 105 ºC TJ(max) 150 ºC Tstg –55 to 150 ºC G temperature range *Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Thermal Characteristics may require derating at maximum conditions, see application information Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* Value Unit Package LP, on 4-layer PCB based on JEDEC standard 28 ºC/W Package LB, on 4-layer PCB based on JEDEC standard 35 ºC/W *Additional thermal information available on the Allegro website Table of Contents Specifications Functional Block Diagram Pin-out Diagram and Terminal List Electrical Characteristics Table Functional Description Enabling the IC Powering up: LED pin short-to-GND check Soft start function Frequency selection Synchronization LED current setting and LED dimming PWM dimming Analog dimming Boost switch overcurrent protection Setting the current sense resistor Current sense resistor routing 2 3 4 5 8 8 8 9 10 10 11 12 12 13 13 13 Pulse-by-pulse current limit Secondary boost switch limit Output overvoltage and undervoltage protection LED Open Detect Undervoltage Protection (UVP) LED short detect Input UVLO VDD and VDR Shutdown Fault protection during operation Application Information Paralleling more than one A8509 Design Example Typical Applications Typical Applications Package Drawings 14 14 14 15 15 16 16 16 17 17 19 19 21 24 25 27 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Functional Block Diagram VDR GATE SENP SENN Regulator UVLO VIN 1.25 V Ref Internal VDD ∑ FSET/SYNC Oscillator VREF2 FB AGND – Driver Circuit + + Fault – + COMP VREF Current Sense Internal Soft Start – VDD ISS MODE Thermal Shutdown EN Enable Fault 100 kΩ OVP/UVP Sense + 70 kΩ OVP VREF – 50 μA PWM PWM Open/Short LED Detect 100 kΩ ISS VREF1 LED1 LED2 LED3 LED4 LED Driver ISET ISET FAULT FB AGND PAD LP Package Only PGND AGND Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Pin-out Diagrams SENP 1 24 SENN SENN 1 24 PGND GATE 2 23 PGND SENP 2 23 NC VDR 3 22 LED1 GATE 3 22 LED1 VDR 4 21 LED2 COMP 4 21 NC MODE 5 20 LED2 COMP 5 NC 6 19 AGND MODE 6 NC 7 18 AGND EN 7 EN 8 17 LED3 PWM 8 PWM 9 16 LED4 FSET/SYNC 9 16 LED3 15 VIN ISET 10 15 LED4 ISET 11 14 OVP VDD 11 14 VIN VDD 12 13 FAULT FSET/SYNC 10 20 NC PAD 18 AGND 17 NC 13 OVP FAULT 12 LB Package 19 AGND LP Package Terminal List Table Name Number LB LP Function AGND 18, 19 18, 19 COMP 4 5 LED ground. Output of the error amplifier and compensation node. Connect a compensation network from this pin to ground. EN 8 7 Enable for the A8509. ¯F ¯¯A¯U¯¯L¯¯T ¯ 13 12 This pin is used to indicate a fault condition. Connect a pull-up resistor between this pin and the required logic level voltage. The pin is an open drain type configuration that will be pulled low when a fault occurs. FSET/SYNC 10 9 Frequency/synchronization pin. A resistor RFSET from this pin to ground sets the switching frequency. This pin can also be used to synchronize two or more converters in the system. GATE 2 3 Gate pin for driving external N-channel FET. ISET 11 10 Connect the RISET resistor between this pin and ground to set the 100% LED current. LED1 LED2 LED3 LED4 22 20 17 16 22 21 16 15 Connect the cathode of each LED string to these pins. MODE 5 6 This pin is used to determine the mode of operation. MODE high tied to VDD allows parallel operation, and MODE low is used for single IC operation. NC 6, 7, 21 OVP 14 13 This pin is used to sense an Overvoltage (OVP) condition. Connect the ROVP resistor from VOUT to this pin to adjust the overvoltage protection. PAD n.a. – For TSSOP package, this exposed pad provides enhanced thermal dissipation. This pad must be connected to the ground plane(s) of the PCB with at least 8 vias, directly in the PAD solder pad. PGND 23 24 Power ground for the internal gate driver circuit. PWM 9 8 PWM dimming pin. Used to control the LED intensity by using pulse width modulation. The typical PWM dimming frequency is in the range of 100 to 1000 Hz. SENN 24 1 Negative sense line for boost switch current sensing. SENP 1 2 Positive sense line for boost switch current sensing. VDD 12 11 Output of internal LDO regulator. Connect a 0.1 μF decoupling capacitor between this pin and ground. VDR 3 4 Output of the gate driver bias voltage regulator. Connect a 1 μF decoupling capacitor between this pin and ground. VIN 15 14 Input power to the A8509. 17, 20, 23 No connection. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 ELECTRICAL CHARACTERISTICS1 Valid at VIN = 12 V, TA = 25°C, indicates specifications guaranteed by design and characterization over the full operating temperature range with TA = TJ = –40°C to 105°C; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit 9 – 40 V Input Voltage Specifications Operating Input Voltage Range VIN UVLO Start Threshold VUVLO(th) VIN rising − – 8.5 V UVLO Hysteresis VUVLO(hys) VIN falling − 400 – mV EN = VIH ; fSW = 800 kHz, no load − 7 − mA VIN = 12 V, EN = FSET/SYNC = 0 V − 0.5 10.0 μA Input Currents Input Quiescent Current Input Sleep Supply Current IQ IQSLEEP Input Logic Levels (EN, PWM, MODE, FSET/SYNC) Input Logic Level-Low VIL 9 V < VIN < 40 V – – 400 mV Input Logic Level-High VIH 9 V < VIN < 40 V 1.5 – – V Rpulldown EN, PWM = 5 V − 100 − kΩ MODE=2.5 V − 70 − kΩ − 47 − dB EN, PWM pins Pull-Down Resistor MODE Pin Pull-Down Resistor RMODE Error Amplifier Open Loop Voltage Gain Transconductance Source Current AVOL gm IEA(SRC) ΔICOMP = ±10 μA − 990 − μA/V VCOMP = 1.5 V − –360 − μA Sink Current MODE High IEA(SINK)H VCOMP = 1.5 V, MODE = VIH − 80 − μA Sink Current MODE Low IEA(SINK)L VCOMP = 1.5 V, MODE = VIL − 360 − μA ¯F ¯¯A¯U¯¯L¯¯T ¯ =0 − 1.5 − kΩ − 200 − mV 1.11 1.25 1.4 V 45 49 53 μA VUVP(LOW) Falling − 100 − mV VUVP(HIGH) Rising − 120 − mV Measured at GATE pin − 7 – V COMP Pin Pull-Down Resistor Soft Start COMP Level RCOMP VCOMPSS Overvoltage Protection Overvoltage Threshold OVP Sense Current Output Undervoltage Threshold VOVP(th) OVP connected to VOUT IOVPH Boost Switch Gate Driver Gate Driver Voltage VDRV Driver Pull-up and Pull-down Resistance RGATEUD Measured at VGATE =VDRV / 2 − 4.5 – Ω Driver to Ground Resistance RGATEG EN = 0, VIN = 0 − 200 − kΩ Sense Positive VSENSEP 85 100 115 mV VSENSESEC − 165 − mV Secondary Sense Positive Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 ELECTRICAL CHARACTERISTICS1 (continued) Valid at VIN = 12 V, TA = 25°C, indicates specifications guaranteed by design and characterization over the full operating temperature range with TA = TJ = –40°C to 105°C; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit − 39 − mV Boost Switch Gate Driver (continued) Soft Start Boost Current Limit Reference Voltage VSWSS(LIM) Reference voltage for boost switch current limit during soft start Minimum Switch On-Time tSWONTIME − − 110 ns Minimum Switch Off-Time tSWOFFTIME − − 85 ns RFSET = 7.5 kΩ 725 800 875 kHz RFSET = 10 kΩ 540 600 660 kHz RFSET = 20 kΩ − 300 − kHz RFSET = 8.25 kΩ − 1.00 − V fSWSYNC 300 − 800 kHz Synchronization Input Minimum Off-Time tPWSYNCOFF 150 − − ns Synchronization Input Minimum On-Time tPWSYNCON 150 − − ns – 0.7 – % Oscillator Frequency Oscillator Frequency FSET/SYNC Pin Voltage fSW VFSET Synchronization Synchronized PWM Frequency LED Current Sinks LEDx Accuracy ErrLED ISET = 80 μA LEDx Matching ΔLEDx ISET = 80 μA – 0.8 2.5 % LEDx Regulation Voltage VLED VLED1 through VLED4 all equal, ISET = 80 μA − 650 − mV ISET to ILEDx Current Gain AISET ISET = 80 μA ISET Pin Voltage VISET Allowable ISET Current ISET − 2320 − A/A − 1.000 − V 34 − 130 μA 4.6 − − V LEDx Pin Short Detect VLEDSC While LED sinks are in regulation, sensed from LEDx pin to GND Soft Start LEDx Current Gain ILEDSS Current through each enabled LEDx pin during soft start, RISET = 12.4 kΩ − 88 − A/A PWM High to LED-On Delay tdPWM(on) Time between PWM enable and LEDx current reaching 90% of maximum − 0.5 1.1 μs PWM Low to LED-Off Delay tdPWM(off) Time between PWM enable going low and LEDx current reaching 10% of maximum − − 500 ns Continued on the next page… Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 ELECTRICAL CHARACTERISTICS1 (continued) Valid at VIN = 12 V, TA = 25°C, indicates specifications guaranteed by design and characterization over the full operating temperature range with TA = TJ = –40°C to 105°C; unless otherwise noted Characteristics Symbol Test Conditions Min. Typ. Max. Unit IFAULT = 1 mA (400 Ω internal switch resistance) − 0.4 − V VFAULT = 5 V − − 1 μA − 165 − ºC − 20 − ºC ¯F ¯¯A¯¯U¯¯L ¯¯T ¯ Pin ¯F ¯¯A¯U¯¯L¯¯T ¯ Pin Pull-Down Voltage VFAULT ¯F ¯¯A¯U¯¯L¯¯T ¯ Pin Leakage Current IFAULTLKG Thermal Protection (TSD) Thermal Shutdown Threshold2 TSD Thermal Shutdown Hysteresis2 TSDHYS Temperature rising 1For LEDx Regulation Voltage, VREGx (mV) input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). 2Ensured by design and characterization, not production tested. 654 653 652 651 650 649 648 647 646 645 644 643 -40 -20 0 20 40 60 80 100 Junction Temperature, TJ (°C) Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Functional Description Enabling the IC The IC turns on when a logic high signal is applied on the EN pin, and the input voltage present on the VIN pin is greater than the 8.5 V necessary to clear the UVLO (VUVLOrise ) threshold. Before the LEDs are enabled, the A8509 driver goes through a system check to determine if there are any possible fault conditions that might prevent the system from functioning correctly. Powering up: LED pin short-to-GND check After the VIN pin goes above the UVLO threshold, and a high signal is present on the EN pin, the IC proceeds to check if any LEDx pins are shorted to GND and/or are not used. Each unused pin should be connected to GND with a 2.4 kΩ pull-down resistor. After the voltage threshold on the LEDx pins exceeds 120 mV, a timer of 1536 clock cycles (2 ms at 800 kHz switching frequency, see figure 2) is applied during which the A8509 determines the status of the pins. Any unused pin connected to GND with the pull-down resistor will be taken out of regulation at this point and will not contribute to the boost regulation loop (see figure 3). A typical example is shown in figure 4. When a pin is connected to GND through a 2.4 kΩ resistor, the voltage on that LEDx pin during the LED detection period is about 200 mV. This is shown in figure 2. If an LEDx pin is shorted to ground such that LEDx pin voltage is < 100 mV, the A8509 will not proceed with soft start until the short is removed from the LEDx pin. This prevents the A8509 VOUT C1 VEN C2 VLEDa(not used) C3 VLEDb(used) C4 t Figure 3. LED detect circuit operation for an LED pin that is not being used; shows VOUT (ch1, 10 V/div.), VEN (ch2, 5 V/div.), an unused LEDx with a 2.4 kΩ resistor from this pin to GND, VLEDa (ch3, 500 mV/div.), and a used LEDx, VLEDb (ch4, 500 mV/div.), t = 2 ms/div. A8509 A8509 GND LED1 LED1 LED2 LED2 LED3 LED3 LED4 GND LED4 2.4 kΩ Figure 4. Channel select setup: (left) channel LED4 not used, (right) using all channels. VOUT VOUT C1 C2 VEN C1 VEN C2 VLEDa C3 Short removed LED detection period C3 VLEDa (with temporary short) LED detection period C4 VLEDb VLEDb (no short) C4 t Figure 2. LED detect circuit operation for two connected LEDs at fSW = 800 kHz; shows VOUT (ch1, 10 V/div.), VEN (ch2, 5 V/div.), an LEDx, VLEDa (ch3, 500 mV/div.), another LEDx, VLEDb (ch4, 500 mV/div.), t = 2 ms/div. t Figure 5. LED detect circuit operation: device powers-up after the short is removed from the LED pin; shows VOUT (ch1, 10 V/div.), VEN (ch2, 5 V/ div.), an LEDx with short, VLEDa (ch3, 500 mV/div.), and an LEDx without short, VLEDb (ch4, 500 mV/div.), t = 2 ms/div. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 from powering-up and putting an uncontrolled amount of current through the LEDs. After the short is removed the affected LEDx pin will rise up to the 500 mV level. When the LEDx pin voltage exceeds the 260 mV threshold, the IC detects connected LEDs and proceeds with LED detection and soft start. Figure 2 shows a case when two LED channels are enabled. During the LED detection period, voltage on both LEDx pins > 260 mV. Figure 5 shows a case with LEDa temporarily shorted to ground and LEDb in normal operation. When the converter senses that there is enough voltage on the LEDx pins, the converter proceeds to increase the LED current to the preset regulation current and the boost switch current sense voltage limit is switched to the ISW(LIM) level to allow the A8509 to deliver the necessary output power to the LEDs (figure 8). Soft start function VEN During soft start the LED current gain is reduced to (ILEDSS). As an example, for a 240 mA output current, the soft-start LED current would be set to about 9 mA (see figure 7). Also during soft start the boost switch sense voltage is reduced to the VSWSS(LIM) level, to limit the initial inrush current generated by the charging of the output capacitors. The actual current limit (ILIM) is equal to: ILIM = VSWSS(LIM) / RSENSE (1) where VSWSS(LIM) is found in the Electrical Characteristics table, and RSENSE is the current sense resistor value. VEN C1 IIN limited by boost switch to VSWSS(lim) / RSENSE C1 IIN limited by boost switch to VSWSS(LIM) / RSENSE IIN C2 IOUT C3 VOUT C4 t Figure 7. Start-up operation, individual LEDx current = 240 mA, boost sense resistor = 0.010 Ω; shows VEN (ch1, 2 V/div.), IIN (ch2, 2 A/div.), IOUT (ch3, 1 A/div.), and VOUT (ch4, 20 V/div.), t = 500 μs/div. Boost starts operating in normal current limit VSW(LIM) VEN C1 VCOMP C2 IIN IIN limited by boost switch to VSWSS(LIM) / RSENSE C2 C3 IOUT IIN C3 VOUT C4 VOUT sufficient to begin normal power-up VOUT t Figure 6. Start-up operation, individual LEDx current = 120 mA, boost sense resistor = 0.020 Ω; shows VEN (ch1, 2 V/div.), IIN (ch2, 1 A/div.), IOUT (ch3, 200 mA/div.), and VOUT (ch4, 20 V/div.), t = 500 μs/div. C4 t Figure 8. Normal start-up behavior; shows VEN (ch1, 2 V/div.), VCOMP (ch2, 2 V/div.), IIN (ch3, 1 V/div.), and VOUT (ch4, 10 V/div.), t = 500 μs/div. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Frequency selection VOUT The switching frequency on the boost regulator is set by connecting a resistor between the FSET/SYNC pin and ground. The switching frequency range is 300 to 800 kHz, with example values of: RFSET Value (kΩ) 800 10 600 IIN FSET/SYNC shorted to GND C1 Swtiching Frequency, fSW (kHz) 7.5 VFSET/SYNC C2 C3 IOUT C4 The relationship of RFSET and fSW is shown in figure 9. The FSET/SYNC pin has short-to-ground protection. If the FSET/SYNC pin is held low for more than 4 μs typical, the A8509 will stop switching and disable the LEDx pins (see figures 10 and 11). If the FSET/SYNC pin is released at any time after 7 μs, the A8509 will proceed to soft start but will not perform the LED detection phase. t Figure 10. Shutdown when the FSET/SYNC pin is shorted to ground; shows VOUT (ch1, 10 V/div.), VFSET/SYNC (ch2, 1 V/div.), IIN (ch3, 2 A/div.), and IOUT (ch4, 500 mA/div.), t = 200 μs/div. VOUT VFSET/SYNC C2 Synchronization IIN The A8509 can also be synchronized by using an external clock connected to the FSET/SYNC pin. The synchronization function of IC was designed to work with a push-pull type of clock driver. The amplitude of the clock signal should be between 1.5 and 3.3 V. The synchronization clock should have duty cycles that meet the minimum on/off times. Figure 12 shows the timing for a synchronization clock into the A8509 at 800 kHz. The 150 ns minimum on-time and 150 ns minimum off-time are Switching Frequency, fSW (kHz) FSET/SYNC shorted to GND 900 800 C1 C3 IOUT C4 t Figure 11. Zoomed-in view of figure 9, showing quick shutdown when FSET/SYNC shorted to ground, preventing IC running at very high frequency; shows VOUT (ch1, 10 V/div.), VFSET/SYNC (ch2, 1 V/div.), IIN (ch3, 2 A/div.), and IOUT (ch4, 1 A/div.), t = 10 μs/div. 700 t PWSYNCON 600 150 ns 500 950 ns 400 300 200 7 9 11 13 15 17 19 FSET Resistor Value, RFSET (kΩ) Figure 9. Switching Frequency as determined by RFSET value. 21 150 ns T = 1.25 μs t PWSYNCOFF Figure 12. SYNC pulse minimum on and off time requirements, for an 800-kHz clock. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 indicated by the specifications for tPWSYNCON and tPWSYNCOFF . Thus any pulse with a duty cycle of 19% to 85% at 800 kHz will synchronize the IC. It is recommended to also use the RFSET resistor with the external clock signal. If a synchronization clock is lost during operation, the IC will revert to the preset switching frequency that is set by the RFSET resistor. In this configuration the preset frequency does not have any restrictions other than the normal operating range of 300 to 800 kHz. During the changeover period the IC stops switching for an approximately 5 μs period to allow for the synchronization detection circuitry to switch over to external preset switching frequency. Although examples shown in figures 13 and 14 are extreme cases of clock-to-resistor frequency changes, it is recommended that actual applications not have such large switching frequency changes. In most applications the RFSET resistor and clock frequency should be very close to each other in terms of frequency. Setting the frequencies close together will prevent the system from experiencing large changes on frequency-dependent signals and components, such as the inductor ripple current and the compensation resistor and capacitor. C1 VCOMP C2 IOUT C3 VFSET/SYNC C4 t Figure 13. Synchronization feature with 200 kHz difference between RFSET and external clock signal. The synchronization frequency is 600 kHz, and the resistor preset frequency is 800 kHz. Note that there is very little disturbance in the LED current at the time of changeover; shows VGATE (ch1, 5 V/div.), VCOMP (ch2, 1 V/div.), IOUT (ch3, 1 A/div.), and VFSET/SYNC (ch4, 5 V/div.), t = 5 μs/div. LED current per LED, ILED (mA) 7.87 9.53 11.5 14.3 19.1 300 240 200 160 120 C1 fSW = 300 Hz from SYNC pulse VGATE VCOMP C2 (2) where RISET is in Ω, and ILED is in A. This sets the maximum current through the LEDs, referred to as the 100% current. Standard RISET values are as follows: Standard Resistor Value Closest to RISET (kΩ) Changeover period fSW = 800 Hz from RFSET value The maximum LED current can be up to 300 mA per channel. The LED current is set through the RISET resistor connected between the ISET pin and ground. The ILED current is set according to the following formula: fSW = 600 kHz from SYNC pulse VGATE LED current setting and LED dimming RISET = (1.000 / ILED ) × 2320 Changeover period fSW = 800 kHz from RFSET value IOUT C3 VFSET/SYNC C4 t Figure 14. Synchronization feature with 500 kHz difference between RFSET and external clock signal, illustrating the flexibility of the RFSET/SYNC pin; synchronization frequency is 300 kHz, and the resistor preset frequency is 800 kHz; shows VGATE (ch1, 5 V/div.), VCOMP (ch2, 1 V/div.), IOUT (ch3, 1 A/div.), and VFSET/SYNC (ch4, 5 V/div.), t = 10 μs/div. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 The cited values are for 1% tolerance resistors. If the calculated value was not present, the next lowest value of 1% resistor was chosen. VOUT IOUT PWM dimming C1 Applying an external PWM signal on the PWM pin performs PWM dimming. When the PWM pin is pulled high, the A8509 enables the LEDx pins to sink 100% current. When PWM is pulled low, the boost converter and LEDx sinks are turned off. The compensation (COMP) pin is floated, and critical internal circuits are kept active. C2 C3 C4 VPWM The typical PWM dimming frequencies fall between 100 and 1000 Hz. Figures 15 and 16 show examples of dimming at 50% and 0.5% duty cycles. t Figure 15. PWM dimming: fSW = 200 Hz, 50% duty cycle, VOUT = 30 V, VIN = 12 V, and ILED = 240 mA per LED string; shows VOUT (ch1, 10 V/div.), IOUT (ch2, 500 mA/div.), VCOMP (ch3, 2 V/div.), and PWM (ch4, 5 V/div.), t = 2 ms/div. Analog dimming VOUT The A8509 can also be dimmed by using an external DAC or other voltage source applied either directly to the ground side of the RISET resistor or through an external resistor to the ISET pin (see figure 17). The ISET current can be varied in the range between 34 μA and 130 μA. VISET – VDAC RISET C2 C3 (3) where VISET is the ISET pin voltage and VDAC is the DAC output voltage. • For a dual-resistor configuration (panel B of figure 17), the ISET current is controlled by the following formula: ISET = VISET VDAC – VISET – RISET R1 (4) The advantage of this circuit is that the DAC voltage can be higher or lower, thus adjusting the LED current to a higher or lower value of the preset LED current set by the RISET resistor: ▫ VDAC = 1.00 V: output is strictly controlled by RISET ▫ VDAC > 1.00 V: LED current is reduced ▫ VDAC < 1.00 V: LED current is increased C1 IOUT • For a single-resistor configuration (panel A of figure 17), the ISET current is controlled by the following formula: ISET = VCOMP C4 VCOMP VPWM t Figure 16. PWM dimming: fSW = 200 Hz, 0.5% duty cycle, VOUT = 30 V, VIN = 15 V, ILED = 240 mA per LED string; shows VOUT (ch1, 10 V/div.), IOUT (ch2, 500 mA/div.), VCOMP (ch3, 2 V/div.), and VPWM (ch4, 5 V/div.), t = 10 μs/div. DAC R ISET VDAC GND DAC GND A R1 A8509 VDAC GND A8509 ISET ISET R ISET GND B Figure 17. Typical application simplified diagram of voltage LED current control using a DAC to control LED current. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A8509 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver Boost switch overcurrent protection RSENSE SENN Current Sense – Setting the current sense resistor The current sense resistor (see figure 18) is set according to the following formula: VSENP (5) ILIM = RSENSE SENP A8509 + The boost switch is protected with pulse-by-pulse current limiting set by the external RSENSE resistor. There also is a secondary current limit that is sensed on the boost switch. Figure 18. Simplified schematic of the current sense resistor connections to the current sense amplifier. where VSENP is found in the Electrical Characteristics table, and RSENSE is the current sense resistor value. The current limit is calculated by the following formula: ∆IL ILIM = IIN(max) + 2 RSENSE A A (6) where IIN(max) is the maximum input current, and ΔIL is the inductor current ripple. Current sense resistor routing The current sense resistor must be routed as a differential pair to minimize measurement accuracy errors. For most current sense resistors the resistance is measured between the inside edges of the mounting pads of the RSENSE resistor. Figure 19 shows correct differential current sensing connections to the A8509. The individual current sense traces are kept short and side-by-side to get proper signal voltage levels. The trace for the positive sense pin (SENP) must be routed to the inside edge of the mounting pad on the high side of RSENSE. The trace for the negative sense pin (SENN) must be routed to the inside edge of the mounting pad on the ground side of RSENSE. It should be noted that when designing the PCB layout, the trace for the negative sense pin (SENN) is often automatically merged with the ground flood fill and with the mounting pad on the ground side of RSENSE (shown in figure 20). However, the trace must be kept separate and dedicated, and careful attention must be given when routing the PCB. GND B A8509LP SENN SENP Figure 19. Correct layout of current sense resistor traces: (A) connect to inside edges of pads, (B) parallel and dedicated RSENSE A SENN SENP B GND A8509LP Figure 20. Incorrect layout of current sense resistor traces: (A) do not connect to outside edge of pad, (B) do not merge trace into ground Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Pulse-by-pulse current limit Figure 21 illustrates the normal waveform for the current sense signal. The pulse-by-pulse current limit is designed to limit the current through the external MOSFET to prevent failure. When the VSENSEP threshold is reached, the IC stops switching to allow the inductor current to fall. Operation of pulse-by-pulse current limiting is shown in figure 22. Secondary boost switch limit In case there is an inductor short during operation ,the A8509 has a secondary switch current limit. When this threshold is reached, the IC immediately shuts down. The level of this current limit is set above the pulse-by-pulse current limit to protect the switch from destructive currents when the boost inductor is shorted. Output overvoltage and undervoltage protection IL C1 C2 C3 Normal spikes due to switching VSENSE The OVP pin on the A8509 controls both the overvoltage (OVP) and undervoltage (UVP) protection features. The pin circuit is shown in figure 23. The OVP protection protects the boost converter from excessive voltage levels when the feedback control loop is broken, usually caused by an open connection from output voltage to the LEDs. The UVP function provides output voltageto-ground short protection when an external disconnect switch is used. For more detailed information on disconnect switch application, see the Undervoltage Protection (UVP) section. For proper operation of this pin, due to the relatively low voltage level, special care has to be taken during PCB layout. Figure 24 is an example of a proper PCB layout. VGATE t VOUT ROVP A8509 + – Figure 21. Current sense signal (VSENSE) during normal operation, showing large spikes that are filtered out by a blanking period to avoid false overcurrent tripping; RSENSE = 10 mΩ; shows inductor current IL (ch1, 1 A/div.), VSENSE (ch2, 20 mV/div.), and gate voltage of the main boost switch VGATE (ch3), t = 500 ns/div. OVP – + UVP 50 μA 100 mV Figure 23. Simplified schematic of the Overvoltage Protection section. IL VOUT OVP A8509LP C2 C1 OVP 1.25 V A VCOMP ROVP VOUT C3 B C4 VGATE t Figure 22. Typical pulse-by-pulse current limit; shows IL (ch1, 2 A/div.), VOUT (ch2, 10 V/div.), VCOMP (ch3, 2 V/div.), and VGATE (ch4), t = 500 ns/div. Figure 24. Simplified schematic of the OVP resistor connections; (A) connection should be short, (B) connection to VOUT can be long, and ROVP should be as close to the OVP pin as possible. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 LED Open Detect When any LED string opens, the boost control circuit increases the output voltage until it reaches the overvoltage protection level. The OVP event causes any LED string that is below regulation level to be disabled. After disabling the open string, the output voltage returns to normal operating voltage. An EN low signal will reset the LED string regulation lock. Figure 25 shows a typical overvoltage condition when the output voltage is disconnected from the LED load. Figure 26 shows an VOUT Undervoltage Protection (UVP) If the output voltage is shorted to ground the OVP pin will sense an undervoltage condition (UVP). When UVP is sensed, the IC sets the Fault flag low which, if used to interface to the outputdisconnect switch, will shut off the P-FET device. Figure 28 is a schematic showing the input disconnect switch implementation. OVP limit is reached, and string is removed from control loop VOUT (30 V) OVP level Fault occurrence IOUT C2 extended view of the same situation. Figure 27 shows an OVP condition created by a single open LED string. VLEDx VCOMP C2 C1 Control loop reduces VOUT to new regulation level LED string opens IOUT C3 VCOMP begins to decrease C3 t t Figure 25. OVP operation with all LEDx pins open. VOUT rises to the overvoltage level and stays there until the IC is shut down; shows VOUT (ch1, 20 V/div.), IOUT (ch2, 1 A/div.), and VCOMP (ch3, 2 V/div.), t = 2 ms/div. Figure 27. OVP condition created by an open LED string; shows VOUT (ch1, 2 V/div.), pin voltage VLEDx (ch2, 5 V/div.), and IOUT (ch3, 200 mA/div.), t = 2 ms/div. OVP level 10 kΩ VOUT C2 L1 VIN IOUT Periodic switch node bursts occur when all LEDx pins are open C1 VCOMP C3 VDR CIN (optional) AO4421 1 kΩ 1 kΩ 2N7002 VSW A8509 FAULT C4 t Figure 26. Extended view of the OVP condition in figure 25; shows VOUT (ch1, 20 V/div.), IOUT (ch2, 1 A/div.), VCOMP (ch3, 1 V/div.), and switch node (VSW) (ch4, 20 V/div.), t = 10 ms/div. Figure 28. Simplified schematic of an external disconnect switch implementation. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 The waveforms in figure 29 show the operation of the disconnect feature. LED short detect All LEDx pins are rated for 55 V, thus allowing LEDx pin-toVOUT short protection in case of a connector short. Any LEDx pin that has a voltage exceeding VLEDSC will be removed from operation. This is to prevent the IC dissipating too much power by having a large voltage present on the LEDx pins. Input UVLO When VIN rises above the UVLO threshold (VUVLO(th) ), the A8509 is enabled. It is disabled when VIN falls below VUVLO(th) – VUVLO(hys) for more than 2 μs. This lag is to avoid shutdown because of momentary glitches in the power supply. VDD and VDR The VDD pin provides the regulated bias supply for the internal circuits. A capacitor with a value in the range 0.1 to 1 μF should be used to decouple the internal analog and digital circuitry. VOUT VOUT VEN C1 Output short occurrence C2 IIN C2 FAULT C3 IOUT C1 C3 VLEDx VGATE(PMOS) IIN C4 C4 t Figure 29. Input disconnect switch shutdown during an output short ¯¯A¯U¯¯L¯¯T ¯ (ch3, condition; shows VOUT (ch1, 20 V/div.), IIN (ch2, 10 A/div.), ¯F 5 V/div.), and PMOS device VGATE (ch4, 5 V/div.), t = 50 μs/div. VLEDSC is detected t Figure 30. Typical shorted LED: when voltage exceeds VLEDSC , the LED is disabled and remains disables until either the EN pin is toggled or the power cycled; shows VOUT (ch1, 20 V/div.), VEN (ch2, 5 V/div.), IOUT (ch3, 0.5 A/div.), and VLEDx (ch4, 10 V/div.), t = 10 μs/div. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 The VDR circuit provides power to the gate driver of the A8509. For VDR the decoupling capacitor value should fall in the range 0.47 to 1 μF. A 1 μF capacitor is recommended. Shutdown If the EN pin is pulled low, the IC will shut down immediately. Fault protection during operation The A8509 device constantly monitors the state of the system to determine if any fault conditions occur during normal operation. The response to a triggered fault condition is summarized in table 1. The possible fault conditions that the part can detect are: • Open LED pin • Shorted inductor with second level switch current protection • VOUT short-to-ground • ISET pin short-to-ground • FSET pin short-to-ground • Shorted LED • Open Schottky diode • Short Schottky diode protection with second level switch current protection • Thermal shutdown (TSD) • Overvoltage protection (OVP) VOUT 1 C1 2 IIN C2 Soft start and power-up FAULT C4 C3 LED detection period VGATE(PMOS) t Figure 31. Input disconnect switch power-up: (1) VOUT charges via 10 kΩ resistor, (2) IIN current spike from charging COUT when the PMOS is ¯¯A¯U¯¯L¯¯T ¯ (ch3, enabled; shows VOUT (ch1, 20 V/div.), IIN (ch2, 2 A/div.), ¯F 5 V/div.), and PMOS device VGATE (ch4, 5 V/div.), t = 2 ms/div. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Table 1. Fault Modes Fault Name Type Active Fault Flag Set Primary switch current protection (pulse-bypulse current limit) Auto-restart Always No Secondary switch current limit Latched Always LEDx pin short to GND protection Auto-restart Startup LEDx pin open LED short protection FSET pin short protection Auto-restart Auto-restart Auto-restart Normal operation Always Always Boost Sink driver This fault condition is triggered by the pulse-by-pulse current limit when the SENSP pin voltage exceeds VSENSEP . Off for a single cycle On Yes When the current through the boost switch exceeds the secondary current limit (VSENSESEC) the IC immediately shuts down the LED drivers and the boost. To re-enable the A8509 the EN pin must be toggled. Off Off Yes This fault prevents the IC from starting-up if any of the LEDx pins are shorted. The IC stops soft start from starting while any of the LEDx pins are determined to be shorted. After the short is removed, soft start is allowed to start. Off Off No When an LEDx pin is open the device will determine which LEDx pin is open by increasing the output voltage until OVP is reached. Any LED string below regulation will be turned off. The device then goes back to normal operation by reducing the output voltage to the appropriate voltage level. On Off for open pins. On for all others No This fault occurs when the LED pin voltage exceeds VLEDSC . When the LED short protection is detected, the LED string that is above the threshold will be removed from operation. On Off for shorted pins. On for all others No This fault occurs when the FSET pin current goes above 150% of the maximum current. The boost stops switching, and the IC disables the LED sinks until the fault is removed. When the fault is removed the IC tries to restart with soft start. Off On in soft start current Off Off Stop during OVP event On Description ISET pin short protection Auto-restart Always No This fault occurs when the ISET pin current goes above 150% of the maximum current. The boost stops switching and the IC disables the LED sinks until the fault is removed. When the fault is removed the IC tries to regulate to the preset LED current. Overvoltage protection Auto-restart Always No The fault occurs when the OVP pin voltage exceeds the VOVP(th) threshold. The A8509 immediately stops switching to try to reduce the output voltage. If the output voltage decreases then the A8509 restarts switching to regulate the output voltage. Output undervoltage protection Auto-restart Always Yes This fault occurs when the OVP pin senses less than 100 mV on the pin. The IC disables the external P-FET switch, if one is used. Off Off Overtemperature protection Auto-restart Always Yes The fault occurs when the die temperature exceeds the overtemperature threshold, typically 165°C. Off Off VIN UVLO Auto-restart Always No This fault occurs when VIN drops below VUVLO(th)(max), 8.5 V. This fault resets all latched faults. Off Off Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Application Information Paralleling more than one A8509 The A8509 can be paralleled together by using a single boost converter (master) to provide output power for up to a total of four A8509s (slaves). The MODE pin of each device must be tied to the VDD pin of the same device for proper mode selection. ¯¯T ¯ pins and the COMP pins become a biIn this mode, the ¯F¯A¯¯U¯¯L direction signal bus for the system to communicate. At initial power-up, each IC will release a pull-down resistor on the COMP pin and start in soft start mode. When 200 mV is detected on the COMP pin, the master will then switch to normal ¯¯T ¯ pins must be mode. Also, for proper operation all of the ¯F¯A¯¯U¯¯L tied together to prevent the parallel ICs from powering-up into ¯¯T ¯ pins are pulled a shorted LEDx pin situation. While the ¯F¯A¯¯U¯¯L low, the system will not proceed with start-up. Below is a simple list of necessary connections for the master, to ensure proper parallel operation (refer to Application C in the Typical Applications section): • COMP pin • VOUT node ¯¯T ¯ pin • ¯F¯A¯¯U¯¯L • EN pin • PWM pin Each one of these must be connected to the corresponding signal on the slave devices. OVP setting for parallel operation A notable exception to the list is the OVP pin. In this system each OVP pin must be set with a dedicated resistor. To make sure that the system will operate properly, the overvoltage protection on the master IC should be set higher than on the slave IC. The A8509 checks open LED condition upon hitting the OVP voltage. If the master OVP voltage is set lower than the slave OVP, the slave OVP pin will not trip to permit the open LED check. This in turn will not remove the corresponding LEDx pins from regulation. Therfore, the output voltage will stay at the master OVP limit and never decrease the output voltage to the lower regulation level. The required slave OVP resistor value can be calculated using the following formula: VOUT(OVP) – 1.25 V (7) ROVP(slave) = IOVPH(min) where VOUT(OVP) is the required OVP voltage level, and IOVPH(min) is the current into the OVP pin found in the Electrical Characteristics table. The minimum value should be used in this calculation. The required master OVP voltage level can be calculated using the following formula: VOVP(master) = ROVP(slave) × IOVPH(max) + 1.25 V (8) where VOVP(master) is the minimum minimum OVP voltage level of the master IC, IOVPH(max) is current into the OVP pin found in the Electrical Characteristics table. The maximum value should be used in this calculation. The required master OVP resistor value can be calculated using the following formula: VOVP(master) – 1.25 V (9) ROVP(master) = IOVPH(min) where VOVP(master) is the minimum required master OVP voltage level, and IOVPH(min) is the current into the OVP pin found in the Electrical Characteristics table. The minimum value should be used in this calculation. Following the above formulas will guarantee that there is no overlap in OVP voltage levels in the system. All slave A8509s in the system can have the same OVP voltage setting. Figure 32 shows a proper master-slave OVP setting, and figure 33 shows the result of setting the master OVP too low. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 OVP limit is reached, and string is removed from control loop VOUT (30 V) VLEDx VOUT Control loop reduces VOUT to new regulation level LED string opens C2 System VOUT clamped to OVP setting of master IC VLEDx C2 C1 IOUT OVP of slave is never exceeded, so VOUT remains higher than necessary LED string opens IOUT C3 C3 t Figure 32. Proper OVP setting for the master and slave configuration. The master OVP is set higher than the slave, shows VOUT (ch1, 2 V/div.), pin voltage VLEDx (ch2, 2 V/div.), and IOUT (ch3, 200 mA/div.), t = 2 ms/div. t Figure 33. OVP on the master IC is set too low and the IC does not respond properly to the open LED condition on the slave IC; shows VOUT (ch1, 10 V/div.), VLEDx (ch2, 5 V/div.), and IOUT (ch3, 200 mA/div.), t = 100 ms/div. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 20 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Design Example This section provides a method for selecting component values when designing an application using the A8509. Assumptions: For the purposes of this example, the following are given as the application requirements: Electrical Characteristics table. Choose a value of resistor that is the closest value higher than the calculated ROVP . In this design example, a value of 750 kΩ is selected. Below is the actual value of the minimum OVP trip level with the selected resistor, applying equation 8: VOVP(master) = ROVP × IOVPH + 1.25 V • VIN: 10 to 16 V • Quantity of LED channels, #CHANNELS: 4 • Quantity of series LEDs per channel, #SERIESLEDS : 10 • LED current per channel, ILED : 240 mA • Vf(240) at 240 mA: 3.2 V (max) • fSW : 600 kHz • TA(max): 65°C • PWM dimming frequency: 200 Hz, 1% duty cycle = 750 kΩ × 49 μA + 1.25 V = 38.75 V STEP 4: Determine the inductor. The inductor must be chosen such that it can handle the necessary input current. In most applications, due to stringent EMI requirements, the inductor must operate in continuous conduction mode throughout the whole input voltage range. Step 1: Connect LEDs to pins LED1 through LED4. STEP4a: Determine the maximum duty cycle of the system: Step 2: Determine the LED current by setting resistor RISET . To do so, apply equation 2: VIN(min) × η (12) VOUT(OVP) + Vf(boost) 10 V × 0.9 =1– 34.65 V+ 0.4 V = 74.5% A good approximation of efficiency (η) is 90%. The voltage drop of the boost diode can be approximated to be about 0.4 V. RISET = (1.000 / ILED ) × 2320 = (1.000 V / 0.240 A ) × 2320 = 9.67 kΩ Choose an 9.53 kΩ resistor. STEP 3: Determine the OVP resistor. The OVP resistor is connected between the OVP pin and the output voltage of the converter. The first step is to determine the maximum voltage based on the LED requirements. Then the regulation voltage of 650 mV should be added, along with 2 V for noise and regulation. Given the regulation voltage (VLED) of the A8509 is 650 mV, the minimum required voltage can be determined as follows: VOUT(OVP) = #SERIESLEDS ×Vf(240) + VLED + 2 V (10) = 10 × 3.2 V + 0.650 V + 2 V VOUT(OVP)(min) = 34.65 V The OVP resistor (ROVP) value can be calculated as: ROVP = VOUT(OVP)(min) – VOVP(th)(min) IOVPH(min) 34.65 V – 1.11 V 45 μA = 745 kΩ = where both IOVP(th)(min) and VOVP(th)(min) are found in the (11) D(max) =1– STEP 4b: Determine the maximum and minimum input current to the system. The minimum input current dictates the inductor value. The maximum current rating dictates the current rating of the inductor. To calculate the maximum input current, first determine the required output current: IOUT = #CHANNELS × ILED (13) = 4 × 240 mA = 0.960 A Then substitute into the formula for maximum input current: IIN(max) = VOUT × IOUT VIN(min) × η (14) 34.65 V × 0.960 A 10 V × 0.90 = 3.7 A = Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 21 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 The minimum input current can be calculated as: V ×I IIN(min) = OUT OUT VIN(max) × η (15) 34.65 V × 0.960 A 16 V × 0.90 = 2.31 A STEP 4c: Determining the inductor value. To assure that the inductor operates in continuous conduction mode, the value of inductor must be set such that 1/2 of the inductor ripple current is not greater than the average minimum input current. = As a first pass, take Iripple to be 30% of the maximum inductor current: ∆IL = IIN(max) × (Iripple / IIN(max)) = 3.72 A × 0.30 = 1.1 A (16) IIN(min) > 1 × ∆IL 2 2.31 A > 0.56 A (17) 10 V × 0.745 1.1 A × 600 kHz = 10.62 μH = A good inductor value to use would be Lused = 10 μH. STEP 4d: Determining the inductor current rating. The inductor current rating must be greater than the IIN(max) value plus the ripple current ΔIL , calculated as: 1 ∆I × Lused 2 = 3.72 A + 0.56 A = 4.28 A IL(min) = IIN(max) + STEP 4e: Choosing the RSENSE resistor. The sense resistor value can be calculated as follows: = 0.086 V 4.28 A (19) = 0.02 Ω 0.018 Ω is a good value to use for the resistor. STEP 4f: This step is used to verify that there is sufficient slope compensation for the inductor chosen. The internal slope compensation value is determined by the following formula: Slope Compensation = 2.81×10–7 × fSW where fSW is in Hz. Substituting: = 0.168 V / μs With RSENSE = 0.02 Ω this translates to: (20) Next invert equation 17 and insert the inductor value used in the design: VIN(min) × D(max) Lused × fSW where fSW is in MHz. Substituting: 10 V × 0.745 = 10 μH × 600 kHz = 1.24 A ∆ ILused× 1 × 10 –6 Inductor Current Slope = 1 × (1 – D(max)) fSW 1.24 A × 1 × 10 –6 = 1 × (1 – 0.745) 600 kHz = 2.91 A / μs ∆ ILused = The inductor value can be calculated as: VIN(min) × D(max) ∆ IL × fSW VSENSEP IL(min) 0.168 / 0.02 = 8.4 A/μs Check to make sure that 1/2 of the inductor ripple current is less than IIN(min): L= RSENSE = (18) (21) (22) Note: that the 1×10 –6 is a constant multiplier. This slope should be smaller than the internal slope compensation. STEP 5: To determine the resistor values for a switching frequency use figure 9. STEP 6: Choosing the proper switching diode. The switching diode must be chosen for three characteristics when it is used in LED lighting circuitry: reverse voltage rating, current rating, and reverse current characteristic of the diode. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 22 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 The reverse voltage rating should be such that, during any operation condition, the voltage rating of the device is larger than the maximum output voltage. In this case, the maximum output voltage is VOUT(OVP) . The peak current through the diode is: Id(peak) = IIN(max) + ∆ILused The other major component in determining the switching diode is the reverse current characteristic of the diode. This characteristic is especially important when PWM dimming is implemented. During PWM off-time the boost converter is not switching. This results in a slow bleeding-off of the output voltage due to leakage currents (IR). IR , or reverse current, can be a huge contributor especially at high temperatures. On the diode that was selected in this design, the current varies between 1 and 100 μA. STEP 7: Choosing the output capacitors. The output capacitors must be chosen such that they can provide filtering for both the boost converter and for the PWM dimming function. The biggest factor that contributes to the size of the output capacitor is PWM dimming frequency and the PWM duty cycle. Another major contributor is leakage current (ILK ). This current is the combination of the OVP current sense as well as the reverse current of the switching diode. In this design the PWM dimming frequency is 200 Hz and the minimum duty cycle is 1%. Typically the voltage variation on the output during PWM dimming must be less than 250 mV (VCOUT) so that no audible hum can be heard: 1 – DPWM(min) (24) COUT = ILK× fPWM × VCOUT 1 – 0.01 = 300 μA × 200 Hz × 0.250 V = 5.94 μF A capacitor larger than 5.94 μF should be selected due to degradation of capacitance at high voltages on the capacitor. Two ceramic 4.7 μF 50 V capacitors are a good choice to fulfill this requirement. The rms current through the capacitor is given by: ICOUTrms = IOUT = 0.960 A (23) = 3.72 A + 0.56 A = 4.28 A ∆ILused IIN(max) 12 1 – D(max) D(max) + (25) 1.24 A 12 3.72 A 1 – 0.745 0.745 + = 1.67 A The output capacitor must have a current rating of at least 1.67 A. The output capacitors selected in this design have a combined rms current rating of 2 A. STEP 8: Selection of input capacitor. The input capacitor must be selected such that it provides a good filtering of the input voltage waveform. A good rule of thumb is to set the input voltage ripple (ΔVIN) to be 1% of the minimum input voltage. The minimum input capacitor requirements are as follows: CIN = ∆ILused fSW 8 ∆VIN 1.24 A = 8 600 kHz 0.1 V = 2.65 μF The rms current through the capacitor is given by: IINrms = IOUT × ∆ILused IIN(max) (26) (27) (1 – D(max)) 12 0.960 A × 1.24 A 3.72 A = (1 – 0.765) 12 = 0.363 A A good ceramic input capacitor with ratings of 50 V, 4.7 μF will suffice for this application. Corresponding capacitors include: Vendor Value Part number Murata 4.7 μF 50 V GRM32ER71H475KA88L Murata 2.2 μF 50 V GRM31CR71H225KA88L Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 23 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Typical Applications The following is the component list for the typical application circuit shown in figure 1. Designator Description CDD 0.1 μF / 10 V CDR 1 μF / 16 V CIN 4.7 μF / 50 V COUT 10 μF / 50 V CP 1 μF / 16V CZ DNP D1 60 V / 5 A Schottky L1 Q1 Part Number GRM2195C1H104JA01D DRM188R61A105K GRM32ER71H475KA88L GRM32ER71H475KA88L Manufacturer Murata Murata Murata Murata GRM188R61A474K Murata CMSH5-60-AMI Central Semi 10 μH / 5 A 74477110 Wurth Electronics NMOS FQD13N06LTM Faichild R1 100 kΩ RFSET 8.45 kΩ 1% RISET 12.4 kΩ 1% ROVP 732 kΩ 1% RSENSE 0.015 Ω RZ DNP U1 A8509 DigiKey A8509 Allegro Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 24 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Typical Applications 10 kΩ CIN VIN Q2 VDR 1 kΩ L1 D1 (Optional) Q1 COUT Q3 1 kΩ VOUT ROVP RSENSE R1 VIN FAULT GATE SENP SENN LED1 PWM CDR CDD EN VDR VDD FSET/SYNC ISET COMP RFSET RISET OVP LED2 A8509 LED3 LED4 PAD CP MODE AGND PGND Application A. Typical schematic for boost application with disconnect switch application R2 10 kΩ L1 VIN L2 CF CIN VC D1 COUT VIN FAULT GATE SENP SENN CDD OVP LED1 PWM EN VDR VDD FSET/SYNC ISET COMP RFSET ROVP RSENSE R1 CDR VOUT A8509 LED2 LED3 LED4 PAD RISET CP MODE AGND PGND Application B. Typical application showing SEPIC configuration Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 25 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 L1 VIN CIN D1 Q1 COUT VC R1 GATE SENP CDD SENN OVP LED1 A8509 (master) EN VDR VDD MODE FSET/SYNC ISET COMP RFSET ROVP RSENSE VIN FAULT PWM CDR VOUT LED2 LED3 LED4 PAD RISET AGND PGND CP1 VIN VOUT ROVP RGATE 50 kΩ VIN FAULT GATE PWM EN VDR VDD MODE FSET/SYNC ISET COMP CDR RFSET CDD RISET SENP SENN OVP LED1 A8509 (one slave) LED2 LED3 LED4 PAD AGND PGND CP2 Application C. Parallel operation of two A8509s; overvoltage protection on master must be set higher than the OVP on the slave Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 26 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver A8509 Package LP, 24-Pin TSSOP with Exposed Thermal Pad 7.80±0.10 24 0.65 0.45 8º 0º 0.20 0.09 B 3 NOM 4.40±0.10 3.00 6.40±0.20 6.10 0.60 ±0.15 A 1 2 1.00 REF 4.32 NOM 0.25 BSC 24X SEATING PLANE 0.10 C 0.30 0.19 0.65 BSC SEATING PLANE GAUGE PLANE C 1.65 4.32 C PCB Layout Reference View For Reference Only; not for tooling use (reference MO-153 ADT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 1.20 MAX 0.15 0.00 A Terminal #1 mark area B Exposed thermal pad (bottom surface); dimensions may vary with device C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Contact factory for LB package. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 27 A8509 Wide Input Voltage Range, High Efficiency 4-Channel Fault Tolerant LED Driver Copyright ©2011, Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 28