AS3932 3 D L o w F r e q u e n c y Wa k e u p R e c e i v e r 1 General Description The AS3932 is a 3-channel low power ASK receiver that is able to generate a wake-up upon detection of a data signal which uses a LF carrier frequency between 110 - 150 kHz. The integrated correlator can be used for detection of a programmable 16-bit wake-up pattern. The device can operate using one, two, or three active channels. The AS3932 provides a digital RSSI value for each active channel, it supports a programmable data rate. The AS3932 offers a real-time clock (RTC), which is either derived from a crystal oscillator or the internal RC oscillator. The programmable features of AS3932 enable to optimize its settings for achieving a longer distance while retaining a reliable wake-up generation. The sensitivity level of AS3932 can be adjusted in presence of a strong field or in noisy environments. The device is available in 16-pin TSSOP and 16LD QFN (4x4) packages. 2 Key Features 3-channel ASK wake-up receiver Carrier frequency range 110 - 150 kHz One, two, or three channel operation Reliable 1-D, 2-D or 3-D wake-up pattern detection Programmable wake-up pattern (16bits) Doubling of wake-up pattern supported Wake-up sensitivity 100 µVRMS (typ.) Adjustable sensitivity level Highly resistant to false wake-ups False wake-up counter Periodical forced wake-up supported (1s – 2h) Low power listening modes Current consumption in 3-channel listening mode 1.7 µA (typ.) Programmable data-rate 0.5 – 4 kbaud (Manchester encoded) Digital RSSI values available for each channel Dynamic range 64dB 5 bit RSSI step (2dB per step) RTC based on 32kHz XTAL, RC-OSC, or External Clock Operating temperature range -40ºC to +85ºC Operating supply voltage 2.4V – 3.6V (TA = 25ºC) Bidirectional serial digital interface (SDI) Package option: 16-pin TSSOP, 16LD QFN (4x4) 3 Applications The AS3932 is ideal for Active RFID tags, Real-time location systems, Operator identification, Access control, and Wireless sensors. Wake-up without pattern detection supported www.ams.com/LF-Receiver/AS3932 Revision 1.7 1 - 34 AS3932 Datasheet - A p p l i c a t i o n s Figure 1. AS3932 Typical Application Diagram with Crystal Oscillator VCC CL CBAT XIN NC XOUT LF1P X, Y, and Z Receiving Antennas TX CS XTAL Transmitting Antenna TRANSMITTER VCC DAT AS3932 WAKE LF2P SCL LF3P SDO LFN SDI VSS GND VCC CS XIN NC Figure 2. AS3932 Typical Application Diagram with RC Oscillator VCC CBAT www.ams.com/LF-Receiver/AS3932 LF1P X, Y, and Z Receiving Antennas TX Transmitting Antenna XOUT TRANSMITTER Revision 1.7 DAT AS3932 WAKE LF2P SCL LF3P SDO LFN SDI VSS GND 2 - 34 AS3932 Datasheet - A p p l i c a t i o n s Figure 3. AS3932 Typical Application Diagram with Clock from External Source VCC CBAT EXTERNAL CLOCK VCC CS XIN NC R C www.ams.com/LF-Receiver/AS3932 LF1P X, Y, and Z Receiving Antennas TX Transmitting Antenna XOUT TRANSMITTER Revision 1.7 DAT AS3932 WAKE LF2P SCL LF3P SDO LFN SDI VSS GND 3 - 34 AS3932 Datasheet - C o n t e n t s Contents 1 General Description .................................................................................................................................................................. 1 2 Key Features............................................................................................................................................................................. 1 3 Applications............................................................................................................................................................................... 1 4 Pin Assignments ....................................................................................................................................................................... 5 4.1 TSSOP Package .................................................................................................................................................................................. 5 4.1.1 Pin Descriptions........................................................................................................................................................................... 5 4.2 QFN Package ....................................................................................................................................................................................... 6 4.2.1 Pin Descriptions........................................................................................................................................................................... 6 5 Absolute Maximum Ratings ...................................................................................................................................................... 7 6 Electrical Characteristics........................................................................................................................................................... 8 7 Typical Operating Characteristics ........................................................................................................................................... 10 8 Detailed Description................................................................................................................................................................ 11 8.1 Operating Modes ................................................................................................................................................................................ 8.1.1 8.1.2 8.1.3 8.1.4 Power Down Mode .................................................................................................................................................................... Listening Mode .......................................................................................................................................................................... Preamble Detection / Pattern Correlation .................................................................................................................................. Data Receiving .......................................................................................................................................................................... 8.2 System and Block Specification ......................................................................................................................................................... 8.2.1 8.2.2 8.2.3 8.2.4 Register Table ........................................................................................................................................................................... Register Table Description and Default Values ......................................................................................................................... Serial Data Interface (SDI)......................................................................................................................................................... SDI Timing ................................................................................................................................................................................. 8.3 Channel Amplifier and Frequency Detector........................................................................................................................................ 12 12 12 13 13 14 14 14 16 19 20 8.3.1 Frequency Detector / AGC ........................................................................................................................................................ 20 8.3.2 Antenna Damper........................................................................................................................................................................ 21 8.4 Channel Selector / Demodulator / Data Slicer.................................................................................................................................... 21 8.5 Correlator............................................................................................................................................................................................ 22 8.6 Wake-up Protocol - Carrier Frequency 125 kHz................................................................................................................................. 23 8.6.1 Without Pattern Detection.......................................................................................................................................................... 23 8.6.2 Single Pattern Detection ............................................................................................................................................................ 24 8.7 False Wake-up Register ..................................................................................................................................................................... 26 8.8 Real Time Clock (RTC)....................................................................................................................................................................... 27 8.8.1 Crystal Oscillator........................................................................................................................................................................ 28 8.8.2 RC-Oscillator ............................................................................................................................................................................. 28 8.8.3 External Clock Source ............................................................................................................................................................... 29 8.9 Channel Selection in Scanning Mode and ON/OFF Mode ................................................................................................................. 29 9 Package Drawings and Markings ........................................................................................................................................... 30 10 Ordering Information............................................................................................................................................................. 33 www.ams.com/LF-Receiver/AS3932 Revision 1.7 4 - 34 AS3932 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments 4.1 TSSOP Package Figure 4. Pin Assignments 16-pin TSSOP Package 4.1.1 CS 1 16 NC SCL 2 15 DAT SDI 3 14 WAKE SDO 4 13 VSS VCC 5 12 XOUT GND 6 11 XIN LF3P 7 10 LFN LF2P 8 9 LF1P AS3932 Pin Descriptions Table 1. Pin Descriptions 16-pin TSSOP Package Pin Name Pin Number CS 1 SCL 2 SDI 3 SDO 4 Digital output / tristate SDI data output (tristate when CS is low) VCC 5 Supply pad Positive supply voltage GND 6 Supply pad Negative supply voltage LF3P 7 Input antenna channel three LF2P 8 Input antenna channel two LF1P 9 LFN 10 XIN 11 Crystal oscillator input XOUT 12 Crystal oscillator output VSS 13 WAKE 14 DAT 15 NC 16 www.ams.com/LF-Receiver/AS3932 Pin Type Description Chip select Digital input SDI interface clock SDI data input Input antenna channel one Analog I/O Common ground for antenna one, two and three Supply pad Substrate Wake-up output IRQ Digital output Data output - Not connected Revision 1.7 5 - 34 AS3932 Datasheet - P i n A s s i g n m e n t s 4.2 QFN Package LF3P 1 LF2P 2 GND VCC SDO SDI Figure 5. Pin Assignments 16LD QFN (4x4) Package 16 15 14 13 AS3932 4.2.1 12 SCL 11 CS LFN 4 9 DAT 5 6 7 8 WAKE NC VSS 10 XOUT 3 XIN LF1P Pin Descriptions Table 2. Pin Descriptions 16LD QFN (4x4) Package Pin Name Pin Number LF3P 1 Input antenna channel three LF2P 2 Input antenna channel two LF1P 3 LFN 4 XIN 5 Crystal oscillator input XOUT 6 Crystal oscillator output VSS 7 WAKE 8 DAT 9 NC 10 CS 11 SCL 12 SDI 13 SDO 14 Digital output / tristate SDI data output (tristate when CS is low) VCC 15 Supply pad Positive supply voltage GND 16 Supply pad Negative supply voltage Pin Type Description Input antenna channel one Analog I/O Common ground for antenna one, two and three Supply pad Substrate Wake-up output IRQ Digital output Data output - Not connected Chip select Digital input SDI interface clock SDI data input Note: The exposed pad has to be connected to ground. www.ams.com/LF-Receiver/AS3932 Revision 1.7 6 - 34 AS3932 Datasheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 8 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Absolute Maximum Ratings Parameter Min Max Units Notes DC supply voltage (VDD) -0.5 5 V Input pin voltage (VIN) -0.5 5 V Input current (latch up immunity) (ISOURCE) -100 100 mA Norm: Jedec 78 kV Norm: MIL 883 E method 3015 (HBM) Electrical Parameters Electrostatic Discharge Electrostatic discharge (ESD) ±2 Continuous Power Dissipation Total power dissipation (all supplies and outputs) (Pt) 0.07 mW 150 ºC Temperature Ranges and Storage Conditions Storage temperature (Tstrg) -65 Package body temperature (Tbody) Humidity non-condensing Moisture Sensitivity Level (MSL) www.ams.com/LF-Receiver/AS3932 5 260 ºC 85 % 3 Norm: IPC/JEDEC J-STD-020 The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices”. Represents a maximum floor life time of 168h Revision 1.7 7 - 34 AS3932 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics Table 4. Electrical Characteristics Symbol Parameter Conditions Min Typ Max Units Operating Conditions VDD Positive supply voltage 2.4 3.6 V VSS Negative supply voltage 0 0 V TAMB Ambient temperature -40 85 ºC DC/AC Characteristics for Digital Inputs and Outputs CMOS Input VIH High level input voltage 0.58* VDD 0.7* VDD 0.83* VDD V VIL Low level input voltage 0.125* VDD 0.2* VDD 0.3* VDD V ILEAK Input leakage current 100 nA CMOS Output VOH High level output voltage With a load current of 1mA VOL Low level output voltage With a load current of 1mA VSS + 0.4 V CL Capacitive load For a clock frequency of 1 MHz 400 pF VOH High level output voltage With a load current of 1mA VOL Low level output voltage With a load current of 1mA VSS + 0.4 V IOZ Tristate leakage current to VDD and VSS 100 nA Max Units VDD - 0.4 V Tristate CMOS Output VDD - 0.4 V Table 5. Electrical System Specifications Symbol Parameter Conditions RIN Input Impedance In case no antenna damper is set (R1<4>=0) Fmin Fmax Min Typ Input Characteristics 2 MΩ Minimum Input Frequency 110 kHz Maximum Input Frequency 150 kHz Current Consumption IPWD Power Down Mode 400 nA I1CHRC Current Consumption in standard listening mode with one active channel and RCoscillator as RTC 2.7 µA I2CHRC Current Consumption in standard listening mode with two active channels and RCoscillator as RTC 4.2 µA I3CHRC Current Consumption in standard listening mode with three active channels and RCoscillator as RTC 5.7 I3CHSCRC Current Consumption in scanning mode with three active channels and RCoscillator as RTC 2.7 www.ams.com/LF-Receiver/AS3932 Revision 1.7 8.3 µA µA 8 - 34 AS3932 Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 5. Electrical System Specifications Symbol Parameter Conditions Min Typ Current Consumption in ON/ OFF mode with three active channels and RC-oscillator as RTC 11% Duty Cycle 1.7 I3CHOORC 50% Duty Cycle 3.45 I3CHXT Current Consumption in standard listening mode with three active channels and crystal oscillator as RTC IDATA Current Consumption in Preamble detection / Pattern correlation / Data receiving mode (RC-oscillator) Input Sensitivity on all channels Max Units µA 6.5 8.9 µA With 125 kHz carrier frequency and 1kbps data-rate. No load on the output pins. 8.3 12 µA With 125 kHz carrier frequency, chip in default mode, 4 half bits burst + 4 symbols preamble and single preamble detection 100 µVrms 250 µs 32.768 kHz Input Sensitivity SENS Channel Settling Time TSAMP Amplifier settling time Crystal Oscillator FXTAL Frequency Crystal dependent TXTAL Start-up Time Crystal dependent IXTAL Current consumption 1 s 1 µA 1 µA External Clock Source IEXTCL Current consumption RC Oscillator FRCNCAL Frequency If no calibration is performed 27 32.768 42 kHz FRCCAL32 Frequency If calibration with 32.768 kHz reference signal is performed 31 32.768 34.5 kHz FRCCALMAX Frequency Maximum achievable frequency after calibration 35 kHz FRCCALMIN Frequency Minimum achievable frequency after calibration 30 kHz TCALRC Calibration time IRC Current consumption www.ams.com/LF-Receiver/AS3932 65 200 Revision 1.7 Periods of reference clock nA 9 - 34 AS3932 Datasheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics Figure 6. Sensitivity over Voltage and Temperature Figure 7. Sensitivity over RSSI 1000000 120 VIN = 2.4V 95 oC 100000 100 27 oC VIN = 1.5V Input Voltage [µVrms] -40 oC Sensitivity [µVrms] 80 60 40 10000 VIN = 1.0V 1000 100 10 20 1 0 2.4 3 2 3.6 4 6 8 10 12 14 16 18 20 22 24 26 28 30 RSSI [dB] Supply Voltage [V] Figure 8. RC-Osc Frequency over Voltage (calibr.) Figure 9. RC-Osc Frequency over Temperature (calibr.) 34.5 34.5 34 33.5 RC-OSC Frequency [KHz] RC-OSC Frequency [KHz] 34 33 32.5 33.5 33 32.5 32 32 31.5 31.5 31 31 2.4 2.6 2.8 3 3.2 3.4 -36 -30 -20 -10 3.6 www.ams.com/LF-Receiver/AS3932 0 10 20 30 40 50 60 70 80 90 Operating Temperature [oC] Supply Voltage [V] Revision 1.7 10 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n 8 Detailed Description The AS3932 is a three-dimensional low power low-frequency wake-up receiver. The AS3932 is capable to detect the presence of an inductive coupled carrier and extract the envelope of the On-Off-Keying (OOK) modulated carrier. In case the carrier is Manchester coded the clock is recovered from the transmitted signal and the data can be correlated with a programmed pattern. If the detected pattern corresponds to the stored one a wake-up signal (IRQ) is risen up. The pattern correlation can be bypassed in which case the wake-up detection is based only on the frequency detection. The AS3932 is made up by three independent receiving channels, one envelop detector, one data correlator, 8 programmable registers with the main logic and a real time clock. The digital logic can be accessed by an SPI. The real time clock can be based on a crystal oscillator or on an internal RC one. If the internal RC oscillator is used, a calibration procedure can be performed to improve its accuracy. Figure 10. Block Diagram of LF Wake-up Receiver AS3932 AS3932 Wake-up IRQ Data LF1P Channel Amplifier 1 SCL RSSI Main Logic SPI SDI SDO Freq. OK LF2P Channel Amplifier 2 Envelope Detector / Data Slicer Channel Selector Data CS Correlator RSSI Freq. OK DAT Data LF3P Channel Amplifier 3 RSSI Freq. OK I/V Bias Xtal RTC GND Xin RC RTC LFN VCC www.ams.com/LF-Receiver/AS3932 Revision 1.7 Xout 11 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n AS3932 needs the following external components: Power supply capacitor - CBAT – 100 nF 32.768 kHz crystal with its two pulling capacitors – XTAL and CL – (it is possible to omit these components if the internal RC oscillator is used instead of the crystal oscillator). One, two, or three LC resonators according to the number of used channels. In case the internal RC-oscillator is used (no crystal oscillator is mounted), the pin XIN has to be connected to the supply, while pin XOUT should stay floating. Application diagrams with and without crystal are shown in Figure 1 and Figure 2 8.1 Operating Modes 8.1.1 Power Down Mode In Power Down Mode AS3932 is completely switched off. The typical current consumption is 400 nA. 8.1.2 Listening Mode In listening mode only the active channel amplifiers and the RTC are running. In this mode the system detects the presence of a carrier. In case the carrier is detected the RSSI can be displayed. If the three dimensional detection is not required it is possible to deactivate one or more channels. In case only two channels are required the deactivated channel must be the number two, while if only one channel detection is needed the active channel must be the number one. Inside this mode it is possible to distinguish the following three sub modes: Standard Listening mode. All channels are active at the same time Scanning mode (Low Power mode 1). All used channels are active, but only one per time slot, where the time slot T is defined as 1ms. Thus, if all three channels are active the procedure is as follows (see Figure 11): for the first millisecond only channel one is active while channel two and three are powered down; for the next millisecond only channel three is active while channel one and two are powered down; finally, channel two is active while the other two are deactivated. This channel rotation goes on until the presence of the carrier is detected by any of the channels; then immediately all three channels will become active at the same time. Now AS3932 can perform a simultaneous multidirectional evaluation (on all three channels) of the field and evaluate which channel has the strongest RSSI. The channel with the highest RSSI will be put through to the demodulator. In this way it is possible to perform multidirectional monitoring of the field with a current consumption of a single channel, keeping the sensitivity as good as if all channels are active at the same time. Figure 11. Scanning Mode Channel 1 Channel 3 time Channel 2 time Presence of carrier time t0 www.ams.com/LF-Receiver/AS3932 t0+T t0+2T t0+3 T t0+4T Revision 1.7 t0+5T t1 time 12 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n ON/OFF mode (Low Power mode 2). All active channels are on at the same time but not for the whole time (time slot T is defined as 1ms). An on-off duty-ratio is defined. This duty ratio is programmable see R4<7:6>. Figure 12. ON/OFF Mode Channel 1 Channel 2 time Channel 3 time Presence of carrier time t0 t0+T 2 *t 0 2 *t 0 + T 3 *t 0 time For each of these sub modes it is possible to enable a further feature called Artificial Wake-up. The Artificial Wake-up is a counter based on the used RTC. Three bits define a time window see R8<2:0>. If no activity is seen within this time window the chip will produce an interrupt on the WAKE pin that lasts 128 µs. With this interrupt the microcontroller (µC) can get feedback on the surrounding environment (e.g. read the false wake-up register R13<7:0>) and/or take actions in order to change the setup. 8.1.3 Preamble Detection / Pattern Correlation The preamble detection and pattern correlation are only considered for the wake-up when the data correlator function is enabled (see R1<1>). The correlator searches first for preamble frequency (constant frequency of Manchester clock defined according to bit-rate transmission, see Table 19) and then for data pattern. If the pattern is matched the wake-up interrupt is displayed on the WAKE output and the chip goes in Data receiving mode. If the pattern fails the internal wake-up (on all active channels) is terminated and no IRQ is produced. 8.1.4 Data Receiving After a successful wake-up the chip enters the data receiving mode. In this mode the chip can be retained a normal OOK receiver. The received data are streamed out on the pin DAT. It is possible to put the chip back to listening mode either with a direct command (CLEAR_WAKE (see Table 12)) or by using the timeout feature. This feature automatically sets the chip back to listening mode after a certain time R7<7:5>. www.ams.com/LF-Receiver/AS3932 Revision 1.7 13 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n 8.2 System and Block Specification 8.2.1 Register Table Table 6. Register Table 7 6 R0 n.a. R1 ABS_HY R2 S_ABSH R3 HY_20m R4 AGC_TLIM 5 4 3 2 1 0 ON_OFF MUX_123 EN_A2 EN_A3 EN_A1 PWD AGC_UD ATT_ON EN_PAT2 EN_WPAT EN_RTC W_PAT_T<1:0> Reserved HY_POS FS_SLC<2:0> T_OFF<1:0> FS_ENV<2:0> R_VAL<1:0> GR<3:0> R5 TS2<7:0> R6 TS1<7:0> R7 S_WU1<1:0> T_OUT<2:0> T_HBIT<4:0> R8 n.a. R9 T_AUTO<2:0> n.a. Reserved R10 n.a. RSSI1<4:0> R11 n.a. RSSI3<4:0> R12 n.a. RSSI2<4:0> R13 8.2.2 F_WAKE Register Table Description and Default Values Table 7. Default Values of Registers Register Name Type Default Value R0<5> ON_OFF R/W 0 On/Off operation mode. (Duty-cycle defined in the register R4<7:6> R0<4> MUX_123 R/W 0 Scan mode enable R0<3> EN_A2 R/W 1 Channel 2 enable R0<2> EN_A3 R/W 1 Channel 3 enable R0<1> EN_A1 R/W 1 Channel 1 enable R0<0> PWD R/W 0 Power down R1<7> ABS_HY R/W 0 Data slicer absolute reference R1<6> AGC_TLIM R/W 0 AGC acting only on the first carrier burst R1<5> AGC_UD R/W 1 AGC operating in both direction (up-down) R1<4> ATT_ON R/W 0 Antenna damper enable R1<2> EN_PAT2 R/W 0 Double wake-up pattern correlation R1<1> EN_WPAT R/W 1 Data correlation enable R1<0> EN_RTC R/W 1 Crystal oscillator enable R2<7> S_ABSH R/W 0 Data slicer threshold reduction R2<6:5> W_PAT R/W 00 Pattern correlation tolerance (see Table 20) R2<4:2> Reserved 000 Reserved R2<1:0> S_WU1 00 Tolerance setting for the stage wake-up (see Table 14) www.ams.com/LF-Receiver/AS3932 R/W Description Revision 1.7 14 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n Table 7. Default Values of Registers Register Name Type Default Value R3<7> HY_20m R/W 0 Data slicer hysteresis if HY_20m = 0 then comparator hysteresis = 40mV if HY_20m = 1 then comparator hysteresis = 20mV R3<6> HY_POS R/W 0 Data slicer hysteresis on both edges (HY_POS = 0 → hysteresis on both edges; HY_POS = 1 → hysteresis only on positive edges) R3<5:3> FS_SCL R/W 100 Data slicer time constant (see Table 18) R3<2:0> FS_ENV R/W 000 Envelop detector time constant (see Table 17) Description Off time in ON/OFF operation mode R4<7:6> T_OFF R/W 00 T_OFF=00 1ms T_OFF=01 2ms T_OFF=10 4ms T_OFF=11 8ms R4<5:4> D_RES R/W 01 R4<3:0> GR R/W 0000 R5<7:0> TS2 R/W 01101001 2 Byte of wake-up pattern R6<7:0> TS1 R/W 10010110 1 Byte of wake-up pattern R7<7:5> T_OUT R/W 000 R7<4:0> T_HBIT R/W 01011 Antenna damping resistor (see Table 16) Gain reduction (see Table 15) nd st Automatic time-out (see Table 21) Bit rate definition (see Table 19) Artificial wake-up R8<2:0> T_AUTO R/W 000 T_AUTO=000 No artificial wake-up T_AUTO=001 1 sec T_AUTO=010 5 sec T_AUTO=011 20 sec T_AUTO=100 2 min T_AUTO=101 15min T_AUTO=110 1 hour T_AUTO=111 2 hour R9<6:0> Reserved R10<4:0> RSSI1 R RSSI channel 1 R11<4:0> RSSI2 R RSSI channel 2 R12<4:0> RSSI3 R RSSI channel 3 R13<7:0> F_WAK R False wake-up register www.ams.com/LF-Receiver/AS3932 000000 Reserved Revision 1.7 15 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n 8.2.3 Serial Data Interface (SDI) This 4-wires interface is used by the Microcontroller (µC) to program the AS3932. The maximum clock frequency of the SDI is 2MHz. Table 8. Serial Data Interface (SDI) pins Name Signal Signal Level Description CS Digital Input with pull down CMOS Chip Select SDI Digital Input with pull down CMOS Serial Data input for writing registers, data to transmit and/or writing addresses to select readable register SDO Digital Output CMOS Serial Data output for received data or read value of selected registers SCLK Digital Input with pull down CMOS Clock for serial data read and write Note: SDO is set to tristate if CS is low. In this way more than one device can communicate on the same SDO bus. SDI Command Structure. To program the SDI the CS signal has to go high. A SDI command is made up by a two bytes serial command and the data is sampled on the falling edge of SCLK. The Table 9 shows how the command looks like, from the MSB (B15) to LSB (B0). The command stream has to be sent to the SDI from the MSB (B15) to the LSB (B0). Table 9. SDI Command Structure Mode B15 Register address / Direct Command B14 B13 B12 B11 B10 B9 Register Data B8 B7 B6 B5 B4 B3 B2 B1 B0 The first two bits (B15 and B14) define the operating mode. There are three modes available (write, read, direct command) plus one spare (not used), as shown in Table 10. Table 10. SDI Command Structure B15 B14 Mode 0 0 WRITE 0 1 READ 1 0 NOT ALLOWED 1 1 DIRECT COMMAND In case a write or read command happens the next 6 bits (B13 to B8) define the register address which has to be written respectively read, as shown in Table 11. Table 11. SDI Command Structure B13 B12 B11 B10 B9 B8 Read/Write register 0 0 0 0 0 0 R0 0 0 0 0 0 1 R1 0 0 0 0 1 0 R2 0 0 0 0 1 1 R3 0 0 0 1 0 0 R4 0 0 0 1 0 1 R5 0 0 0 1 1 0 R6 0 0 0 1 1 1 R7 0 0 1 0 0 0 R8 0 0 1 0 0 1 R9 www.ams.com/LF-Receiver/AS3932 Revision 1.7 16 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n Table 11. SDI Command Structure B13 B12 B11 B10 B9 B8 Read/Write register 0 0 1 0 1 0 R10 0 0 1 0 1 1 R11 0 0 1 1 0 0 R12 0 0 1 1 0 1 R13 The last 8 bits are the data that has to be written respectively read. A CS toggle high-low-high terminates the command mode. If a direct command is sent (B15-B14=11) the bits from B13 to B8 defines the direct command while the last 8 bits are omitted. The Table 12 shows all possible direct commands: Table 12. List of Direct Commands COMMAND_MODE B13 B12 B11 B10 B9 B8 clear_wake 0 0 0 0 0 0 reset_RSSI 0 0 0 0 0 1 trim_osc 0 0 0 0 1 0 clear_false 0 0 0 0 1 1 preset_default 0 0 0 1 0 0 All direct commands are explained below: - clear_wake: clears the wake state of the chip. In case the chip has woken up (WAKE pin is high) the chip is set back to listening mode reset_RSSI: resets the RSSI measurement. trim_osc: starts the trimming procedure of the internal RC oscillator (see Figure 21) clear_false: resets the false wake-up register (R13<7:0>=00) preset_default: sets all register in the default mode, as shown in Figure 7 Writing of Data to Addressable Registers (WRITE Mode). The SDI is sampled at the falling edge of SCLK (as shown in the following diagrams). A CS toggling high-low-high indicates the end of the WRITE command after register has been written. The following example shows a write command. Figure 13. Writing of a Single Byte (falling edge sampling) CS SCLK SDI X 0 0 A5 Two leading Zeros indicate WRITE Mode www.ams.com/LF-Receiver/AS3932 A4 A3 SCLK rising edge Data is transfered from µC A2 A1 A0 D7 D6 SCLK falling edge Data is sampled D5 D4 D3 D2 D1 Data is moved to Address A5-A0 Revision 1.7 D0 X CS falling edge signals end of WRITE Mode 17 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 14. Writing of Register Data with Auto-incrementing Address CS SCLK SDI A A A A A D D D D D D D D D D D D D D D D D D X 0 0 A 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 Two leading Zeros indicate WRITE Mode Data is moved to Address <A5-A0 > Data is moved to Address <A5-A0 > + 1 D D D D D D D D D D 1 0 7 6 5 4 3 2 1 0 CS falling edge signals end of WRITE Mode Data is moved to Address <A5-A0 > + n Data is moved to Address <A5-A0 > + (n-1) X Reading of Data from Addressable Registers (READ Mode). Once the address has been sent through SDI, the data can be fed through the SDO pin out to the microcontroller. A CS LOW toggling high-low-high has to be performed after finishing the read mode session, in order to indicate the end of the READ command and prepare the Interface to the next command control Byte. To transfer bytes from consecutive addresses, SDI master has to keep the CS signal high and the SCLK clock has to be active as long as data need to be read. Figure 15. Reading of Single Register Byte CS SCLK SDI X 0 1 A5 SDO A4 A3 A2 A1 X 01 pattern indicates READ Mode www.ams.com/LF-Receiver/AS3932 X A0 D7 SCLK rising edge Data is transfered from µC SCLK falling edge Data is sampled D6 SCLK rising edge Data is moved from Address <A5-A0> Revision 1.7 D5 D4 D3 SCLK falling edge Data is transfered to µC D2 D1 D0 X CS falling edge signals end of READ Mode 18 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 16. Send Direct COMMAND Byte CS SCLK X SDI 1 1 Two leading ONE indicate COMMAND Mode 8.2.4 C5 C4 C3 SCLK rising edge Data is transfered from µC C2 C1 X C0 SCLK falling edge Data is sampled CS falling edge signals the end of COMMAND Mode SDI Timing Table 13. SDI Timing Parameters Symbol Parameter Conditions Min Typ Max Units TCSCLK Time CS to Sampling Data 500 ns TDCLK Time Data to Sampling Data 300 ns THCL SCLK High Time 200 ns TCLK SCLK period 1 µs TCLKCS Time Sampling Data to CS down 500 ns TCST CS Toggling time 500 ns Figure 17. SDI Timing Diagram TCST CS SPI SCLK SCL t TCSCLK TDCLK t THCL TCLKCS t TCLK www.ams.com/LF-Receiver/AS3932 Revision 1.7 19 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n 8.3 Channel Amplifier and Frequency Detector Each of the 3 channels consists of a variable gain amplifier, an automatic gain control and a frequency detector. The latter detects the presence of a carrier. As soon as the carrier is detected the AGC is enabled, the gain of the VGA is reduced and set to the right value and the RSSI can be displayed. It is possible to enable/disable individual channels, in case not all three channels are needed. This enables to reduce the current consumption by 1.5 µA (typ.) per channel. 8.3.1 Frequency Detector / AGC The frequency detection uses the RTC as time base. In case the internal RC oscillator is used as RTC, it must be calibrated, but the calibration is guaranteed for a 32.768 kHz crystal oscillator only. The frequency detection criteria can be tighter or more relaxed according to the setup described in R2<1:0> (see Table 14). Table 14. Tolerance Settings for Wake-up R2<1> R2<0> Tolerance 0 0 relaxed 0 1 tighter (medium) 1 0 stringent 1 1 reserved The AGC can operate in two modes: AGC down only (R1<5>=0) AGC up and down (R1<5>=1) As soon as the AGC starts to operate, the gain in the VGA is set to maximum. If the AGC down only mode is selected, the AGC can only decrease the gain. Since the RSSI is directly derived from the VGA gain, the system holds the RSSI peak. When the AGC up and down mode is selected, the RSSI can follow the input signal strength variation in both directions. Regardless which AGC operation mode is used, the AGC needs maximum 35 carrier periods to settle. The RSSI is available for all 3 channels at the same time and it is stored in 3 registers (R10<4:0>, R11<4:0>, R12<4:0>) Both AGC modes (only down or down and up) can also operate with time limitation. This option allows AGC operation only in time slot of 256µs following the internal wake-up. Then the AGC (RSSI) is frozen till the wake-up or RSSI reset occurs. The RSSI is reset either with the direct command 'clear_wakeup' or 'reset_RSSI'. The 'reset_RSSI' command resets only the AGC setting but does not terminate wake-up condition. This means that if the signal is still present the new AGC setting (RSSI) will appear not later than 300µs (35 LF carrier periods) after the command was received. The AGC setting is reset if for duration of 3 Manchester half symbols no carrier is detected. If the wake-up IRQ is cleared the chip will go back to listening mode. In case the maximum amplification at the beginning is a drawback (e.g. in noisy environment) it is possible to set a smaller starting gain on the amplifier, according to the Table 15. In this way it is possible to reduce the false frequency detection. Table 15. Bit Setting of Gain Reduction R4<3> R4<2> R4<1> R4<0> Gain reduction 0 0 0 0 no gain reduction 0 0 0 1 n.a. 0 0 1 0 or 1 n.a. 0 1 0 0 or 1 -4dB 0 1 1 0 or 1 -8dB 1 0 0 0 or 1 -12dB 1 0 1 0 or 1 -16dB 1 1 0 0 or 1 -20dB 1 1 1 0 or 1 -24dB www.ams.com/LF-Receiver/AS3932 Revision 1.7 20 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n 8.3.2 Antenna Damper The antenna damper allows the chip to deal with higher field strength, it is enabled by register R1<4>. It consists of shunt resistors which degrade the quality factor of the resonator by reducing the signal at the input of the amplifier. In this way the resonator sees a smaller parallel resistance (in the band of interest) which degrades its quality factor in order to increase the linear range of the channel amplifier (the amplifier doesn't saturate in presence of bigger signals). Table 16 shows the bit setup. Table 16. Antenna Damper Bit Setup R4<5> R4<4> Shunt resistor (parallel to the resonator at 125 kHz) 0 0 1 kΩ 0 1 3 kΩ 1 0 9 kΩ 1 1 27 kΩ 8.4 Channel Selector / Demodulator / Data Slicer When at least one of three gain channel enters initial wake-up state the channel selector makes a decision which gain channel to connect to the envelope detector. If only one channel is in wake-up state the selection is obvious. If more than one channel enters wake-up state in 256µs following the first active channel the channel with highest RSSI value is selected. The output signal (amplified LF carrier) of selected channel is connected to the input of the demodulator. The performance of the demodulator can be optimized according to bit rate and preamble length as described in Table 17 and Table 18. Table 17. Bit Setup for the Envelop Detector for Different Symbol Rates R3<2> R3<1> R3<0> Symbol rate [Manchester symbols/s] 0 0 0 4096 0 0 1 2184 0 1 0 1490 0 1 1 1130 1 0 0 910 1 0 1 762 1 1 0 655 1 1 1 512 If the bit rate gets higher the time constant in the envelop detector must be set to a smaller value. This means that higher noise is injected because of the wider band. The next table is a rough indication of how the envelop detector looks like for different bit rates. By using proper data slicer settings it is possible to improve the noise immunity paying the penalty of a longer preamble. In fact if the data slicer has a bigger time constant it is possible to reject more noise, but every time a transmission occurs, the data slicer need time to settle. This settling time will influence the length of the preamble. Table 18 gives a correlation between data slicer setup and minimum required preamble length. Table 18. Bit Setup for the Data Slicer for Different Preamble Length R3<5> R3<4> R3<3> Minimum preamble length [ms] 0 0 0 0.8 0 0 1 1.15 0 1 0 1.55 0 1 1 1.9 1 0 0 2.3 1 0 1 2.65 1 1 0 3 1 1 1 3.5 www.ams.com/LF-Receiver/AS3932 Revision 1.7 21 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n Note: These times are minimum required, but it is recommended to prolong the preamble. The comparator of the data slicer can work only with positive or with symmetrical threshold (R3<6>). In addition the threshold can be 20 or 40 mV (R3<7>) In case the length of the preamble is an issue the data slicer can also work with an absolute threshold (R1<7>). In this case the bits R3<2:0> would not influence the performance. It is even possible to reduce the absolute threshold in case the environment is not particularly noisy (R2<7>). 8.5 Correlator After frequency detection the data correlation is only performed if the correlator is enabled (R1<1>=1). The data correlation consists of checking the presence of a preamble (ON/OFF modulated carrier) followed by a certain pattern. After the frequency detection the correlator waits 16 bits (see bit rate definition in Table 19) and if no preamble is detected the chip is set back to listening mode and the false wake-up register (R13<7:0>) is incremented by one. To get started with the pattern correlation the correlator needs to detect at least 4 bits of the preamble (ON/OFF modulated carrier). The bit duration is defined in the register R7<4:0> according to the Table 19 as function of the Real Time Clock (RTC) periods. Table 19. Bit Rate Setup R7<4> R7<3> R7<2> R7<1> R7<0> Bit duration in RTC clock periods Bit rate (bits/s) Symbol rate (Manchester symbols/s) 0 0 0 1 1 4 8192 4096 0 0 1 0 0 5 6552 3276 0 0 1 0 1 6 5460 2730 0 0 1 1 0 7 4680 2340 0 0 1 1 1 8 4096 2048 0 1 0 0 0 9 3640 1820 0 1 0 0 1 10 3276 1638 0 1 0 1 0 11 2978 1489 0 1 0 1 1 12 2730 1365 0 1 1 0 0 13 2520 1260 0 1 1 0 1 14 2340 1170 0 1 1 1 0 15 2184 1092 0 1 1 1 1 16 2048 1024 1 0 0 0 0 17 1926 963 1 0 0 0 1 18 1820 910 1 0 0 1 0 19 1724 862 1 0 0 1 1 20 1638 819 1 0 1 0 0 21 1560 780 1 0 1 0 1 22 1488 744 1 0 1 1 0 23 1424 712 1 0 1 1 1 24 1364 682 1 1 0 0 0 25 1310 655 1 1 0 0 1 26 1260 630 1 1 0 1 0 27 1212 606 1 1 0 1 1 28 1170 585 1 1 1 0 0 29 1128 564 www.ams.com/LF-Receiver/AS3932 Revision 1.7 22 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n Table 19. Bit Rate Setup R7<4> R7<3> R7<2> R7<1> R7<0> Bit duration in RTC clock periods Bit rate (bits/s) Symbol rate (Manchester symbols/s) 1 1 1 0 1 30 1092 546 1 1 1 1 0 31 1056 528 1 1 1 1 1 32 1024 512 If the preamble is detected correctly the correlator keeps searching for a data pattern. The duration of the preamble plus the pattern should not be longer than 40 bits (see bit rate definition in Table 19). The data pattern can be defined by the user and consists of two bytes which are stored in the registers R5<7:0> and R6<7:0>. The two bytes define the pattern consisting of 16 half bit periods. This means the pattern and the bit period can be selected by the user. The only limitation is that the pattern (in combination with preamble) must obey Manchester coding and timing. It must be noted that according to Manchester coding a down-to-up bit transition represents a symbol "0", while a transition up-to-down represents a symbol "1". If the default code is used (96 [hex]) the binary code is (10 01 01 10 01 10 10 01). MSB has to be transmitted first. The user can also select (R1<2>) if single or double data pattern is used for wake-up. In case double pattern detection is set, the same pattern has to be repeated 2 times. Additionally it is possible to set the number of allowed missing zero bits (not symbols) in the received bitstream (R2<6:5>), as shown in the Table 20. Table 20. Allowed Pattern Detection Errors R2<6> R2<5> Maximum allowed error in the pattern detection 0 0 No error allowed 0 1 1 missed zero 1 0 2 missed zeros 1 1 3 missed zeros If the pattern matches the wake-up, interrupt is displayed on the WAKE output. If the pattern detection fails, the internal wake-up (on all active channels) is terminated with no signal sent to MCU and the false wake-up register will be incremented (R13<7:0>). 8.6 Wake-up Protocol - Carrier Frequency 125 kHz The wake-up state is terminated with the direct command ‘clear_wake’ Table 12. This command terminates the MCU activity. The termination can also be automatic in case there is no response from MCU. The time out for automatic termination is set in a register R7<7:5>, as shown in the Table 21. Table 21. Timeout Setup R7<7> R7<6> R7<5> Time out 0 0 0 0 sec 0 0 1 50 msec 0 1 0 100 msec 0 1 1 150 msec 1 0 0 200 msec 1 0 1 250 msec 1 1 0 300 msec 1 1 1 350 msec www.ams.com/LF-Receiver/AS3932 Revision 1.7 23 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n 8.6.1 Without Pattern Detection Figure 18. Wake-up Protocol Overview without Pattern Detection (only carrier frequency detection) Carrier Burst Data Carrier Burst > 550 us DAT WAKE Clear_wake In case the data correlation is disabled (R1<1>=0) the AS3932 wakes up upon detection of the carrier frequency only as shown in Figure 18. In order to ensure that AS3932 wakes up the carrier burst has to last longer than 550 µs. To set AS3932 back to listening mode there are two possibilities: either the microcontroller sends the direct command clear_wake via SDI or the time out option is used (R7<7:5>). In case the latter is chosen, AS3932 is automatically set to listening mode after the time defined in T_OUT (R7<7:5>), counting starts at the low-to-high WAKE edge on the WAKE pin. 8.6.2 Single Pattern Detection The Figure 19 shows the wake-up protocol in case the pattern correlation is enabled (R1<1>=1) for a 125 kHz carrier frequency. The initial carrier burst has to be longer than 550 µs and can last maximum 16 bits (see bit rate definition in Table 19). If the ON/OFF mode is used (R1<5>=1), the minimum value of the maximum carrier burst duration is limited to 10 ms. This is summarized in Table 22. In case the carrier burst is too long the internal wake-up will be set back to low and the false wake-up counter (R13<7:0>) will be incremented by one. The carrier burst must be followed by a preamble (0101... modulated carrier with a bit duration defined in Table 19) and the wake-up pattern stored in the registers R5<7:0> and R6<7:0>. The preamble must have at least 4 bits and the preamble duration together with the pattern should not be longer than 40 bits. If the wake-up pattern is correct, the signal on the WAKE pin goes high one bit after the end of the pattern and the data transmission can get started. To set the chip back to listening mode the direct command clear_wake, as well as the time out option (R7<7:5>) can be used. www.ams.com/LF-Receiver/AS3932 Revision 1.7 24 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 19. Wake-up Protocol Overview with Single Pattern Detection Carrier Burst 1 bit Preamble Carrier Burst > 550 µs Carrier Burst < 16 bit duration Preamble Pattern Data 1 bit Preamble Preamble > 4 bit duration Preamble + Pattern < 40 bit duration DAT WAKE Clear_wake Table 22. Preamble Requirements in Standard Mode, Scanning Mode and ON/OFF Mode Bit rate (bit/s) Maximum duration of the carrier burst in Standard Mode and Scanning Mode (ms) Maximum duration of the carrier burst in ON/OFF Mode (ms) 8192 1.95 10 6552 2.44 10 5460 2.93 10 4680 3.41 10 4096 3.90 10 3640 4.39 10 3276 4.88 10 2978 5.37 10 2730 5.86 10 2520 6.34 10 2340 6.83 10 2184 7.32 10 2048 7.81 10 1926 8.30 10 1820 8.79 10 1724 9.28 10 1638 9.76 10 www.ams.com/LF-Receiver/AS3932 Revision 1.7 25 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n Table 22. Preamble Requirements in Standard Mode, Scanning Mode and ON/OFF Mode Bit rate (bit/s) Maximum duration of the carrier burst in Standard Mode and Scanning Mode (ms) Maximum duration of the carrier burst in ON/OFF Mode (ms) 1560 10.25 10.25 1488 10.75 10.75 1424 11.23 11.23 1364 11.73 11.73 1310 12.21 12.21 1260 12.69 12.69 1212 13.20 13.20 1170 13.67 13.67 1128 14.18 14.18 1092 14.65 14.65 1056 15.15 15.15 1024 15.62 15.62 8.7 False Wake-up Register The wake-up strategy in the AS3932 is based on 2 steps: 1. Frequency Detection: in this phase the frequency of the received signal is checked. 2. Pattern Correlation: here the pattern is demodulated and checked whether it corresponds to the valid one. If there is a disturber or noise capable to overcome the first step (frequency detection) without producing a valid pattern, then a false wake-up call happens.Each time this event is recognized a counter is incremented by one and the respective counter value is stored in a memory cell (false wake-up register). Thus, the microcontroller can periodically look at the false wake-up register, to get a feeling how noisy the surrounding environment is and can then react accordingly (e.g. reducing the gain of the LNA during frequency detection, set the AS3932 temporarily to power down etc.), as shown in the Figure 20. The false wake-up counter is a useful tool to quickly adapt the system to any changes in the noise environment and thus avoid false wake-up events. Most wake-up receivers have to deal with environments that can rapidly change. By periodically monitoring the number of false wake-up events it is possible to adapt the system setup to the actual characteristics of the environment and enables a better use of the full flexibility of AS3932. www.ams.com/LF-Receiver/AS3932 Revision 1.7 26 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n Figure 20. Concept of the False Wake-up Register together with the system Frequency Detector Wakeup Level 1 Wakeup Level 2 Pattern Correlator WAKE Unsuccessful pattern correlation False wakeup register CHANGE SETUP TO MINIMIZE THE FALSE WAKEUP EVENTS Register Setup READ FALSE WAKEUP REGISTER Microcontroller 8.8 Real Time Clock (RTC) The RTC can be based on a crystal oscillator (R1<0>=1), the internal RC-oscillator (R1<0>=0), or an external clock source (R1<0>=1). The crystal oscillator has higher precision of the frequency with higher current consumption and needs three external components (crystal plus two capacitors). The RC-oscillator is completely integrated and can be calibrated if a reference signal is available for a very short time to improve the frequency accuracy. The calibration gets started with the trim_osc direct command. Since no non-volatile memory is available the calibration must be done every time after the RCO is turned off. The RCO is turned off when the chip is in power down mode, a POR happened, or the crystal oscillator is enabled. Since the RTC defines the time base of the frequency detection, the selected frequency (frequency of the crystal oscillator or the reference frequency used for calibration of the RC oscillator) should be about one forth of the carrier frequency: FRTC ~ FCAR * 0.25 (EQ 1) Where: FCAR is the carrier frequency and FRTC is the RTC frequency The third option for the RTC is the use of an external clock source, which must be applied directly to the XIN pin (XOUT floating). www.ams.com/LF-Receiver/AS3932 Revision 1.7 27 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n 8.8.1 Crystal Oscillator Table 23. Characteristics of XTAL Symbol Parameter Conditions Crystal accuracy (initial) Overall accuracy Min Typ Crystal motional resistance Units ±120 p.p.m. 60 KΩ Frequency 32.768 kHz Contribution of the oscillator to the frequency error ±5 p.p.m 1 s Start-up Time Crystal dependent Duty cycle 45 Current consumption 8.8.2 Max 50 55 1 % µA RC-Oscillator Table 24. Characteristics of RCO Symbol Parameter Frequency Calibration time Conditions Min Typ Max Units If no calibration is performed 27 32.768 42 kHz If calibration is performed 31 32.768 34.5 kHz 65 cycles Periods of reference clock Current consumption 200 nA To trim the RC-Oscillator, set the chip select (CS) to high before sending the direct command trim_osc over SDI. Then 65 digital clock cycles of the reference clock (e.g. 32.768 kHz) have to be sent on the clock bus (SCLK), as shown in Figure 21. After that the signal on the chip select (CS) has to be pulled down. The calibration is effective after the 65th reference clock edge and it will be stored in a volatile memory. In case the RC-oscillator is switched off or a power-on-reset happens (e.g. battery change) the calibration has to be repeated. Figure 21. RC-Oscillator Calibration via SDI www.ams.com/LF-Receiver/AS3932 Revision 1.7 28 - 34 AS3932 Datasheet - D e t a i l e d D e s c r i p t i o n 8.8.3 External Clock Source To clock the AS3932 with an external signal the crystal oscillator has to be enabled (R1<0>=1). As shown in the Figure 3 the clock must be applied on the pin XIN while the pin XOUT must stay floating. The RC time constant has to be 15µs with a tolerance of ±10% (e.g. R=680 kΩ and C=22pF). In the Table 25 the clock characteristics are summarized. Table 25. Characteristics of External Clock Symbol Parameter VI Low level Vh High level Tr Conditions Min Max Units 0 0.1 * VDD V 0.9 * VDD VDD V Rise-time 3 µs Tf Fall-time 3 µs T = RC RC Time constant 16.5 µs 13.5 Typ 15 Note: In power down mode the external clock has to be set to VDD. 8.9 Channel Selection in Scanning Mode and ON/OFF Mode In case only 2 channels are active and one of the Low Power modes is enabled, then the channels 1 and 3 have to be active. If the chip works in On-Off mode and only one channel is active then the active channel has to be the channel 1. Both Low Power modes are not allowed to be enabled at the same time. www.ams.com/LF-Receiver/AS3932 Revision 1.7 29 - 34 AS3932 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 9 Package Drawings and Markings The product is available in a 16-pin TSSOP package. Figure 22. Drawings and Dimensions AS3932 @ YYWWMZZ Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. Symbol A A1 A2 b c D E E1 e L L1 Min 0.05 0.80 0.19 0.09 4.90 4.30 0.45 - Nom 1.00 5.00 6.40 BSC 4.40 0.65 BSC 0.60 1.00 REF Max 1.20 0.15 1.05 0.30 0.20 5.10 4.50 0.75 - Symbol R R1 S θ1 θ2 θ3 aaa bbb ccc ddd N Min 0.09 0.09 0.20 0º - Nom 12 REF 12 REF 0.10 0.10 0.05 0.20 16 Max 8º - Marking: YYWWMZZ. YY WW M ZZ @ Year (i.e. 10 for 2010) Manufacturing Week Assembly plant identifier Assembly traceability code Sublot identifier www.ams.com/LF-Receiver/AS3932 Revision 1.7 30 - 34 AS3932 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s The product is available in a 16LD QFN (4x4) package. Figure 23. Drawings and Dimensions AS3932 YYWWXZZ @ Notes: 1. Dimensions and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. Angles are in degrees. 3. Dimension b applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip. Dimension L1 represents terminal full back from package edge up to 0.15mm is acceptable. 4. Coplanarity applies to the exposed heat slug as well as the terminal. 5. Radius on terminal is optional. 6. N is the total number of terminals. Symbol A A1 A3 L L1 b D E e D2 E2 aaa bbb ccc ddd eee fff N Min 0.80 0 0.40 0 0.25 2.30 2.30 - Nom 0.90 0.02 0.20 REF 0.50 0.30 4.00 BSC 4.00 BSC 0.65 BSC 2.40 2.40 0.15 0.10 0.10 0.05 0.08 0.10 16 Max 1.00 0.05 0.60 0.15 0.35 2.50 2.50 - Marking: YYWWXZZ. YY WW X ZZ @ Year (i.e. 10 for 2010) Manufacturing Week Assembly plant identifier Assembly traceability code Sublot identifier www.ams.com/LF-Receiver/AS3932 Revision 1.7 31 - 34 AS3932 Datasheet - R e v i s i o n H i s t o r y Revision History Table 26. Revision History Revision Date 1.0 Feb 12, 2009 1.0a Feb 24, 2009 1.1 Owner Description Table 27 (Ordering information), -Z removed from part numbers New figure inserted Figure 2 on page 2, all subsequent chapters and page numbers are therefore incremented by one Apr 2, 2009 esn Default Values of RegistersTable 7, default value of R4<3:0> corrected Bit Setting of Gain ReductionTable 15, stepsize of gain reduction increased to -4dBm 1.11 Apr 22, 2009 Description of external components on page 12 updated 1.12 May 25, 2009 Update of Section 10 Ordering Information on page 33 1.13 Jul 13, 2009 Updated Wake-up Protocol - Carrier Frequency 125 kHz 8.6 and description of Section 8.8.2 RC-Oscillator on page 28 Updated Key Features for External Clock Added Figure 3 AS3932 Typical Application Diagram with Clock from External Source Added External Clock Source in Electrical System SpecificationsTable 5 1.2 Oct 13, 2009 Deleted table Minimum duration of carrier burst in ON/OFF mode (Manchester decoder enabled) mrh Updated Real Time Clock (RTC) 8.8 with External Clock Added External Clock Source 8.8.3 Added a new section SDI Timing 8.2.4 1.3 Updated R11 and R12 in Table 7 Mar 25, 2010 Updated clock frequency of SDI to 2MHz in Serial Data Interface (SDI) 8.2.3 Updated time constant of RC filter in External Clock Source 8.8.3 1.4 1.5 1.6 1.7 Sep 21, 2010 Updated Figure 19 and Figure 8.7 Mar 04, 2011 Updated General Description, Key Features, Figure 1, Figure 2, Figure 3, Figure 4, Table 1, Figure 5, Table 2, Figure 10, Section 8.1.4, Table 6, Table 7, Section 8.1.4, Section 8.6.1, Figure 19, Section 8.6.2, Package Drawings and Markings. Deleted figure “Synchronization of Data with Recovered Manchester Clock” and chapter on “Single Pattern Detection (Manchester decoder enabled)” rlc Mar 17, 2011 Updated Absolute Maximum Ratings Jun 14, 2011 Deleted max value for IPWD parameter Feb 04, 2012 Jun 18, 2013 jry Corrected data inconsistencies across the datasheet. Corrected package drawings in Figure 23 on page 31. Note: Typos may not be explicitly mentioned under revision history. www.ams.com/LF-Receiver/AS3932 Revision 1.7 32 - 34 AS3932 Datasheet - O r d e r i n g I n f o r m a t i o n 10 Ordering Information The devices are available as the standard products shown in Table 27. Table 27. Ordering Information 1 Ordering Code Type Marking Delivery Form Delivery Quantity AS3932-BTST 16-pin TSSOP AS3932 7 inches Tape & Reel 1000 pcs AS3932-BQFT 16LD QFN (4x4) AS3932 7 inches Tape & Reel 1000 pcs 1. Dry Pack Sensitivity Level =3 according to IPC/JEDEC J-STD-033A for full reels. Note: All products are RoHS compliant and ams green. Buy our products or get free samples online at www.ams.com/ICdirect Technical Support is available at www.ams.com/Technical-Support For further information and requests, email us at [email protected] (or) find your local distributor at www.ams.com/distributor www.ams.com/LF-Receiver/AS3932 Revision 1.7 33 - 34 AS3932 Datasheet - C o p y r i g h t s Copyrights Copyright © 1997-2013, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. 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Contact Information Headquarters ams AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel Fax : +43 (0) 3136 500 0 : +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.ams.com/contact www.ams.com/LF-Receiver/AS3932 Revision 1.7 34 - 34