AMSCO AS5130-ASST-OM

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ams AG
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D atas hee t
AS5130
8-Bit Programmable Magnetic Rotary Encoder with Motion Detection
& Multiturn
2 Key Features
Two digital 8-bit absolute outputs:
- Serial interface
- Pulse width modulated (PWM) output
User programmable zero position
High speed: up to 30000 rpm
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360º contactless angular position encoding
Failure detection mode for magnet placement monitoring and
loss of power supply
Wide temperature range: -40ºC to +125ºC
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The AS5130 is a contactless magnetic rotary encoder for accurate
angular measurement over a full turn of 360º. It is a system-on-chip,
combining integrated Hall elements, analog front end and digital
signal processing in a single device. The angle can be measured
using only a simple two-pole magnet rotating over the center of the
chip. The magnet may be placed above or below the IC. The
absolute angle measurement provides instant indication of the
magnet’s angular position with a resolution of 8 bit = 256 positions
per revolution. This digital data is available as a serial bit stream and
as a PWM signal. The AS5130 can be operated in pulsed mode
(Vsupply=off), which reduces the average power consumption
significantly. During Vsupply=off, the measured angle can be stored
using an internal storage register supplied by a low power voltage
line. This mode achieves very low power consumption during polling
of the rotary position of the magnet. If the position of the magnet
changes, then the motion detection feature wakes up an external
system. The device is capable of counting the amount of magnet
revolutions. The multi turn counter value is stored in a register and
can be read in addition to the angle information. Furthermore, any
arbitrary position can be set as zero-position. The system is tolerant
to misalignment, air gap variations, temperature variations and
external magnetic fields and high reliability due to non-contact
sensing.
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1 General Description
Multi Turn counter / Movement detection
Small Pb-free package: SSOP-16 (5.3mm x 6.2mm)
Automotive qualified to AEC-Q100, grade 1
3 Applications
The AS5130 is an ideal solution for Ignition key position sensing,
Steering wheel position sensing, Transmission gearbox encoder,
Front panel rotary switches and replacement of Potentiometers.
Figure 1. AS5130 Block Diagram
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SINP / SINN / COSP / COSN
AS5130
PWM Decoder
PWM
Ang
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Sin
Hall Array
&
Frontend
Amplifier
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Zero
Postion
Tracking ADC
& Angle
Decoder
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Cos
Absolute
Serial
Interface
(SSI)
Mag
DIO
CS
DCLK
C1
AGC
AGC
Power Management
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CAO
OTP
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AS5130
Datasheet - C o n t e n t s
Contents
1
2 Key Features.............................................................................................................................................................................
1
3 Applications...............................................................................................................................................................................
1
4 Pin Assignments .......................................................................................................................................................................
4
4.1 Pin Descriptions....................................................................................................................................................................................
4
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1 General Description ..................................................................................................................................................................
5 Absolute Maximum Ratings ......................................................................................................................................................
5
6 Electrical Characteristics...........................................................................................................................................................
6
8
8
7 Detailed Description..................................................................................................................................................................
9
7.1 Connecting the AS5130........................................................................................................................................................................
9
Serial 3-Wire Connection (Default Setting).................................................................................................................................. 9
Serial 3-Wire Connection (OTP Programming Option).............................................................................................................. 11
1-Wire PWM Connection ........................................................................................................................................................... 11
Analog Output............................................................................................................................................................................ 12
Analog Sin/Cos Outputs with External Interpolator.................................................................................................................... 13
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7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
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6.1 Timing Characteristics ..........................................................................................................................................................................
6.2 Magnetic Input Range ..........................................................................................................................................................................
7.2 Serial Synchronous Interface (SSI) ....................................................................................................................................................
15
7.2.1 Commands of the SSI in Normal Mode ..................................................................................................................................... 15
7.2.2 Commands of the SSI in Extended Mode.................................................................................................................................. 16
7.3 OTP Programming..............................................................................................................................................................................
17
7.4 Multi Turn Counter..............................................................................................................................................................................
19
7.5 AS5130 Status Indicators ...................................................................................................................................................................
19
7.5.1 Lock Status Bit........................................................................................................................................................................... 19
7.5.2 Magnetic Field Strength Indicators ............................................................................................................................................ 19
7.6 “Pushbutton” Feature..........................................................................................................................................................................
7.7 High Speed Operation ........................................................................................................................................................................
Propagation Delay .....................................................................................................................................................................
Sampling Rate ...........................................................................................................................................................................
Chip Internal Lowpass Filtering .................................................................................................................................................
Digital Readout Rate..................................................................................................................................................................
Total Propagation Delay of the AS5130 ....................................................................................................................................
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7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.8 Reduced Power Modes ......................................................................................................................................................................
20
21
21
21
21
21
21
22
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7.8.1 Low Power Mode ....................................................................................................................................................................... 22
7.8.2 Power Cycling Mode.................................................................................................................................................................. 23
7.8.3 Polling Mode .............................................................................................................................................................................. 24
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8 Application Information ...........................................................................................................................................................
27
27
8.2 Application Example II: Low-Power Encoder......................................................................................................................................
28
8.3 Application Example III: Polling Mode ................................................................................................................................................
29
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8.1 Application Example I: 3-Wire Sensor with Magnetic Field Strength Indication .................................................................................
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AS5130
Datasheet - C o n t e n t s
8.4 Accuracy of the Encoder System .......................................................................................................................................................
Quantization Error......................................................................................................................................................................
Vertical Distance of the Magnet.................................................................................................................................................
Choosing the Proper Magnet.....................................................................................................................................................
Magnet Placement.....................................................................................................................................................................
Lateral Displacement of the Magnet ..........................................................................................................................................
Magnet Size...............................................................................................................................................................................
30
32
33
34
35
36
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8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
30
9 Package Drawings and Markings ...........................................................................................................................................
37
9.1 Recommended PCB Footprint............................................................................................................................................................
40
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10 Ordering Information.............................................................................................................................................................
38
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AS5130
Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
1
16
DVDD
PROG
2
15
PWM
VSS
3
14
WAKE
SINP
4
13
C1
SINN
5
12
VDD
COSP
6
11
DIO
COSN
7
10
CS
TestCoil
8
9
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AS5130
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Figure 2. Pin Assignments (Top View)
DCLK
4.1 Pin Descriptions
Pin Name
CAO
PROG
VSS
SINP
SINN
COSP
COSN
Description
1
Indicates if the magnetic field is present. If the field is too low, the signal is HI.
2
OTP Programming Pad, programming voltage. For normal operation it must be left
unconnected.
3
Supply Ground.
4
Used for factory testing. For normal operation it must be left unconnected.
5
Used for factory testing. For normal operation it must be left unconnected.
6
Used for factory testing. For normal operation it must be left unconnected.
7
Used for factory testing. For normal operation it must be left unconnected.
8
Test pin. Must be left unconnected.
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Test Coil
Pin Number
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Table 1. Pin Descriptions
9
Clock Source for SSI communication. Schmitt trigger input.
CS
10
Chip Select for SSI. Active high. Schmitt trigger input.
DIO
11
Data input / output for SSI communication.
VDD
12
Positive Supply Voltage 5V.
C1
13
Test mode selector. For normal operation it must be connected to VSS.
WAKE
14
Interrupt output. Used for polling mode. Open Drain NMOS. Use pull-up resistor with
>1.5kΩ.
PWM
15
Pulse Width Modulation output. 0.5µs width step per LSB.
16
Pin to connect to low power supply for polling mode. Must be connected to VSS in normal
mode.
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DCLK
DVDD
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AS5130
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 6 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Min
Max
Units
Comments
Supply Voltage
0.3
7
V
Only relevant for polling operation mode, supply
voltage with capacitor of the integrated storage register
during toff phase of VDD
Input Pin Voltage
VSS-0.5
VDD
V
Input Current (latchup immunity)
-100
100
mA
Norm: EIA/JESD78 ClassII Level A
±2
kV
Norm: JESD22-A114E
168
K/W
Still Air / Single Layer PCB
Package Thermal Resistance SSOP-16
133
-55
150
ºC
-40
125
ºC
150
ºC
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Storage Temperature
Ambient Temperature
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Electrostatic Discharge
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Parameter
Junction Temperature
Package body temperature
Humidity non-condensing
5
ºC
85
%
3
Represents a maximum floor life time of 168h
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Moisture Sensitivity Level (MSL)
260
Norm: IPC/JEDEC J-STD-020.
The reflow peak soldering temperature (body
temperature) specified is in accordance with IPC/
JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Non-Hermetic Solid State Surface
Mount Devices”.
The lead finish for Pb-free leaded packages is matte tin
(100% Sn).
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AS5130
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
TAMB = -40ºC to +125ºC, unless otherwise noted.
Table 3. Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Units
VDD
Positive Supply Voltage
Except OTP programming
4.5
5
5.5
V
DVDD
Polling Mode Supply Voltage
3.6
5
5.5
V
IDD
Power Supply Current
14
24
mA
Ioff
Power Down Mode
2
mA
N
Resolution
1.4
8
Startup from zero
deg
2000
Startup with preset AGC - Polling mode
(Supplied during toff phase of VDD from the
external buffer capacitor via DVDD pin)
250
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Power Up Time
TPwrUp
bit
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1.406
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Symbol
Startup from low power mode
150
tda
Propagation Delay
Analog signal path; over full temperature
range
tdd
Tracking rate
Step rate of tracking ADC;
1 step = 1.406º
tdelay
Signal Processing Delay
Total signal processing delay, Analog +
Digital + SSI readout
(tda + tdd + tSSI)
T
Analog filter time constant
Internal lowpass filter
4.1
Centered Magnet
-2
2
Accuracy
Within horizontal displacement radius (see
parameters for magnet)
-3
3
Transition Noise
rms (1 sigma)
INLcm
TN
PORr
Power-On-Reset levels
PORf
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Parameters for Magnet
1.15
1.45
µs
21.55
µs
12.5
µs
6.6
0.235
4,3
V
VDD falling
3.4
3.7
3.9
V
-30000
30000
rpm
MD
Magnet diameter
Diametrically magnetized
MT
Magnet thickness
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µs
4
Frequencies above 1000 rpm causes an
additional not specified DNL Error
6
mm
2.5
mm
Magnetic input range
Valid for use of full range of sensitivity
32
75
mT
Magnetic Sensitivity of AGC
AGC value available at SSI
0.5
5
LSB/mT
Magnetic Offset
Magnetic stray field without gradient
4
mT
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BDC
17
3.7
Rotational Speed
s
0.85
15
VDD rising
n
Bi
µs
DC/AC Characteristics for Digital Inputs and Outputs
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CMOS Input
0.7 x
VDD
VIH
High level Input voltage
VIL
Low level Input Voltage
0.3 x
VDD
V
ILEAK
Input Leakage Current
1
µA
V
CMOS Output
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AS5130
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
Min
Typ
Max
VOH
High level Output voltage
VOL
Low level Output Voltage
VSS +
0.4
V
CL
Capacitive Load
35
pF
tslew
Slew Rate
tdelay
Time Rise Fall
Vout_wake up
Wake up output
VDD 0.5
Units
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V
Open drain output with tri-state behavior
Programming Parameters
30
ns
15
ns
5
V
8.5
V
100
mA
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External capacitive load C_L = 35pF
External series resistance R = 0Ω
Junction temperature TJ = 136ºC
Rise time of the internal driver t_rise = 3ns
Fall time of the internal driver t_fall = 3ns
VPROG
Programming Voltage
IPROG
Programming Current
TambPROG
Programming ambient temperature
During programming
0
85
ºC
tPROG
Programming time
Timing is internally generated
2
4
µs
Analog readback voltage
During Analog Readback mode at pin
PROG
VR,unprog
WakeLSB
Angle difference threshold for wake up Factory setting is 4 LSB, value is accessible
by SSI in buffered register and can be
generation
changed by customer.
8-bit PWM output
8.0
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VR,prog
Static voltage at pin PROG
0.5
2.2
3.5
0
127
V
LSB
PWM resolution
PWMIN
PWM pulse width
Angle = 0º (00H)
0.71
0.55
0.43
µs
PWMAX
PWM pulse width
Angle = 358.6º (FFH)
182.88
142.24
108.48
µs
PWP
PWM Period
Over full temperature range
183.6
142.8
108.9
µs
fPWM
PWM Frequency
=1 / PWM period
5.44
7
9.18
kHz
Hyst
Digital hysteresis
At change of rotation direction
Serial 8-bit Output
fCLK
Normal operation
Clock Frequency
During OTP programming
1
6
166.6
250
bit
bit
MHz
ns
500
kHz
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fCLK, P
8
Clock Frequency
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tCLK
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NPWM
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AS5130
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6.1 Timing Characteristics
TAMB = -40ºC to 125ºC, unless otherwise noted.
Table 4. Timing Characteristics
Rising CLK to CS
t1
Min
Typ
Max
Units
15
--
ns
Chip select to positive edge of CLK
15
--
ns
t2
Chip select to drive bus externally
--
--
ns
t3
Setup time command bit,
Data valid to positive edge of CLK
30
t4
Hold time command bit,
Data valid after positive edge of CLK
30
t5
Float time,
Positive edge of CLK for last command bit to
bus float
30
t6
Bus driving time,
Positive edge of CLK for last command bit to
bus drive
CLK/2
+0
CLK/2
+30
ns
t7
Setup time data bit,
Data valid to positive edge of CLK
CLK/2
+0
CLK/2
+30
ns
t8
Hold time data bit,
Data valid after positive edge of CLK
CLK/2
+0
CLK/2
+30
ns
t9
Hold time chip select,
Positive edge CLK to negative edge of chip
select
30
t10
Bus floating time,
Negative edge of chip select to float bus
0
30
ns
tTO
Timeout period in 2-wire mode (from rising
edge of CLK)
20
24
µs
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t0
Conditions
ns
ns
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Parameter
CLK/2
ns
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Symbol
ns
6.2 Magnetic Input Range
The magnetic input range is defined by the AGC loop. This regulating loop keeps the Hall sensor output in the optimum range for low SNR by
adjusting the Hall bias current. This loop can adjust to a magnetic field strength variation of ±38%. The AGC output voltage is an indicator for the
magnetic field.
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The nominal magnetic field for a balanced AGC is defined by the Hall bias and the Hall sensitivity and can be set by a variable gain in the signal
path. The gain can be set in 8 steps in the OTP or by the SSI in a mirror register. The resulting magnetic input range is a value of Bnominal±38%
inside of a range of 32mT …75mT, if the trimming is performed by the customer.
Setting
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Table 5. Magnetic Input Range
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
Gain A
0.9
1.05
1.2
1.4
1.65
1.9
2.2
2.55
Blimit
Max. 75mT
Min. 32mT
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Binary
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
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Figure 3. Typical Arrangement of AS5130 and Magnet
7.1 Connecting the AS5130
The AS5130 can be connected to an external controller in several ways as listed below:
Serial 3-wire connection (default setting)
Serial 3-wire connection (OTP programming option)
1-wire PWM connection
Analog output
Analog Sin/Cos outputs with external interpolator
7.1.1
Serial 3-Wire Connection (Default Setting)
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In this mode, the AS5130 is connected to the external controller via three SSI signals: Chip Select (CS), Clock (CLK) input and DIO (Data) in/
output. This configuration not only helps to read and write data but also defines different operation modes. The data transfer in all cases is done
via the DIO port.
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Figure 4. Standard SSI Serial Data Interface
+5V
VDD
VDD
VDD
CS
100n
AS5130
AS5130
micro
controller
CLK
DIO
VSS
VSS
VSS
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 5. Normal Operation Mode
CMD_PHASE
DATA_PHASE
READ: Device to µC
WRITE: µC to Device
t1
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DCLK
t9
CS
t5
CMD4
t3
CMD3
CMD2
CMD1
t4
DIO
CMD0
t6
CMD
t7
t8
D15
t10
D14
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t2
DIO
D0
D13
t11
t13
t12
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DIO
READ
D15
D13
D14
D0
WRITE
Table 6. Serial Bit Sequence (16-bit read/write)
Write Command
C4
C3
C2
C1
Read/Write Data
C0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 6. Extended Operation Mode (for access of OTP only)
DATA_PHASE
CMD_PHASE
t1
CS
t2
DIO
t5
CMD3
CMD2
CMD1
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CMD4
t3
t4
t7
CMD0
CMD
t8
t6
t10
D44
D45
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DIO
t9
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DCLK
t11
READ
D0
t12
DIO
t13
D45
D44
WRITE
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D0
Table 7. Serial Bit Sequence (16-bit read/write)
Write Command
C4
C3
C2
C1
Read/Write Data
C0
D15
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D14
D13
D12
D11
D10
D9
Revision 1.12
D8
D7
D6
D5
D4
D3
D2
D1
D0
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
7.1.2
Serial 3-Wire Connection (OTP Programming Option)
This mode provides with an option to configure the serial interface for programming the OTP register. Using a clock input (CLK), DIO (Data) in/
output and CS pin, it is possible to write and read out data from the OTP Register. The data transfer is done via the DIO channel. For
programming, the PROG pin must be connected to +8V. Analog readout for trimming verification is mandatory.
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Figure 7. Serial Data Transmission in Continuous Readout Mode
+5V
VDD
VDD
Output
VDD
Output
I/O
DIO
8.0 - 8.5V
PROG
C1
AS5130
AS5130
100n
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micro
controller
DCLK
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CS
+
VSS
10µF 100n
VSS
-
VSS
Note: For further details on OTP programming, please refer to OTP Programming (page 17).
7.1.3
1-Wire PWM Connection
If the line (PWM) is used as angle output, the total number of connections can be reduced to three, including the supply lines. This type of
configuration is especially useful for remote sensors. Low power mode is not possible in this configuration. If the AS5130 angular data is invalid,
the PWM output will remain at low state.
100n
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Figure 8. Data Transmission with Pulse Width Modulated (PWM) Output
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+5V
VDD
VDD
VDD
AS5130
micro
controller
PWM
VSS
VSS
VSS
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
The minimum PWM pulse width tON (PWM = high) is 1 LSB @ 0º (Angle reading = 00H). 1LSB = nom. ,0.556µs. The PWM pulse width increases
with 1LSB per step. At the maximum angle 358.6º (Angle reading = FFH), the pulse width tON (PWM = high) is 256 LSB and the pause width tOFF
(PWM = low) is 1 LSB. This leads to a total period (tON + tOFF) of 257LSB.
PWM out
71.7µs
0.556µs
142.3µs
ton
142.3µs
0.556µs
71.15µs
toff
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5V
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Figure 9. PWM Output Signal
Position
255
128
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0
Table 8. PWM Signal Parameters
Position
Angle
LSB @ High
t_high
Low Column
t_low
Duty-Cycle
0
0º
1
0.556µs
256
142.3µs
0.39%
127
178.59º
128
71.15µs
129
71.7µs
49.4%
128
180º
129
71.7µs
128
71.15µs
50.2%
358.59º
256
142.3µs
1
0.556µs
99.6%
255
This means that the PWM pulse width is (position + 1) LSB, where position is 0….255.
The tolerance of the absolute pulse width and frequency can be eliminated by calculating the angle with the duty cycle rather than with the
absolute pulse width:
t ON
angle [ 8 - bit ] = ⎛ 257 --------------------------⎞ -1
⎝
t ON + t OFF⎠
(EQ 1)
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results in an 8-bit value from 00H to FFH,
t ON ⎞
⎛ 257 -------------------------–1
⎝
t ON + t OFF⎠
(EQ 2)
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360
angle [ º ] = --------256
results in a degree value from 0º ...358.6º
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Note: The absolute frequency tolerance is eliminated by dividing tON by (tON+TOFF), as the change of the absolute timing effects both TON
and TOFF in the same way.
7.1.4
Analog Output
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The AS5130 can generate a ratiometric analog output voltage by low-pass filtering the PWM output. Figure 10 shows a simple passive 2nd order
low pass filter as an example. In order to minimize the ripple on the analog output, the cut-off frequency of the low pass filter should be well below
the PWM base frequency.
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Revision 1.12
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 10. Ratiometric Analog Output
+5V
VDD
R≥4k7
C≥1µF
PWM
analog
out
VSS
micro
controller
VSS
lv
AS5130
100n
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VDD
VDD
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VSS
5V
Analog out
0V
PWMout
Angle
0º
360º
Analog Sin/Cos Outputs with External Interpolator
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7.1.5
180º
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By connecting C1 to VDD, the AS5130 provides analog Sine and Cosine outputs (SINP, COSP) of the Hall array front-end for test purposes.
These outputs allow the user to perform the angle calculation by an external ADC + µC, e.g. to compute the angle with a high resolution. In
addition, the inverted Sinus and Cosine signals (SINN, COSN; see dotted lines) are available for differential signal transmission.
The input resistance of the receiving amplifier or ADC should be greater than 100kΩ. The signal lines should be kept as short as possible, longer
lines should be shielded in order to achieve best noise performance.
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The SINN / COSN / SINP / COSP signals are amplitude controlled to ~1.3Vp (differential) by the internal AGC controller. The DC bias voltage is
2.25 V.
Te
If the SINN and COSN outputs cannot be sampled simultaneously, it is recommended to disable the automatic gain control (see Table 9) as the
signal amplitudes may be changing between two readings of the external ADC. This may lead to less accurate results.
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
VDD
C1 VDD
D A
SINN
SINP
D A
COSN
COSP
micro
controller
AS5130
AS5130
VSS
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VSS
100n
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+5V
VDD
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Figure 11. Sine and Cosine Outputs for External Angle Calculation
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VSS
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Revision 1.12
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
7.2 Serial Synchronous Interface (SSI)
7.2.1
Commands of the SSI in Normal Mode
Table 9. SSI in Normal Mode
mode
23
22
WRITE CUST
10111
write
WD2COS
10110
write
21
SET TEST
CFG1
10101
write
20
reserved
10100
write
19
HYST_RST
10011
write
18
WD2SIN
10010
17
WRITE
CONFIG
16
--
7
READ CUST
00111
6
RD2COS
00110
4
RD_BOTH
00100
3
STORE REF
00011
2
RD2SIN
00010
5
15
14
xen_7
inv_7
write
xen_7
inv_7
10001
write
go2sle
ep
10000
write
RD_MULTI
00001
0
RD_ANGLE
00000
11
10
9
8
7
6
5
4
3
gain <2:0>
xen_6 inv_6 xen_5
inv_5
rst_m
ulti
nc
inv_5
read
read
inv_7
gain <2:0>
xen_6 inv_6 xen_5
inv_5
0
xen_4 inv_4 xen_3 inv_3 xen_2 inv_2 xen_1 inv_1 xen_0 inv_0
wlsb <6:0>
xen_7
1
nc
setHy
st
xen_6 inv_6 xen_5
2
xen_4 inv_4 xen_3 inv_3 xen_2 inv_2 xen_1 inv_1 xen_0 inv_0
gen_r
st
nc
1
12
wlsb <6:0>
rst_otp
00101
13
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bin
lv
cmd
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#
nc
parity
xen_4 inv_4 xen_3 inv_3 xen_2 inv_2 xen_1 inv_1 xen_0 inv_0
read
read
Multiturn <7:0>
read
store_ vdd_ok reg_s
ok
et
read
xen_7
inv_7
angle <7:0>
nc
xen_6 inv_6 xen_5
angle_stored <7:0>
inv_5
parity
xen_4 inv_4 xen_3 inv_3 xen_2 inv_2 xen_1 inv_1 xen_0 inv_0
read
lock
agc <5:0>
Multiturn <7:0>
parity
read
lock
agc <5:0>
angle <7:0>
parity
WD2COS / WD2SIN: xen_X disables Hall element X from the sensor array in the cosine or sine channel; xinv_X inverts the voltage output of Hall
element X in the channels.
RD2COS / RD2SIN: The Hall array configuration for cosine and sine channel can be read out by these commands, initial values are 0.
SET TEST CFG 1: gen_rst HI triggers a digital reset.
WRITE CONFIG: go2sleep HI activates the low power mode of the AS5130. The power consumption is significantly reduced. go2sleep LO
returns to normal operation mode. During low power mode, the lock bit in command 0 and command 1 is LO.
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WRITE CUST: With “wlsb_x” the threshold level for generation of a WAKE pulse is set (only important in polling mode). The initial value is 4 LSB.
No value lower than 4 LSB can be set. The maximum value is 127 LSB.
“gain_x” sets the gain in the signal
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HYST_RST: “setHyst” enables an additional hysteresis of the digital output signal. It is enabled by default. Only after 2 consecutive equal signals
the output is changed.
“rst_otp” forces the IC to read out the OTP in polling mode. This reset has to be performed after initial startup and every WAKE signal.
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“rst_multi” resets the multi turn counter to 0.
READ CUST: With this command “wlsb_x” and “gain_x” can be read out.
RD_BOTH: Angle and multi turn counter value can be read out simultaneously by this command. Due to limited data size, the parity bit is not
available in this command.
Te
STORE REF: This command stores the actual angle as reference angle in the storage registers (only important in polling mode). The output is
the stored angle (angle_stored), a flag, if the voltage at DVDD is OK (store_ok), a flag, if the supply voltage is OK (vdd_ok) and a check bit, if the
register was written.
RD_MULTI: Command for read out of multi turn register (multiturn) and AGC value (agc). “Lock” indicates a locked ADC and “parity” an even
parity checksum.
RD_ANGLE: Command for read out of angle value and AGC value (agc). “Lock” indicates a locked ADC and “parity” an even parity checksum.
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
7.2.2
Commands of the SSI in Extended Mode
For programming or readout of the OTP data, the chip has to be started with DVDD at a low voltage (polling mode off or cap discharged) or the
OTP reset has to be performed. If not, the OTP is not read out and the OTP data is not available.
Table 10. SSI in Extended Mode
cmd
bin
mode
<45:44>
31
WRITE_O
TP
11111
xt write
OTP Test
30
11110
xt write
29
11101
xt write
xt write
11011
xt write
11010
xt write
11001
xt write
24
11000
xt write
15
01111
xt read
14
01110
xt read
13
01101
xt read
12
01100
xt read
11
01011
xt read
10
01010
xt read
01001
xt read
01000
xt read
26
25
9
8
PROG_OT
P
RD_OTP_
ANA
<27:26>
<25>
<24:23>
<22:20>
<19:16>
<15:12>
<11:9>
<8>
<7:0>
ID
OTP
lock
VREF
Hall Bias
Osc
Redundan Sensitivi
cy
ty
Wake
enable
Zero
Angle
OTP Test
ID
OTP
lock
VREF
Hall Bias
Osc
Redundan Sensitivi
cy
ty
Wake
enable
Zero
Angle
OTP Test
ID
OTP
lock
VREF
Hall Bias
Osc
Redundan Sensitivi
cy
ty
Wake
enable
Zero
Angle
lv
11100
27
<31:28>
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28
<43:32>
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#
WRITE OTP: Writing of the OTP register. The written data is volatile. “Zero Angle” is the angle, which is set for zero position. “Wake enable”
enables the polling mode. “Sensitivity” is the gain setting in the signal path. “Redundancy is a number of bits, which allows the customer to
overwrite one of the customer OTP bits <0:11>.
PROG_OTP: Programming of the OTP register. Only Bits <0:15> can be programmed by the customer.
RD_OTP: Read out the content of the OTP register. Data written by WRITE_OTP and PROG_OTP is read out.
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RD_OTP_ANA: Analog read out mode. The analog value of every OTP bit is available at pin 2 (PROG), which allows for a verification of the fuse
process. No data is available at the SSI.
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
7.3 OTP Programming
For programming of the OTP, an additional voltage has to be applied to the pin PROG. It has to be buffered by a fast 100nF capacitor (ceramic)
and a 10µF capacitor. The information to be programmed is set by command 25. The OTP bits 16 to 45 are used for AMS factory trimming and
cannot be overwritten.
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Figure 12. OTP Programming Connection
+5V
VDD
VDD
Output
Output
micro
controller
DCLK
I/O
AS5130
AS5130
DIO
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8.0 - 8.5V
100n
lv
VDD
CS
+
VSS
10µF 100n
PROG
C1
VSS
-
VSS
Figure 13. External Circuitry for OTP Programming
maximum
parasitic cable
inductance
VSUPPLY
L<50nH
Vzapp
ca
C1
C2
PROG
GND
PROM Cell
10µF
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ni
100nF
VDD
Vprog
Table 11. OTP Programming Parameters
Parameter
Min
Max
Unit
VDD
Supply Voltage
5
5.5
V
GND
Ground Level
0
0
V
V_zapp
Programming Voltage
8
8.5
V
T_zapp
Temperature
0
85
ºC
f_clk
CLK Frequency
100
kHz
Te
Symbol
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Revision 1.12
Notes
At pin PROG
At pin DCLK
17 - 41
AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
Programming Verification. After programming, the programmed OTP bits are verified in following two ways:
By Digital Verification: This is simply done by sending a READ OTP command (#0FH, Refer to Table 10). The structure of this register is the
same as for the OTP PROG or OTP WRITE commands.
By Analog Verification: By sending an ANALOG OTP READ command (#09H), pin PROG becomes an output, sending an analog voltage with
each clock, representing a sequence of the bits in the OTP register. A voltage of <500mV indicates a correctly programmed bit (“1”) while a
voltage level between 2.2V and 3.5V indicates a correctly unprogrammed bit (“0”). Any voltage level in between indicates improper programming.
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Figure 14. Analog OTP Verification
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+5V
VDD
VDD
VDD
Output
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CS
Output
micro
controller
CLK
I/O
AS5130
AS5130
DIO
100n
PROG
VSS
V
C1
VSS
VSS
Redundancy Decoding. If a bit is not fused properly (analog readout levels violated), the redundancy bits can be used as shown in the table
replaced bit
<15:12>
replaced bit
none
1000
7
0
1001
8
1
1010
9
ni
below. Only one single bit can be overwritten with a logic HI. An improper fusing cannot be made undone.
<15:12>
2
1011
10
3
1100
11
4
1101
none
0110
5
1110
none
0111
6
1111
none
ca
0000
0001
0010
0011
0100
Te
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0101
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
7.4 Multi Turn Counter
An 8-bit register is used for counting the magnet’s revolutions. With each zero transition in any direction, the output of a special counter is
incremented or decremented. The initial value after reset is 0 LSB.
The multi turn value is encoded as complement on two. Clockwise rotation gives increasing angle values and positive turn count. Counter
clockwise rotation exhibits decreasing angle values and a negative turn count respectively.
Decimal Value
01111111
127
---
---
00000011
+3
00000010
+2
00000001
+1
00000000
0
11111111
-1
11111110
-2
11111101
-3
---
---
10000000
-128
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Bit Code
The counter output can be reset by using command 19 – HYST_RST. It is immediately reset by the rising clock edge of this bit. Any zero crossing
between the clock edge and the next counter readout changes the counter value.
7.5 AS5130 Status Indicators
7.5.1
Lock Status Bit
The Lock signal indicates whether the angle information is valid (ADC locked, Lock = high) or invalid (ADC unlocked, Lock = low). To determine
a valid angular signal at best performance, the following indicators should be set:
Lock = 1
0x00h < AGC < 0x2Fh
7.5.2
ca
Note: The angle signal may also be valid (Lock = 1), when the AGC is out of range (00H or 2FH), but the accuracy of the AS5130 may be
reduced due to the out of range condition of the magnetic field strength.
Magnetic Field Strength Indicators
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The AS5130 is not only able to sense the angle of a rotating magnet, it can also measure the magnetic field strength (and hence the vertical
distance) of the magnet. This additional feature can be used for several purposes:
ch
- as a safety feature by constantly monitoring the presence and proper vertical distance of the magnet
- as a state-of-health indicator, e.g. for a power-up self test
- as a pushbutton feature for rotate-and-push types of manual input devices
The magnetic field strength information is available in two forms – Magnetic field strength hardware indicator and Magnetic field strength
software indicator.
Te
Magnetic Field Strength Hardware Indicator. Pin CAO (#1) will be low, when the magnetic field is too weak. The switching limit is
determined by the value of the AGC. If the AGC value is <3FH, the CAO output will be high (green range), If the AGC is at its upper limit (3FH),
the CAO output will be low (red range).
Magnetic Field Strength Software Indicator. D13:D7 in the serial data that is obtained by command READ ANGLE (see Table 9)
contains the 6-bit AGC information. The AGC is an automatic gain control that adjusts the internal signal amplitude obtained from the Hall
elements to a constant level. If the magnetic field is weak, e.g. with a large vertical gap between magnet and IC, with a weak magnet or at
elevated temperatures of the magnet, the AGC value will be high. Likewise, the AGC value will be lower when the magnet is closer to the IC,
when strong magnets are used and at low temperatures.
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
The best performance of the AS5130 will be achieved when operating within the AGC range. It will still be operational outside the AGC range, but
with reduced performance especially with a weak magnetic field due to increased noise.
Factors Influencing the AGC Value. In practical use, the AGC value will depend on several factors:
The initial strength of the magnet. Aging magnets may show a reducing magnetic field over time which results in an increase of the AGC
value. The effect of this phenomenon is relatively small and can easily be compensated by the AGC.
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The vertical distance of the magnet. Depending on the mechanical setup and assembly tolerances, there will always be some variation of
the vertical distance between magnet and IC over the lifetime of the application using the AS5130. Again, vertical distance variations can be
compensated by the AGC.
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The temperature and material of the magnet. The recommended magnet for the AS5130 is a diametrically magnetized 6mm diameter
magnet. Other magnets may also be used as long as they can maintain to operate the AS5130 within the AGC range. Every magnet has a
temperature dependence of the magnetic field strength. The temperature coefficient of a magnet depends on the used material. At elevated
temperatures, the magnetic field strength of a magnet is reduced, resulting in an increase of the AGC value. At low temperatures, the magnetic field strength is increased, resulting in a decrease of the AGC value. The variation of magnetic field strength over temperature is automatically compensated by the AGC.
OTP Sensitivity Adjustment. To obtain best performance and tolerance against temperature or vertical distance fluctuations, the AGC value
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at normal operating temperature should be in the middle between minimum and maximum, hence it should be around 32 (20H). To facilitate the
“vertical centering” of the magnet+IC assembly, the sensitivity of the AS5130 can be adjusted in the OTP register in 8 steps (see Table 10). The
OTP sensitivity setting corresponds to the customer register setting gain <2:0>.
7.6 “Pushbutton” Feature
Using the magnetic field strength software and hardware indicators described above, the AS5130 provides a useful method of detecting both
rotation and vertical distance simultaneously. This is especially useful in applications implementing a rotate-and-push type of human interface
(e.g. in panel knobs and switches).
The CAO output is low, when the magnetic field is below the low limit (weak or no magnet) and high when the magnetic field is above the low limit
(in-range or strong magnet).
A finer detection of a vertical distance change, for example when only short vertical strokes are made by the pushbutton, is achieved by
memorizing the AGC value in normal operation and triggering on a change from that nominal the AGC value to detect a vertical movement.
Figure 15. Magnetic Field Strength Indicator
ca
+5V
VDD
VDD
CAO
Output
CS
Output
DCLK
I/O
AS5130
AS5130
100n
DIO
C1
VSS
VSS
VSS
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micro controller
VDD
1k
LED1
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Revision 1.12
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
7.7 High Speed Operation
The AS5130 is using a fast tracking ADC (TADC) to determine the angle of the magnet. The TADC has a tracking rate of 1.15µs (typ).
Once the TADC is synchronized with the angle, it sets the LOCK bit in the status register (see Table 9). In worst case, usually at start-up, the
TADC requires a maximum of 127 steps (127 * 1.15µS = 146.05µs) to lock. Once it is locked, it requires only one cycle (1.15µs) to track the
moving magnet.
The AS5130 can operate in locked mode at rotational speeds up to 30,000 rpm.
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In Low Power Mode, the position of the TADC is frozen. It will continue from the frozen position once it is powered up again. If the magnet has
moved during the power down phase, several cycles will be required before the TADC is locked again. The tracking time to lock in with the new
magnet angle can be roughly calculated as:
(EQ 3)
7.7.1
Propagation Delay
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tLOCK = 1.15µs* |NewPos – OldPos|
Where:
tLOCK = time required to acquire the new angle after power up from one of the reduced power modes [µs]
OldPos = Angle position when one of the reduced power modes is activated [º]
NewPos = Angle position after resuming from reduced power mode [º]
7.7.2
Sampling Rate
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The Propagation delay is the time required from reading the magnetic field by the Hall sensors to calculating the angle and making it available on
the serial or PWM interface. While the propagation delay is usually negligible on low speeds, it is an important parameter at high speeds. The
longer the propagation delay, the larger becomes the angle error for a rotating magnet as the magnet is moving while the angle is calculated. The
position error increases linearly with speed. The main factors that contribute to the propagation delay are discussed in detail further in this
document.
For high speed applications, fast ADCs are essential. The ADC sampling rate directly influences the propagation delay. The fast tracking ADC
used in the AS5130 with a tracking rate of only 1.15µs (typ) is a perfect fit for both high speed and high performance.
7.7.3
Chip Internal Lowpass Filtering
A commonplace practice for systems using analog-to-digital converters is to filter the input signal by an anti-aliasing filter. The filter characteristic
must be chosen carefully to balance propagation delay and noise. The lowpass filter in the AS5130 has a cutoff frequency of typ. 23.8kHz and
the overall propagation delay in the analog signal path is typ. 15.6µs.
7.7.4
Digital Readout Rate
7.7.5
ca
Aside from the chip-internal propagation delay, the time required to read and process the angle data must also be considered. Due to its nature,
a PWM signal is not very usable at high speeds, as you get only one reading per PWM period. Increasing the PWM frequency may improve the
situation but causes problems for the receiving controller to resolve the PWM steps. The frequency on the AS5130 PWM output is typ. 1.95kHz
with a resolution of 2µs/step. A more suitable approach for high speed absolute angle measurement is using the serial interface. With a clock
rate of up to 6MHz, a complete set of data (21bits) can be read in >3.5µs.
Total Propagation Delay of the AS5130
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The total propagation delay of the AS5130 is the delay in the analog signal path and the tracking rate of the ADC:
15.6µs + 1.15µs = 16.75µs
(EQ 4)
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If only the SIN-/COS-outputs are used, the propagation delay is the analog signal path delay only (typ. 15.6µs).
Position Error Over Speed: The angle error over speed caused by the propagation delay is calculated as:
-6
Δθpd = rpm * 6 * 16.75E
in degrees
(EQ 5)
Te
In addition, the anti-aliasing filter causes an angle error calculated as:
Δθlpf = ArcTan [rpm / (60*f0)]
(EQ 6)
Table 12. Examples of the Overall Position Error caused by Speed (includes both propagation delay and filter delay)
Speed (rpm)
Total Position Error (Δθpd + Δθlpf)
100
0.0175º
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 12. Examples of the Overall Position Error caused by Speed (includes both propagation delay and filter delay)
Speed (rpm)
Total Position Error (Δθpd + Δθlpf)
1000
0.175º
10000
1.75º
7.8 Reduced Power Modes
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Low Power Mode: reduced current consumption, very fast start-up. Ideal for short sampling intervals (<3ms).
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The AS5130 can be operated in three reduced power modes. All three modes have in common that they switch off or freeze parts of the chip
during intervals between measurements. In Low Power Mode or Ultra Low Power Mode, the AS5130 is not operational, but due to the fast startup, an angle measurement can be accomplished very quickly and the chip can be switched to reduced power immediately after a valid
measurement has been taken. Depending on the intervals between measurements, very low average power consumption can be achieved using
such a strobed measurement mode.
Power Cycling Mode: zero power consumption (externally switched off) during sampling intervals, but slower start-up than Polling Mode.
Ideal for sampling intervals 200ms.
7.8.1
Low Power Mode
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Polling Mode: for reduction of the average power consumption; especially suited for battery powered applications.
The AS5130 can be put in Low Power Mode by simple serial commands, using the regular SSI commands. The required serial command is
WRITE CONFIG (17H, Figure 4 on page 9). The angle data is valid, as soon as the LOCK- Flag is 1 (see Table 9).
In Reduced Power Modes, the AS5130 is inactive. The last state, e.g. the angle, AGC value, etc. is frozen and the chip starts from this frozen
state when it resumes active operation. This method provides much faster start-up than a “cold start” from zero.
Figure 16. Low Power Mode and Ultra Low Power Mode Connection
R1
Ion
Ioff
VDD
ton
+5V
VDD
toff
VDD
on/off
C1
AS5130
S
ca
100n
N
CS
DCLK
DIO
AS5130
VSS C1
micro
controller
ni
VSS
Te
ch
VSS
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Revision 1.12
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
If the AS5130 is cycled between active and reduced current mode, a substantial reduction of the average supply current can be achieved. The
minimum dwelling time in active mode is the wake-up time. The actual active time depends on how much the magnet has moved while the
AS5130 was in reduced power mode. The angle data is valid, when the status bit LOCK has been set (see Table 9). Once a valid angle has been
measured, the AS5130 can be put back to reduced power mode. The average power consumption can be calculated as:
I active∗ t on + I powerdown∗ t off
Iavg = --------------------------------------------------------------------t on + t off
sampling interval = ton + toff
(EQ 7)
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Where:
Iavg = Average current consumption
Iactive = Current consumption in active mode
Ipower_down = Current consumption in reduced power mode
ton = Time period during which the chip is operated in active mode
toff = Time period during which the chip is in reduced power mode
7.8.2
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Reducing Power Supply Peak Currents. An optional RC-filter (Rx/Cx) may be added to avoid peak currents in the power supply line when
the AS5130 is toggled between active and reduced power mode. Rx must be chosen such that it can maintain a VDD voltage of 4.5 – 5.5V under
all conditions, especially during long active periods when the charge on Cx has expired. Cx should be chosen such that it can support peak
currents during the active operation period. For long active periods, Cx should be large and Rx should be small.
Power Cycling Mode
The power cycling method shown in Figure 17 cycles the AS5130 by switching it on and off, using an external PNP transistor high side switch.
The current consumption in off-mode is zero. It also has the longest start-up time of all modes, as the chip must always perform a “cold start“
from zero, which takes about 2ms (Compare with Low Power Mode on page 22).
Figure 17. Power Cycling Mode
Rx
Ion
0
N
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AS5130
S
+5V
VDD
ton toff
toff
10k
VDD
100n
ton
Cx
>µF
CS
DCLK
DIO
AS5130
VSS C1
VDD
on/off
micro
controller
ni
VSS
Te
ch
VSS
The optional filter Rx/Cx may again be added to reduce peak currents in the 5V power supply line (see Reducing Power Supply Peak Currents
on page 23).
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Revision 1.12
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
7.8.3
Polling Mode
Target of this mode is a reduction of the average power consumption. In this mode, the IC supply is pulsed, thereby reducing the average power
consumption to a fraction. The actual angle information and multi turn count value is not lost; polling mode is especially suited for battery
powered applications. The IC is furthermore capable of generating a WAKE signal as soon as the magnet’s position has changed, but only if the
supply of the IC is powered-on again. By means of the WAKE signal, the system’s power consumption can be further decreased, if certain
modules are activated on demand.
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Figure 18. External Circuitry for Polling Mode
>1.5K
WAKE
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on A
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st
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VSS
AS5130
DVDD
lv
+5V
VDD
t_wakeup
100n
t_off
t_on
The voltage at pin 16 (DVDD) determines whether polling mode is activated or not. Any voltage above 3.6V activates the polling functionality.
This voltage must always be present at DVDD in order to hold the information in the registers.
The procedure is as follows:
Te
ch
ni
ca
1. Initial startup: The circuit starts up with invalid trim values, which are read back from the storage registers; the command rst_otp
(command 19 – 10011) must be sent to read out valid trim values from the OTP.
2. These values are copied to the storage registers if OTP<8> (Wake enable) is set (must be set for polling mode).
3. The values of AGC counter, actual angle, multi turn counter, hysteresis setting, wake threshold and gain setting are continuously
updated in the storage registers.
4. The actual angle is stored as a reference by sending command STORE REF (command 3 – 00011). without this reference angle, a
WAKE is generated at every startup.
5. The update of the storage registers is stopped if VDD drops below 4.45V and then the information is stored (DVDD) at the next startup
(VDD on), the values are read back from the storage registers and the measured angle is compared with the stored reference angle; if
the difference between both exceeds the threshold, a WAKE pulse is generated.
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Revision 1.12
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
Figure 19. Wake Up Signal Flowchart
VDD on (fast)
POR
store_ok
HI
reset & reset_storage
reset digital core only
Retrieve values from storage registers
WAKE (26 clk periods)
OTP readout (46bit - 140us ... 400us)
Compare mode
HI
| α measured –
store_ok ?
α stored| > α threshold
true
false
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st
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Normal mode
lv
WAKE_ON
LO
Wait (162 clks - 86us ... 95us)
al
id
LO
Copy to Storage
WAKE (20 clk periods)
Normal mode
command rst_otp
true
false
OTP readout (OTP <8> = HI
Figure 21 shows the behavior of the wake up signal. The wake up signal will be low for twakeup = 10us. After that, the wake up signal will go to tristate condition. In case of an angle comparison with a result below the threshold, the signal will remain in tri-state condition. After switching on
VDD, the system needs max. 250us to generate an angle with maximum accuracy. A WAKE signal cannot be expected until the end of this
period.
WAKE Interface. An open drain NMOS structure is used in the WAKE pad. In order to generate a clear output signal level, a pull up resistor is
required. The pad can drive 4mA.
ca
Figure 20. WAKE Output Pin
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ch
ni
VDD
www.austriamicrosystems.com/AS5130
pull up
resistor
PAD
WAKE
AS5130
Revision 1.12
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AS5130
Datasheet - D e t a i l e d D e s c r i p t i o n
Table 13. WAKE Interface Parameters
Parameter
Min
Max
Unit
Notes
Rpull_up
Pull up resistor
1.5
100
kΩ
The used pad can drive 4mA.
twake up
Wake up pulse
10
17
µs
Interrupt signal to external devices, tri-state output, low
active.
ton
On-time
250
---
µs
Time for power up in polling mode.
toff
Off-time
---
---
ms
No limit unless DVDD is always supplied.
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id
Symbol
t_off
t_on
am
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on A
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st
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t_on
lv
Figure 21. Wake Up Signal During Polling Mode of VDD
VDD
tri-state
tri-state
WAKE
t_wakeup
delta (actual - reference angle) </=
threshold
Te
ch
ni
ca
delta (actual - reference angle) >
threshold
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Revision 1.12
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AS5130
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8 Application Information
Benefits of AS5130 are as following:
Complete system-on-chip
Flexible system solution providing absolute angle position, with serial data and PWM output
High reliability due to non-contact sensing
Robust system, tolerant to misalignment, airgap variations, temperature variations and external magnetic fields
8.1 Application Example I: 3-Wire Sensor with Magnetic Field Strength Indication
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id
Ideal for applications in harsh environments due to magnetic sensing principle
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In Figure 22, a simple 360º sensor with PWM output is shown. The complete application requires only three wires, VDD, VSS and the PWM
output. The circle over the center of the chip represents the diametrically polarized magnet. Additionally, the CAO pin will deliver an analog
voltage indicating a missing magnetic field. This signal could be used to drive an external LED or to detect an alert signal.
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Figure 22. 3-Wire Angle Sensor
+5V
1k
LED1
VDD
PROG
CAO
100n
AS5130
S
AS5130
VSS
CAO
CS
N
DCLK
PWM
PWM out
DIO
Te
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VSS
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AS5130
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.2 Application Example II: Low-Power Encoder
Via SSI, the AS5130 will be able to toggle between active mode and low power mode. In active mode, the current consumption is ~15mA and in
low power mode 2mA. The fastest possible startup time from low power mode is 150µs. The AS5130 can be periodically switched between
active and low power mode, the average power consumption depends on the duty cycle. In order to read out the correct data, the active mode
time must be larger than 150µs.
VDD
VDD
on/off
am
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st
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CS
lv
+5V
VDD
al
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Figure 23. Low Power Encoder
100n
AS5130
S
N
CLK
DIO
AS5130
VSS
micro
controller
VSS
VSS
I active∗ t on + I powerdown∗ t off
Iavg = --------------------------------------------------------------------t on + t off
(EQ 8)
Example: sampling period = one measurement every 10ms.
ca
System constants = Iactive = 15mA, Ipower_down = 2 mA, toff = 9,85ms, ton(min) = 150µs (start-up from low power mode):
(EQ 9)
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15mA∗ 150μs + 2mA∗ 9, 85ms
Iavg = -------------------------------------------------------------------------- = 2.195mA
150μs + 9, 85ms
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AS5130
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.3 Application Example III: Polling Mode
+5V
VDD
ton toff
+5V
DVDD
100n
AS5130
S
10k
N
Cx
>1µF
CS
CLK
VDD
on/off
micro
controller
DIO
am
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on A
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st
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AS5130
VSS
lv
VDD
al
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Figure 24. Polling Mode
VSS
VSS
Once powered up for at least 2.5ms, the AS5130 can be operated in a pulsed mode, where it is periodically turned on/off by a high side FET
(PMOS) switching transistor with a low Ron (<10Ω). The on-time is at least 250µs in order to perform one measurement. A valid measurement
result can be verified by checking the lock bit (ADC is locked) in the serial data stream.
ca
After startup an OTP reset has to be performed in order to read out valid trimming information. Then a special SSI command (STORE REF)
copies the actual angle into a buffered reference angle register. Now the AS5130 can be turned off. Special registers will be buffered by the low
power supply and will keep the actual settings. After a ton of min. 250 us, the actual angle is compared with the stored reference angle. If the
angle difference is larger than a threshold value (wlsb, SSI command WRITE CUST), the AS5130 will send an interrupt request to an external
device via the WAKE pin.
ni
Due to the internal POR level of the IC, ton starts after VDD has reached 4.3V (worst case POR level).The average power consumption in this
pulsed mode depends on the supply current in active mode and the duty cycle of the on/off pulse:
I active∗ t on
Iavg = ------------------------t on + t off
(EQ 10)
19mA∗ 250μs
Iavg = ------------------------------------------ = 47.5µA
250μs + 99.75ms
(EQ 11)
Te
ch
Example: Sampling period = one measurement every 100ms. System constants = Iactive = 19mA, ton(min) = 250µs:
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Revision 1.12
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AS5130
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.4 Accuracy of the Encoder System
This section enlightens on the individual factors that influence the accuracy of the encoder system, and provides techniques to improve them.
Accuracy is defined as the difference between measured angle and actual angle. This is not to be confused with resolution, which is the smallest
step that the system can resolve. The two parameters are not necessarily linked together. A high resolution encoder may not necessarily be
highly accurate as well.
8.4.1
Quantization Error
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id
There is however a direct link between resolution and accuracy, which is the quantization error:
Quantization
Error
+1/2 LSB
ideal function
ideal function
digitized
function
digitized
function
low
resolution
high
resolution
error
+1/2 LSB
-1/2 LSB
ca
-1/2 LSB
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Figure 25. Quantization Error of a Low Resolution and a High Resolution System
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The resolution of the encoder determines the smallest step size. The angle error caused by quantization cannot get better than ± ½ LSB. As
shown in Figure 25, a higher resolution system (right picture) has a smaller quantization error, as the step size is smaller. For the AS5130, the
quantization error is ± ½ LSB = ± 0.7º
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Revision 1.12
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AS5130
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 26. Typical INL Error over 360º
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INL including quantization error
1,5
1
lv
INL [°]
0,5
0
-1
-1,5
0
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-0,5
45
90
135
180
225
270
315
360
Angle steps
INL
Average (16x)
Figure 26 shows a typical example of an error curve over a full turn of 360º at a given X-Y- displacement. The curve includes the quantization
error, transition noise and the system error. The total error is ~2.2º peak/peak (+/-1.1º).
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The sawtooth-like quantization error (see Figure 25) can be reduced by averaging, provided that the magnet is in constant motion and there are
an adequate number of samples available. The solid bold line in Figure 26 shows the moving average of 16 samples. The INL (intrinsic nonlinearity) is reduced to from ~+/- 1.1º down to ~ +/-0.3º. The averaging however, also increases the total propagation delay, therefore it may be
considered for low speeds only or adaptive; depending on speed (see Position Error Over Speed: on page 21).
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AS5130
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.4.2
Vertical Distance of the Magnet
The chip-internal automatic gain control (AGC) regulates the input signal amplitude for the tracking-ADC to a constant value. This improves the
accuracy of the encoder and enhances the tolerance for the vertical distance of the magnet.
al
id
Figure 27. Typical Curves for Vertical Distance versus ACG Value on Several Untrimmed Samples
64
2,2
56
lv
Linearity and AGC vs Airgap
1,8
40
32
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st
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AGC value
48
1,6
24
Linearity [°]
2,0
1,4
16
1,2
8
0
0
500
1000
1500
2000
1,0
2500
Airgap [µm]
sample#2
sample#3
sample#4
Linearity [°]
ca
sample#1
ni
As shown in Figure 27, the AGC value (left Y-axis) increases with vertical distance of the magnet. Consequently, it is a good indicator for
determining the vertical position of the magnet, for example as a pushbutton feature, as an indicator for a defective magnet or as a preventive
warning (e.g. for wear on a ball bearing etc.) when the nominal AGC value drifts away. If the magnet is too close or the magnetic field is too
strong, the AGC will be reading 0. If the magnet is too far away (or missing) or if the magnetic field is too weak, the AGC will be reading 63 (3FH).
Te
ch
The AS5130 will still operate outside the AGC range, but the accuracy may be reduced as the signal amplitude can no longer be kept at a
constant level. The linearity curve in Figure 27 (right Y-axis) shows that the accuracy of the AS5130 is best within the AGC range, even slightly
better at small airgaps (0.4 – 0.8mm). At very short distances (0 – 0.1) the accuracy is reduced, mainly due to nonlinearities in the magnetic field.
At larger distances, outside the AGC range (~2.0 – 2.5mm and more) the accuracy is still very good, only slightly decreased from the nominal
accuracy. Since the field strength of a magnet changes with temperature, the AGC will also change when the temperature of the magnet
changes. At low temperatures, the magnetic field will be stronger and the AGC value will decrease. At elevated temperatures, the magnetic field
will be weaker and the AGC value will increase.
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AS5130
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.4.3
Choosing the Proper Magnet
There is no strict requirement on the type or shape of the magnet to be used with the AS5130. It can be cylindrical as well as square in shape.
The key parameter is that the vertical magnetic field Bz measured at a radius of 1mm from the rotation axis is sinusoidal with a peak amplitude of
20...80mT (see Figure 28).
S
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N
lv
typ. 6mm diameter
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Figure 28. Vertical Magnetic Fields of a Rotating Magnet
Magnet axis
Magnet axis
R1
Vertical field
component
N
S
R1 concentric circle;
radius 1.0 mm
Vertical field
component
Bz
(20…80mT)
0
360
Te
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360
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AS5130
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
8.4.4
Magnet Placement
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Ideally, the center of the magnet, the diagonal center of the IC and the rotation axis of the magnet should be in one vertical line. The lateral
displacement of the magnet should be within ±0.25mm from the IC package center or +/-0.5mm from the IC center, including the placement of
the chip within the IC package. The vertical distance should be chosen such that the magnetic field on the die surface is within the specified
limits. The typical distance “z” between the magnet and the package surface is 0.5mm to 1.8mm with the recommended magnet (6mm x 2.5mm).
Larger gaps are possible, as long as the required magnetic field strength stays within the defined limits. A magnetic field outside the specified
range may still produce acceptable results, but with reduced accuracy. The out-of-range condition will be indicated, when the AGC is at the limits
(AGC= 0: field too strong; AGC=63=(3FH): field too weak or missing magnet).
lv
Figure 29. Bz Field Distribution Along the X-axis of a 6mmØ Diametric Magnetized Magnet
Bz; 6mm magnet @y=0; z=1mm
0.0015
S
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N
0.001
0.0005
0
-0.0005
-0.001
-0.0015
3.5
2.5
1.5
0.5
-0.5
-1.5
-2.5
-3.5
ca
X-displacement [mm]
ch
ni
Figure 29 shows a cross sectional view of the vertical magnetic field component Bz between the north and south pole of a 6mm diameter
magnet, measured at a vertical distance of 1mm. The poles of the magnet (maximum level) are about 2.8mm from the magnet center, which is
almost at the outer magnet edges. The magnetic field reaches a peak amplitude of ~±106mT at the poles. The Hall elements are located at a
radius of 1mm (indicated as squares at the bottom of the graph). Due to the side view, the two Hall elements at the Y-axis are overlapping at
X=0mm, therefore only 3 Hall elements are shown. At 1mm radius, the peak amplitude is ~±46mT, respectively a differential amplitude of 92mT.
The vertical magnetic field Bz follows a fairly linear pattern up to about 1.5mm radius. Consequently, even if the magnet is not perfectly centered,
the differential amplitude will be the same as for a centered magnet.
Te
For example, if the magnet is misaligned in X-axis by -0.5mm, the two X-Hall sensors will measure 70mT (@ x = -1.5mm) and -22mt (@ x = 0.5mm). Again, the differential amplitude is 92mT. At larger displacements however, the Bz amplitude becomes nonlinear, which results in larger
errors that mainly affect the accuracy of the system (see Figure 31).
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AS5130
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 30. Vertical Magnetic Field Distribution of a Cylindrical 6mmØ Diametric Magnetized Magnet at 1mm Gap
area of X-Y-misalignment from
center: +/- 0.5mm
N
125
circle of Hall elements on
chip: 1mm radius
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100
75
50
25
0
-25
-50
-75
-100
-125
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Bz [mT]
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BZ; 6mm magnet @ Z=1mm
4
3
2
4
S
3
2
1
0
-1
2
-2
1
0
X-displacement [mm]
-3
-1
Y-displacement [mm]
-4
-2
-3
8.4.5
ca
Figure 30 shows the same vertical field component as Figure 29, but in a 3-dimensional view over an area of ±4mm from the rotational axis.
Lateral Displacement of the Magnet
ni
As shown in the magnet specifications (see Parameters for Magnet under Electrical Characteristics on page 6), the recommended horizontal
position of the magnet axis with respect to the IC package center is within a circle of 0.25mm radius. This includes the placement tolerance of the
IC within the package.
Te
ch
Figure 31 shows a typical error curve at a medium vertical distance of the magnet around 1.2mm (AGC = 24). The X- and Y- axis of the graph
indicate the lateral displacement of the magnet center with respect to the IC center. At X=Y=0, the magnet is perfectly centered over the IC. The
total displacement plotted on the graph is for ±1mm in both directions. The Z-axis displays the worst case INL error over a full turn at each given
X-and Y- displacement. The error includes the quantization error of ±0.7º (refer to Quantization Error on page 30). For example, the accuracy for
a centered magnet is between 1.0 – 1.5º (spec = 2º over full temperature range). Within a radius of 0.5mm, the accuracy is better than 2.0º (spec
= 3º over temperature).
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AS5130
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 31. Typical Error Curve of INL Error Over Lateral Displacement (including quantization error)
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id
INL vs. Displacement: AS5030 for AGC24
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4,500-5,000
4,000-4,500
5,000
3,500-4,000
4,500
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3,000-3,500
4,000
3,500
3,000
2,500
INL [°]
2,000
1,500
1,000
0,500
0,000
2,500-3,000
1000
750
500
250
2,000-2,500
1,500-2,000
1,000-1,500
0,500-1,000
0,000-0,500
0
-1000
-750
-250
-500
-500
-250
0
250
X Displacem ent [µm ]
Y Displacem ent [µm ]
-750
500
-1000
750
8.4.6
Magnet Size
ca
1000
Figure 29 to Figure 31 illustrate a cylindrical magnet with a diameter of 6mm. Smaller magnets may also be used, but since the poles are closer
together, the linear range will also be smaller and consequently the tolerance for lateral misalignment will also be smaller.
ch
ni
If the ±0.25mm lateral misalignment radius (rotation axis to IC package center) is too tight, a larger magnet can be used. Larger magnets have a
larger linear range and allow more misalignment. However at the same time the slope of the magnet is more flat, which results in a lower
differential amplitude. This requires either a stronger magnet or a smaller gap between IC and magnet in order to operate in the amplitudecontrolled area (AGC > 0 and AGC < 63).
In any case, if a magnet other than the recommended 6mm diameter magnet is used, two parameters should be verified:
Te
Verify, that the magnetic field produces a sinusoidal wave, when the magnet is rotated. Note that this can be done with the SIN-/COS- outputs of the AS5130; e.g. rotate the magnet at constant speed and analyze the SIN- (or COS-) output with an FFT-analyzer. It is recommended to disable the AGC for this test (see Analog Sin/Cos Outputs with External Interpolator on page 13).
Verify that the Bz-Curve between the poles is as linear as possible (see Figure 29). This curve may be available from the magnet supplier(s).
Alternatively, the SIN- or COS- output of the AS5130 may also be used together with an X-Y- table to get a Bz-scan of the magnet (as in
Figure 29 or Figure 30). Furthermore, the sinewave tests described above may be re-run at defined X-and Y- misplacements of the magnet
to determine the maximum acceptable lateral displacement range. It is recommended to disable the AGC for both these tests (see Analog
Sin/Cos Outputs with External Interpolator on page 13).
Note: For preferred magnet suppliers, please refer to the austriamicrosystems website (Rotary Encoder section).
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AS5130
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
9 Package Drawings and Markings
The device is available in a 16-Lead Shrink Small Outline Package.
Figure 32. Package Drawings and Dimensions
YYWWMZZ
Te
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513001
Max
1.99
0.21
1.78
0.38
0.25
6.50
8.20
5.60
0.95
8º
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id
Nom
1.86
0.13
1.73
0.30
0.17
6.20
7.80
5.30
0.65 BSC
0.75
1.25 REF
0.25 BSC
4º
16
lv
Min
1.73
0.05
1.68
0.22
0.09
5.90
7.40
5.00
0.55
0.09
0º
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Symbol
A
A1
A2
b
c
D
E
E1
e
L
L1
L2
R
Θ
N
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AS5130
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters, angle are in degrees.
Marking: YYWWMZZ.
WW
M
ZZ
Year
Manufacturing Week
Assembly plant identifier
Assembly traceability code
9.1 Recommended PCB Footprint
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Figure 33. PCB Footprint
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YY
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Recommended Footprint Data
Symbol
mm
inch
A
9.02
0.355
B
6.16
0.242
C
0.46
0.018
D
0.65
0.025
E
5.01
0.197
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AS5130
Datasheet - R e v i s i o n H i s t o r y
Revision History
Revision
Date
Owner
Description
1.5
May 31, 2007
Initial version
1.6
Sep 11, 2008
Ordering code updated
1.9
Mar 03, 2009
Updated Absolute Maximum Ratings (page 5)
1.11
Jun 09, 2010
1) Replaced instances of ‘sleep mode’ to ‘low power mode’
2) Removed duplicate instances of TpwrUp and N; Deleted Hyst from Table 6.
3) Replaced instances of AVDD to VDD
4) Updated diagram for Extended Operation Mode (for access of OTP
only) (page 10)
1.12
May 12, 2011
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rfu
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1.10
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Feb 02, 2010
Updated values for the following parameters (see Electrical Characteristics on
page 6)
1) Power Supply Current
2) PWM Period
3) PWM Frequency
apg
mub
Updated Absolute Maximum Ratings, Electrical Characteristics, Package
Drawings and Markings.
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Note: Typos may not be explicitly mentioned under revision history.
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AS5130
Datasheet - O r d e r i n g I n f o r m a t i o n
10 Ordering Information
The devices are available as the standard products shown in Table 14.
Table 14. Ordering Information
Delivery Form
8-bit Magnetic Rotary Encoder with Multiturn function
Tape & Reel
Tubes
Package
16-pin SSOP (5.3mm x 6.2mm)
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical Support is available at http://www.austriamicrosystems.com/Technical-Support
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For further information and requests, please contact us mailto: sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
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AS5130-ASST-OM
AS5130-ASSU-OM
Description
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Ordering Code
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AS5130
Datasheet - C o p y r i g h t s
Copyrights
Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®.
All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of
the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
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Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale.
austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding
the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at
any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for
current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range,
unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are
specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100
parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location.
Contact Information
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Headquarters
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The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not
be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use,
interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
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austriamicrosystems AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
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Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
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http://www.austriamicrosystems.com/contact
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Revision 1.12
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