AMSCO AS8515

AS8515
D a t a A cq u is i t io n S y st e m w i t h P o w e r M a n a g em en t and L IN Tr an sc e iv er
for 12V Battery Sensor Applications
1 General Description
The AS8515 is designed for simultaneous measurement of shunt
current sensor signal and battery voltage by two independent ADC
channels. Both channels can measure small signals up to ±219 mV
versus ground through programmable gain amplifier or larger signals
in the 1V range without amplifier. After analog to digital conversion
and digital filtering, the resulting digital values are accessible through
4-wire serial interface. The device is powered directly from the
battery through LDO and provides a 3.3V supply for an external
microcontroller. For communication with the next level ECU, the
device offers a LIN 2.1 transceiver. Measurement of battery voltage
is supported through resistive attenuator with disable for power
saving in standby.
The device is a stacked die system providing a high voltage CMOS
IC for power management and transceiver functions as a Top die
and low voltage sensor interface functions as a Bottom die inside
a 32-pin MLF (5x5 mm) package.
Internal temperature sensor
Synchronous acquisition for both ADC channels
Reference-voltage source (high precision and high stability)
Offset auto zero
architecture on both channels
Current monitoring comparator with interrupt signal generation
and µC clock enable. Timer with 2 related outputs for single
shot sampling of current and voltage channel in low power
mode.
Precision on chip RC oscillator or external clock. Low slew, low
EMC clock output which can be used by external
microcontroller which is enabled respectively disabled by mode
control through SPI and interrupt from current monitor in low
power mode.
The integrated circuit can execute measurements with internal and
external sensors and sources for the voltage channel and with
external sensor for the current channel.
External Sensors:
2 Key Features
A precision voltage attenuator with power down facility
LIN 2.1 transceiver
Power-On Reset with programmable reset timeout and brown-
out detection through factory setting
A window Watchdog function in the normal mode and a timeout
Watchdog in the device standby mode as a factory option
Load dump protection (42V) for all battery supplied pins and
Enable pin
Internal reverse polarity protection (up to -27V) for all battery-
sensing pins, and LIN bus pin
Over temperature warning & shutdown functions
Two independent high resolution A/D converters with
programmable over sampling ratio
Current measurement via Shunt resistor (4 ranges)
Battery voltage (internal voltage divider to battery)
ETR and ETS for external temperature sensor (with switchable
current source)
Internal Sensors:
On chip temperature sensor
Internal current sources for functional test of measurement path
and the connection of shunt resistor
3 Applications
The AS8515 is suitable for battery sensors, having shunt current
sensor at minus pole. For lead acid, Li-Ion batteries up to 18V
nominal, 42V over voltage capability.
The device is also ideal as a general purpose sensor interface for
automotive LIN slaves.
Programmable sampling rate up to 4kHz throughput
Programmable gain, low noise amplifier for current channel with
gain stages 5, 25, 40, 100
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AS8515
Datasheet - A p p l i c a t i o n s
VCC
VSUP
MEN
LDO
POR_VSUP
DVDD
AVDD
ETS
ETR
Figure 1. AS8515 Block Diagram
Voltage Channel
Multiplexer,
Current Source
AS8515
Low
Precision
Clock
POR_VCC
LPM
lp_clk
Control
Logic
CHOP_CLK
High
Precision
Clock
CLK
RSHH
hp_clk
Current Channel ADC
PGA
RSHL
VSENSE
To voltage
Channel ADC
DEC
Temperature
Limiter
Voltage Channel ADC
VSENSE_IN
PGA
DEC
VSENSE_GND
VCM
VREF
AVSS
DVSS
INT
SCLK
SDI
SDO
Revision 0.7
CSB
SPI,
Comparator,
Filter Option
Reference
Generator
RESET
CST
EN
Tx
Rx
VSS
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SPI,
Diagnosis,
WWD
LIN
LIN
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AS8515
Datasheet - C o n t e n t s
Contents
1 General Description ..................................................................................................................................................................
1
2 Key Features.............................................................................................................................................................................
1
3 Applications...............................................................................................................................................................................
1
4 Pin Assignments .......................................................................................................................................................................
5
4.1 Pin Descriptions....................................................................................................................................................................................
5
5 Absolute Maximum Ratings ......................................................................................................................................................
7
6 Electrical Characteristics...........................................................................................................................................................
8
6.1 Operating Conditions............................................................................................................................................................................
8
6.2 DC/AC Characteristics for Digital Inputs and Outputs ..........................................................................................................................
8
6.3 System Specifications ........................................................................................................................................................................
7 AS8515 Top Die Overview......................................................................................................................................................
10
11
7.1 Voltage Attenuator ..............................................................................................................................................................................
11
7.2 Voltage Regulators (LDO) ..................................................................................................................................................................
11
7.3 LIN Transceiver ..................................................................................................................................................................................
11
7.4 Temperature Monitor/Limiter...............................................................................................................................................................
11
7.5 VSUP Under-voltage Reset................................................................................................................................................................
12
7.6 Reset ..................................................................................................................................................................................................
12
7.7 VCC Under-voltage Reset ..................................................................................................................................................................
12
7.8 Window Watchdog (WWD) .................................................................................................................................................................
13
7.9 Timeout Watchdog (TWD) ..................................................................................................................................................................
13
7.10 Modes of Operation ..........................................................................................................................................................................
7.10.1
7.10.2
7.10.3
7.10.4
Normal Mode ...........................................................................................................................................................................
Standby Mode..........................................................................................................................................................................
Temporary Shutdown Mode ....................................................................................................................................................
Thermal Shutdown Mode.........................................................................................................................................................
14
15
15
15
15
7.11 Initialization .......................................................................................................................................................................................
16
7.12 Wake-up ...........................................................................................................................................................................................
17
7.12.1 Remote Wake-up Event........................................................................................................................................................... 17
7.13 LIN BUS Transceiver........................................................................................................................................................................
18
7.13.1 Transmit Mode......................................................................................................................................................................... 18
7.13.2 Receive Mode.......................................................................................................................................................................... 18
7.14 Rx and Tx Interface ..........................................................................................................................................................................
19
7.14.1 Input Tx.................................................................................................................................................................................... 19
7.14.2 Output Rx................................................................................................................................................................................. 19
7.15 MODE Input EN................................................................................................................................................................................
20
7.16 Top Die Block Specifications ............................................................................................................................................................
21
7.16.1
7.16.2
7.16.3
7.16.4
7.16.5
7.16.6
Voltage Attenuator ...................................................................................................................................................................
Voltage Regulator (LDO) .........................................................................................................................................................
VCC Power-on-Reset ..............................................................................................................................................................
VSUP Power-on-Reset ............................................................................................................................................................
Window Watchdog Timer.........................................................................................................................................................
LIN Transceiver .......................................................................................................................................................................
7.17 Timing Diagrams ..............................................................................................................................................................................
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22
22
22
23
23
24
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AS8515
Datasheet - C o n t e n t s
7.17.1 Tx Timeout Watchdog.............................................................................................................................................................. 26
7.17.2 Temperature Limiter ................................................................................................................................................................ 26
7.18 Top Die Registers .............................................................................................................................................................................
8 AS8515 Bottom Die Overview ................................................................................................................................................
26
28
8.1 Current Measurement Channel ..........................................................................................................................................................
28
8.2 Voltage/Temperature Measurement Channel .....................................................................................................................................
28
8.3 Digital Implementation of Measurement Path.....................................................................................................................................
29
8.4 Reference-Voltage..............................................................................................................................................................................
29
8.5 Oscillators...........................................................................................................................................................................................
29
8.6 Power-On Reset .................................................................................................................................................................................
29
8.7 Modes of Operation ............................................................................................................................................................................
8.7.1
8.7.2
8.7.3
8.7.4
Normal Mode 1 (NOM1) ............................................................................................................................................................
Normal Mode 2 (NOM2) ............................................................................................................................................................
Standby Mode1 (SBM1) ............................................................................................................................................................
Standby Mode2 (SBM2) ............................................................................................................................................................
8.8 Initialization Sequence at Power ON ..................................................................................................................................................
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
Soft-reset of Device Using Bit D[7] of Reset Register 0x09.......................................................................................................
Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09 .............................................................................
Reconfiguring Gain Setting of PGA ..........................................................................................................................................
Configuring the Device During Normal Mode ............................................................................................................................
Standby Mode - Power Consumption ........................................................................................................................................
8.9 Bottom Die Block Specifications.........................................................................................................................................................
30
31
31
32
33
33
34
35
35
35
36
36
8.9.1 Current Measurement Ranges (across 100µΩ (±5%) shunt resistor) ...................................................................................... 36
8.9.2 System Specifications................................................................................................................................................................ 43
9 4-Wire SPI Interface................................................................................................................................................................
44
9.1 SPI Timing Parameters ......................................................................................................................................................................
9.1.1
9.1.2
9.1.3
9.1.4
SPI Frame..................................................................................................................................................................................
Write Command.........................................................................................................................................................................
Read Command.........................................................................................................................................................................
Timing ........................................................................................................................................................................................
9.2 Bottom Die Registers..........................................................................................................................................................................
44
45
45
46
47
48
10 Application Information .........................................................................................................................................................
60
11 Package Drawings and Markings..........................................................................................................................................
61
12 Ordering Information.............................................................................................................................................................
64
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AS8515
Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
RSHH
EN
RESET
Rx
Tx
CST
INT
32
31
30
29
28
27
26
25
RSHL
1
24
CLK
VREF
2
23
SDI
VCM
3
22
MEN
AVDD
4
21
CHOP_CLK
AVSS
5
20
DVDD
ETR
6
19
DVSS
ETS
7
18
SDO
VSENSE_IN
8
17
SCLK
AS8515
9
VSENSE_GND
10
11
LIN
12
13
VSS VSENSE VSUP
14
15
16
VCC
CSB
4.1 Pin Descriptions
Table 1. Pin Descriptions
Pin Name
Pin Number
Pin Type
RSHL
1
Analog input
Negative differential input for current channel
VREF
2
Analog output
Internal reference voltage to Sigma Delta ADC;
Connect 100nF to AVSS from this pin.
VCM
3
Analog output
Common mode voltage to the internal measurement path;
Connect 100nF to AVSS from this pin.
1
4
Analog input
+3.3V Power-supply; Supplied by LDO output (VCC) in Top die;
Should be shorted to pin 21 (VCC) externally.
2
5
Power supply
0V Power-supply Ground analog
AVDD
AVSS
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Description
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AS8515
Datasheet - P i n A s s i g n m e n t s
Table 1. Pin Descriptions
Pin Name
Pin Number
ETR
6
ETS
7
VSENSE_IN
8
Analog I/O
VSENSE_GND
9
Analog input
LIN
10
Analog I/O
11
Power supply
0V Power-supply Ground analog
VSENSE
12
Analog input
Battery voltage input
Connect 100nF to VSS from this pin.
VSUP
13
Power supply
Supply input from battery (through external reverse polarity
protection device)
-
14
-
15
Analog output
CSB
16
Digital input
Chip select for Bottom die
SCLK
17
Digital input
Clock signal SPI
SDO
VSS
VCC
2
1
Pin Type
Analog input
Description
Voltage channel single ended input
Battery voltage attenuator output and voltage channel input
Input signal for voltage channel (low)
LIN BUS
Regulated 3.3V output supply for loads up to 50mA
18
Digital output
Data signal SDO
2
19
Power supply
0V Power-supply digital
1
20
Analog input
+3.3V Power-supply; Supplied by LDO output (VCC) in Top die;
Should be shorted to pin 21(VCC) externally.
CHOP_CLK
21
Digital output
Chopper clock
MEN
22
Digital I/O
SDI
23
Digital input
CLK
24
Digital I/O
-
25
-
INT
26
Digital output
Interrupt not: Wake-up, digital interrupt, ready flag 2
CST
27
Digital input
Chip select for Top die
Tx
28
Digital input
LIN transceiver transmit pin
Rx
29
Digital output
LIN transceiver receive pin
RESET
30
Digital output
Reset output (open drain)
EN
31
Digital input
Enable input
RSHH
32
Analog input
Positive differential input for current channel
DVSS
DVDD
3
Digital output for Bottom die in SBM mode and input for Top
die
Data signal SDI
Internal/External digital clock signal
-
1. Pin #4, pin #20 and pin #15 needs to be shorted externally on the board. Pin #21 is the LDO output that supplies pin #4 and pin #20.
2. Pin #5, pin #11 and pin #19 needs to be shorted externally on the board as they are the grounds.
3. Use as output port only.
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AS8515
Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 8 is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Min
Typ
Max
Units
Comments
Electrical Parameters
VSUP
Supply voltages
-0.3
42
V
VSENSE
Battery voltage inputs
-27
42
V
AVDD,
DVDD
DC supply voltage
-0.3
5
V
EN
Enable input
-0.3
42
V
VCC
Regulated output supplies
-0.3
5
V
LIN
LIN bus
-27
40
V
VCC generated by Top die must not be larger
than 5V on board level as it has to be
connected with Bottom die AVDD and AVCC
Analog & digital inputs and outputs
-0.3
5
V
Input current (latch-up immunity)
-100
100
mA
Norm: AEC-Q100-004
kV
LIN, VSS
±4
kV
VSUP, VSENSE
±2
kV
All other pins
0.375
W
MLF-32 in still air, soldered on JEDEC
standard board @125º ambient,
static operation = no time limit
40
ºC/W
150
ºC
130
ºC
Electrostatic Discharge
ESD
Electrostatic discharge
Norm: AEC-Q100-002
±6
Continuous Power Dissipation
1
Ptot
Total operating power dissipation
(all supplies and outputs)
Temperature Ranges and Storage Conditions
RΘ
Package thermal resistance
Tstg
Storage temperature
TJ
Junction temperature
TBODY
-55
Package body temperature
Humidity non-condensing
MSL
34
Moisture Sensitive Level
5
260
ºC
85
%
The reflow peak soldering temperature (body
temperature) specified is in accordance with
IPC/JEDEC J-STD-020 “Moisture/Reflow
Sensitivity Classification for Non-Hermetic
Solid State Surface Mount Devices”.
The lead finish for Pb-free leaded packages is
matte tin (100% Sn).
Represents a maximum floor time of 168h
3
1. Total power dissipation cannot exceed 0.375W to avoid increase in junction temperature, i.e. greater than 130ºC. VCC LDO can supply
current externally, which is not greater than 17mA at 18V VSUP and 20mA at 16V VSUP.
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AS8515
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
Unless otherwise noted in this specification, all defined tolerances of parameters are assured over the whole operation conditions range and also
over lifetime.
6.1 Operating Conditions
Table 3. Operating Conditions
Symbol
Parameter
Min
VSUP
Supply voltages
VSENSE
Max
Unit
4.3
18
V
Battery voltage input
4.5
18
V
AVDD
Positive supply voltage
3.15
3.45
V
AVSS
Negative supply voltage
0
V
DVDD
Positive digital supply voltage
3.15
3.45
DVSS
Negative digital supply voltage
0
LIN
LIN bus
0
18
V
EN
Enable input
0
18
V
VCC
Regulated output supply
3.15
3.45
V
TAMB
Ambient temperature
-40
115
ºC
27
mA
ISUP
1
fCLK
Typ
Referring to DVSS, Typical ±10%
V
Supply current
System clock frequency
V
Note
8.192
MHz
Maximum junction temperature (TJ) is 130ºC
When external clock is selected, internal clock
will be 4.096 MHz
1. Total power dissipation cannot exceed 0.375W to avoid increase in junction temperature, i.e. greater than 130ºC. VCC LDO can supply
current externally, which is not greater than 17mA at 18V VSUP and 20mA at 16V VSUP.
6.2 DC/AC Characteristics for Digital Inputs and Outputs
All pull-up, pull-downs have been implemented with active devices. SDO have been measured with 10pF load.
INT Output.
Table 4. INT
Symbol
Parameter
Condition
Min
Typ
Max
VOH
High level output voltage
VOL
Low level output voltage
0.4
V
IO
Output current
4
mA
Max
Unit
2.5
Unit
V
CST, CSB, TxD.
Table 5. CST, CSB
Symbol
Parameter
VIH
High level input voltage
VIL
Low level input voltage
ILEAK
Input leakage current
IPU
Pull-up current
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Condition
Min
Typ
0.8*VCC
V
0.2*VCC
Pulled to GND
Revision 0.7
V
-1
+1
µA
-150
-10
µA
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AS8515
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
SDI, SCLK.
Table 6. SDI, SCLK
Symbol
Parameter
VIH
High level input voltage
VIL
Low level input voltage
ILEAK
Input leakage current
Condition
Min
Typ
Max
0.8*VCC
Unit
V
-1
0.2*VCC
V
+1
µA
Max
Unit
SDO Output.
Table 7. SDO
Symbol
Parameter
Condition
Min
Typ
VOH
High level output voltage
VOL
Low level output voltage
0.4
V
IO
Output current
4
mA
Max
Units
2.5
V
CHOP_CLK Output.
Table 8. CHOP_CLK
Symbol
Parameter
Conditions
Min
Typ
VOH
High level output voltage
VOL
Low level output voltage
0.4
V
IO
Output current
4
mA
Max
Units
2.5
V
EN Input.
Table 9. EN
Symbol
Parameter
Conditions
VIH
High level input voltage
VIL
Low level input voltage
ILEAK
Input leakage current
EN = VSS
Ipd_en
Pull-down current
Pulled up to VCC
Min
Typ
0.8*VCC
V
0.2*VCC
V
-1
+1
µA
30
100
µA
Max
Unit
CLK I/O.
Table 10. CLK I/O
Symbol
Parameter
VIH
High level input voltage
VIL
Low level input voltage
Condition
Min
Typ
2.4
V
1
V
ILEAK
Input leakage current
-1
+1
µA
IPD_EN
Pull-down current
10
100
µA
IO
Output current
4
mA
VOH
High level output voltage
VOL
Low level output voltage
0.4
V
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AS8515
Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
MEN Output.
Table 11. MEN
Symbol
Parameter
Conditions
Min
Typ
Max
VOH
High level output voltage
VOL
Low level output voltage
0.4
V
IO
Output current
2
mA
Max
Units
2.5
Units
V
Rx Output.
Table 12. Rx
Symbol
Parameter
Conditions
Min
Typ
VOH
High level output voltage
VOL
Low level output voltage
VSS+0.4
V
IO
Output Current
1
mA
Ipu_reset
Pull-up current
Pulled down to VSS
-30
-100
µA
Symbol
Parameter
Conditions
Min
Max
Units
VOH
High level output voltage
VOL
Low level output voltage
IO
Output current
VCC-0.5
V
RESET Output.
Table 13. RESET
Typ
2.5
V
Open Drain Pull-down
0.4
V
8
mA
Max
Unit
7
mA
6.3 System Specifications
Table 14. System Specifications
Symbol
Parameter
Condition
Ivsupnom
Current consumption in normal mode
No load on VCC, LIN bus in dominant
state
Ivsupstdby
Current consumption standby
No load on VCC,
LIN bus in recessive state
Min
Typ
80
µA
Note: Stand by mode power consumption is sum of stop mode power consumption and average of normal mode power consumption over a
period of 2s (NOM1 time of device is low in Standby mode).
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AS8515
Datasheet - A S 8 5 1 5 To p D i e O v e r v i e w
7 AS8515 Top Die Overview
The AS8515 Top die consists of a resistive divider, a low dropout regulator, and a LIN bus transceiver. Additionally integrated are a RESET unit
with a power-on-reset delay, programmable window watchdog and timeout watchdog timers as a factory programming option. It also includes a
watchdog timeout on LIN Tx node to indicate if the Microcontroller is stuck in a loop and the LIN bus remains in dominant time for more than the
necessary time.
7.1 Voltage Attenuator
A resistive divider is used as a battery voltage attenuator. Like the amplifier, the attenuator can be enabled or disabled through SPI, and in the
device standby mode, we additionally need logic high on MEN pin for enabling. Internal reverse polarity protection is provided for VSENSE pin.
Figure 3. Attenuator Implementation
VSENSE
PD
VSENSE_IN
VSENSE_GND
7.2 Voltage Regulators (LDO)
The device has a low-dropout voltage regulator named LDO, 3.3V voltage outputs. The output of the LDO is VCC. The regulator is always ON
except when the device enters the over-temperature shutdown.
The regulator has in-built short-circuit current limitation feature. The regulator can be temporarily shut down for hard reset of the external circuitry
by configuring the device to temporary shutdown mode through SPI.
The LDO power-up happens when the POR-VSUP event occurs (RESET_VSUP_N switching from low to high). The LDO will be switched off if
there is an under voltage on VCC, that is, when RESET_VCC_N switches back to low.
7.3 LIN Transceiver
The device has a LIN transceiver with slew-controlled bus driver for controlling the electromagnetic emissions from the LIN bus. Further, the slew
rate is independent of the bus load. The transmitter relays the data from the LIN controller (Tx pin) to the bus (LIN pin), and the receiver provides
the data on the bus to the controller (Rx pin). The transceiver conforms to the LIN 2.1 standard.
The LIN transceiver has a timeout watchdog for Tx. After the timeout, the LIN bus will be released to the recessive state from the dominant state.
The bus driver has an in-built short-circuit current limitation facility to protect the device from damage when there is a short between the bus and
the supply. In addition to the data receiver, there is a low-power receiver active in the device standby mode which received a wake-up event from
the LIN bus to bring the device to normal mode.
7.4 Temperature Monitor/Limiter
The temperature limiter circuit powers down the device when the junction temperature exceeds 170°C (nominal). It also issues an overtemperature warning at 160°C (nominal). The device is powered up again when the junction temperature falls below 140°C (nominal). The overtemperature warning flag is also cleared at this temperature.
The temperature limiter circuit can be optionally disabled through SPI.
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AS8515
Datasheet - A S 8 5 1 5 To p D i e O v e r v i e w
7.5 VSUP Under-voltage Reset
When VSUP drops below VSUVR_ON, the RESET_VSUP_N switches back to low level. This is treated as a master reset and will have the
highest priority over all other signals. In this case, the regulators, LIN transceiver, and all other blocks are shut off, and the device comes to a
complete stop. The device returns to the normal mode when VSUP rises over VSUVR_OFF again irrespective of the mode it was in prior to this
under-voltage condition.
7.6 Reset
RESET module generates an active-low reset signal for the external circuitry supplied by VCC. The behavior of the reset output is depicted in
Figure 4 in different cases. As shown, RESET signal is affected by an under-voltage condition on VCC and Watchdogs which are described in
detail in the subsequent sections.
The reset period can be one-time programmed to 4, 16 and 32 ms with a default value of 8 ms.
Figure 4. Reset Functionality
VSUP
T>Tj
VCC
T<Tj
t<trr
VUVR_OFF
VUVR_ON
tRes
tRes
tRes
tRes
trr
tRes
RESET
Start-up
Over-temp
Shutdown
Glitch in
VSUP
VSUP UV
Reset by
Watchdog
SC Current
Limitation Active
7.7 VCC Under-voltage Reset
When VCC drops below VUVR_ON, the RESET_VCC_N switches back to low level. This event generates a reset output. The reset output is
released again only a reset period (tRes) later after VCC rises above VUVR_OFF. If the time difference between the VCC falling below VUVR_ON
and rising above VUVR_OFF is less than trr, there will be no reset output. The reset output is affected in the conditions like over-temperature
shutdown and temporary shutdown only through VCC under voltage.
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AS8515
Datasheet - A S 8 5 1 5 To p D i e O v e r v i e w
7.8 Window Watchdog (WWD)
The Window Watchdog ensures that the Microcontroller is properly functioning in the normal mode of the device. The Watchdog is started after a
reset and the Microcontroller needs to send a trigger in the window of WD_TSV (service time). If the trigger occurs early, in the period WD_TCL,
or after WD_TSV, a reset output is generated.
The Microcontroller can access the trigger bit for the watchdog through SPI. The WWD can be enabled and the window times can be
programmed through factory setting and enabled as a factory option.
Figure 5. Window Watchdog Functionality
Period
Non-Service time (WD_TCL)
Service time (WD_TSV)
50 %
100 %
Trigger
restart
period
Trigger
via SPI
Last trigger
Earliest point for
correct trigger
(No RESET)
Latest point for
correct trigger
(No RESET)
Correct trigger
(No RESET)
Wrong trigger
(RESET generation)
Wrong trigger
(RESET generation)
7.9 Timeout Watchdog (TWD)
The Timeout Watchdog ensures that the Microcontroller is in proper functional state in the device standby mode. The Watchdog timer will be
started upon a rising edge on INT and will generate a reset output if the Microcontroller doesn’t send a trigger before the timeout.
The Microcontroller can access the trigger bit for the watchdog through SPI. The TWD can be enabled by factory setting and the timeout interval
can be programmed through SPI.
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7.10 Modes of Operation
The AS8515 Top die provides the following four main operating modes:
Normal Mode
Standby Mode
Temporary Shutdown Mode
Thermal Shutdown Mode
The LIN transceiver can be programmed to operate with lower slew in the normal mode. See Figure 6 for a detailed state transition diagram. Soft
states like “TxWD Wait”, “Standby Wait”, and other wait states have also been included in the state diagram for completeness.
Figure 6. Finite State Machine Model of AS8515 Top Die
INIT0
por_vsup
! temp170
OVTEMP
OTP LOAD
otp_load
temp170
128msec
temp170
RESET TIMEOUT
Temp Shut
T
shu emp
tdo
wn
! por_vcc ||
wwdtimeout
Temp shutdown
test_en
STANDBY WAIT
otp
_en
TX=1
WAIT_OTP
al_
wa
it
Rwake / local wake
rwa
ke_
wa
it /
loc
sh
Temp
! por_vcc ||
stdby_timeout
own
u td
n
utdow
STANDBY
RX=0
RX
=0
p sh
Te m
temp170
by
and
! st
Txwd_timeout
y&
ndb e
Sta _mod
p
t
~o
WAIT_TEST
NORMAL
Standby &
otp_mode
temp170
temp170
reset
timeout
! por_vcc ||
wwdtimeout
TXWD WAIT
! por_vcc ||
stdby_timeout
temp170
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Table 15. Transition Table
Transition
From Mode
Interface
To Mode
LIN
Rx
Stand-By
X-RS
X-H
Temporary
Shutdown
X-RS
X-H
OverTemperature
X-RS
X-H
Normal (LW)
X
H-X
Normal (RW)
X
H-X
Temporary
Shutdown
RS
H
1
OverTemperature
RS
H
1
Temporary
Shutdown
Mode
Normal
RS-X
H-X
Overtemperature
Mode
Normal
RS-X
All States
Power Off
X
Normal Mode
Standby Mode
Tx
EN
2
H-L
1
X
H
1
X
X
1
X
L-H
H
Reg.
0x05
D0
Flags
Rwake UVSENSE
OT
UVCC
Comments
X
X
inactive
inactive
Tx is high for
TSTNDY_trigger
H
X
X
inactive
set
The Control Bit is set
through the 4-Wire SPI
interface
L
X
X
set
set
Temperature monitor
output asserted
(covered by scan)
L
X
X
inactive
inactive
X
L
set
X
inactive
Wake up Event
inactive Remote
occurred on LIN
H
L
H
X
X
inactive
set
The Control bit is set
through the 4-Wire SPI
interface
H
L
L
X
X
set
set
Temperature monitor
output asserted
(covered by scan)
1
X
X
L
X
X
inactive
clear
Internal 128ms timer
expired
H-X
1
X
X
L
X
X
clear
clear
Temperature monitor
output de-asserted
(covered by scan)
X
X
X
X
X
L-H
X
X
1
1
H
2
L
2
2
2
2
1. Effect of transition
2. Cause for transition
Note: L = Low state, H = High state, OT = Over temperature Reset, UVCC = Under-voltage VCC, UVSENSE = Under-voltage VSENSE,
Rwake = Remote wake, X = don’t care.
7.10.1 Normal Mode
This is the mode after the power-up. In this mode, voltage regulator, LIN transceiver, window Watchdog is all active. The resistive divider can be
enabled through SPI. LIN transceiver is capable of sending the Tx data from microcontroller to the LIN bus at a maximum rate of 20Kbps.
7.10.2 Standby Mode
Standby Mode is a functional low power mode and is entered by pulling EN to ground. The LIN transceiver, resistive divider, window watchdog,
and Tx timeout watchdog circuits are disabled. But, it is possible to selectively enable the voltage and current measurement paths in this mode
using an externally generated measurement enable (MEN) signal on the MEN pin. The timeout Watchdog can be enabled in this mode to make
sure that the Microcontroller is active.
7.10.3 Temporary Shutdown Mode
In this mode, the regulator is powered down and the VCC is pulled down. This provides an alternative way to reset those components powered
by AS8515. The feature has to be enabled by the factory programming option and can be invoked through SPI. The LIN transceiver along with
the LIN wake-up circuits are powered down. No remote wake functionality possible. LIN bus enters into recessive state. The system goes out of
this mode to normal mode after the timeout of an internal timer.
7.10.4 Thermal Shutdown Mode
If the junction temperature TJ is higher than Tsd, the device will be switched into the thermal shutdown mode. The regulator and the transceiver
are completely disabled. Only the over-temperature monitor is active. As soon as the temperature returns back to TRET, the system enters
normal mode.
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7.11 Initialization
When the power supply is switched on, when VSUP > VSUVR_OFF, RESET_VSUP_N becomes high. This starts the regulator LDO with 3.3V
and Vuvr_off option of 2.75V. When VCC > Vuvr_off (2.75V), active-low PORN_2_OTP is generated. The rising edge of PORN_2_OTP loads
contents of fuse onto the factory setting latch after load access time TLoad. LOAD_OTP_IN_PREREG signal loads contents of factory setting
latch onto a register. This register provides the actual settings of LDO, Vuvr_off and Reset Timeout period TRes. This is done as the factory
setting block is powered by the VCC. If VCC > Vuvr_off (phase 2), Reset timeout is restarted. RESET signal is de-asserted after Reset Timeout
period TRes (phase 2) and then device enters into normal mode. The circuit also needs to initialize correctly for very slow ramp rates on VSUP (of
the order of 0.5V/min).
Figure 7. Initialization Sequence
VSUP_POR_Threshold
VSUP
RESET_VSUP_N
LDO Off
Device Settings
PHASE 1
PHASE 2
LDO On
VCC Por Threshold = 2.75V
LDO setting = 3.3V
Reset Timeout = 4msec
LDO On
VCC Por Threshold = from OTP Block
LDO setting = from OTP Block
Reset Timeout = from OTP Block
LDO settings to 5 V
LDO settings to 3.3 V
VCC_POR_Threshold
VCC
RESET_VCC_N
PORN_2_OT
P
6 Cycles of
RC-Oscillator
LOAD_OTP_IN_PREREG
RESET
If Phase 1 POR threshold != Phase 2 POR threshold
Tres = Reset Timeout from OTP Block
If Phase 1 POR threshold == Phase 2 POR threshold
Tres = Reset Timeout from OTP Block
Table 16. VSUP>Vsuvr_on and VCC<Vuvr_on
Block
Output Signal
TRANSCEIVER=Enabled (disabled only during initial VSUP ramp-up)
LIN=high-z, Rx=follows VCC…
LDO=Enabled (disabled only during initial ramp-up)
VCC=low…
RESET BLOCK=Enabled
RESET=high-z…
RESISTIVE DIVIDER=Enabled
VSENSE=high…, VSENSE_DIV=enabled
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Table 17. VSUP<Vsuvr_on
Block
Output Signal
TRANSCEIVER=Disabled
LIN=high-z, Rx=high-z…
LDO=Disabled
VCC=low
RESET BLOCK=Disabled
RESET=high-z
RESISTIVE DIVIDER=Disabled
VSENSE=high, VSENSE_DIV=low
7.12 Wake-up
When the device enters standby mode, it can be brought back to the normal mode. A dominant state on the BUS for duration of tWAKE (see Table
25) will result in the device wake-up which is termed as remote wake.
7.12.1 Remote Wake-up Event
In all low power modes of Top die, low power BUS receiver is ON. If BUS is in dominant state for longer than tWAKE then, remote wake is
sensed on the BUS and REMOTE_WAKE_flag is set. Indication of wake-up is given to µC by setting a bit in interrupt register and giving interrupt
on INTN pin.
Figure 8. Remote Wake-up Event
BUS
>Twake
REMOTE_WAKE_flag
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Remote wake detected
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AS8515
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7.13 LIN BUS Transceiver
The AS8515 has an integrated bi-directional bus interface device for data transfer between LIN bus and the LIN protocol controller. The
transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage comparator followed
by a de-bouncing unit.
7.13.1 Transmit Mode
During transmission the data at the pin Tx will be transferred to the BUS driver to generate a bus signal. To minimize the electromagnetic
emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit.
Transmitting will be interrupted in the following cases:
Thermal Shutdown active
Master Reset (VSUP < Vsuvr_on)
The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode This diode prevents the reverse
current of VBUS during differential voltage between VSUP and BUS (VBUS>VSUP). No additional termination resistor is necessary to use the
AS8515 in LIN slave nodes. If this IC is used for LIN master nodes it is necessary that the BUS pin is terminated via an external 1kΩ resistor in
series with a diode to VSENSE.
7.13.2 Receive Mode
The data signals from the BUS pin will be transferred continuously to the pin Rx. Short spikes on the bus signal are suppressed by the
implemented debouncing circuit. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and 0.6*VSUP will be securely
observed.
Figure 9. Receive Mode Impulse Diagram
Vthr_max
60%
BUS
Vthr_hys
Vthr_cnt
50%
40%
Vthr_min
t < tdeb_BUS
t < tdeb_BUS
Rx
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7.14 Rx and Tx Interface
7.14.1 Input Tx
The 3.3V input Tx controls directly the BUS level. LIN Transmitter acts like a slew-controlled level shifter. A dominant state (low) on Tx leads to
the LIN bus being pulled low (dominant state) too. The Tx pin has an internal active pull up connected to VCC. This guarantees that an open Tx
pin generates a recessive BUS level.
Figure 10. Tx Interface
MCU
AS8515
VCC
VCC
IPU_TxD
Tx
RC-Filter
(10ns)
7.14.2 Output Rx
The received BUS signal will be output to the Rx pin:
BUS < Vthr_cnt – 0.5 * Vthr_hys → Rx = low
BUS > Vthr_cnt + 0.5 * Vthr_hys → Rx = high
This output is a push-pull driver between VCC and GND with an output current of 1mA
Figure 11. Rx Interface
AS8515
MCU
VCC
Rx
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7.15 MODE Input EN
The AS8515 Top die is switched from normal mode to the standby mode with a falling edge on EN and keeping Tx high for TSTNDY_trigger time.
Device is switched from standby mode to normal mode with a rising edge at the EN pin. The mode change for Top die with a falling edge on EN
can be done independently from the state of the transceiver bus. This ensures the direct control of device to enter into standby mode by
microcontroller using EN pin.
Figure 12. EN Pin Functionality
EN
Tx
Ttx_su
Normal Mode
TSTNDY_trigger
Ttx_hd
Standby/Sleep
Mode
Normal
Mode
The EN input has an internal active pull down to secure that if this pin is not connected, a low level will be generated.
Figure 13. Enable Interface
CLOAD
EN
VCC
+
+3.3V
VBAT
CIN
RESET
VSUP
LIN
VSS
AS8515
+
Tx
Rx
MCU
VSENSE
If the application doesn’t need the low-power modes of the device, a direct connection of EN to VCC is possible. In this case the Top die
operates in permanent normal mode. Also possible is the external (outside of the module) control of the EN line via VSUP signal as shown
below.
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Figure 14. EN Connection for Permanent Normal Mode
CLOAD
EN
VCC
+
+3.3V
VBAT
CIN
RESET
VSUP
LIN
VSS
AS8515
+
Tx
MCU
Rx
7.16 Top Die Block Specifications
This section provides specification of design related key parameters.
7.16.1 Voltage Attenuator
Table 18. Voltage Attenuator
Symbol
Parameter
RDIV
Division ratio
VSENSE
Input voltage range/
Battery voltage range
εp,RDIV
Ratio error
Condition
Min
Typ
4.5
12
At room temperature, VSENSE=12V
Temperature: -25 to +65º @VSENSE=12V
Maximum values will be added after device
evaluation (to be guaranteed by evaluation)
±0.05
εdt2,RDIV
Temperature: -40 to +125º @VSENSE=12V
Maximum values will be added after device
evaluation (to be guaranteed by evaluation)
±0.2
εdv1,RDIV
VSENSE: 11V to 13V @Temperature=27º
Maximum values will be added after device
evaluation (to be guaranteed by evaluation)
±0.05
VSENSE: 6V to 18V @Temperature=27º
Maximum values will be added after device
evaluation (to be guaranteed by evaluation)
±0.2
εdt1,RDIV
Ratio drift
(with reference to Temperature)
Ratio drift
(with reference to VSENSE)
εdv2,RDIV
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Max
21
Revision 0.7
Unit
V/V
18
V
±1
%
%
%
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AS8515
Datasheet - A S 8 5 1 5 To p D i e O v e r v i e w
7.16.2 Voltage Regulator (LDO)
Table 19. Voltage Regulator
Symbol
Parameter
VSUP
Min
Typ
Max
Unit
Input Supply Voltage
4.3
12
18
V
VCC
Output Voltage Range
3.15
3.3
3.45
V
ILOAD
LDO Load Current
45
mA
ICC_SH
Output Short Circuit Current
Normal mode
250
mA
dVCC1
Line Regulation
ΔVCC / ΔVSUP for VSUP range
8
mV/V
LOREG
Load Regulation
ΔVCC / ΔICCn
(0.5mA < ILOAD < 50mA)
1
mV/mA
Output Capacitor 1 LDO
Electrolytic
2.2
10
μF
1
10
Ω
Output Capacitor 2 LDO
Ceramic
100
220
nF
CL1
ESR1
CL2
ESR2
CSUP1E
ESR1_CSUP
CSUP2C
ESR2_CSUP
Condition
Input capacitor (Electrolytic)
For EMC suppression
Input capacitor (Ceramic)
0.02
1
W
22
100
μF
1
10
Ω
100
220
nF
0.02
1
Ω
Max
Unit
7.16.3 VCC Power-on-Reset
Table 20. VCC
Symbol
Parameter
Condition
Min
Typ
Vuvr_off
VCC under-voltage threshold OFF
Rising edge of VCC
2.55
2.95
V
Vuvr_on
VCC under voltage threshold ON
Falling edge of VCC
2.3
2.7
V
Vhyst_vcc
Hysteresis of under-voltage threshold
on/off VCC
0.1
0.25
0.4
V
Condition
Min
Typ
Max
Unit
7.16.4 VSUP Power-on-Reset
Table 21. VSUP
Symbol
Parameter
Vsuvr_off
VSUP under-voltage threshold OFF
Rising edge of VSUP
4.8
5.1
5.4
V
Vsuvr_on
VSUP under-voltage threshold ON
Falling edge of VSUP
3.5
3.8
4.1
V
Vhyst_VSUP
Hysteresis of VSUP under-voltage
1.5
V
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7.16.5 Window Watchdog Timer
Table 22. WWD
Symbol
WD_TCL
WD_TSV
WD_TCL1
WD_TSV1
WD_TCL2
WD_TSV2
WD_TCL3
WD_TSV3
WD_TCL4
WD_TSV4
WD_TCL5
WD_TSV5
Parameter
Condition
Min
Typ
Max
Unit
Factory
setting 1
WWD non-service time
RESET will be generated
0-100
ms
WWD Service time
RESET will not be generated
100-200
ms
Factory
setting 2
WWD non-service time
RESET will be generated
0-80
ms
WWD Service time
RESET will not be generated
80-160
ms
Factory
setting 3
WWD non-service time
RESET will be generated
0-60
ms
WWD Service time
RESET will not be generated
60-120
ms
Factory
setting 4
WWD non-service time
RESET will be generated
0-200
ms
WWD Service time
RESET will not be generated
200-400
ms
Factory
setting 5
WWD non-service time
RESET will be generated
0-160
ms
WWD Service time
RESET will not be generated
160-320
ms
Factory
setting 6
WWD non-service time
RESET will be generated
0-120
ms
WWD Service time
RESET will not be generated
120-240
ms
7.16.6 LIN Transceiver
DC Electrical Characteristics.
Table 23. Driver
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Ibus_lim
Current limitation in dominant state
LIN = VSUP_max
40
120
200
mA
LIN_VOL
Output Voltage BUS (dominant state),
ILIN = 40mA
(short-circuit condition tested at VOL=2.5V)
2
V
Pull-up resistor
Normal mode
(recessive BUS level on Tx pin)
60
KΩ
Ibus_leak_rec
Driver OFF; 7.3V < VSUP < 18;
8V < VBAT < 18,
VSUP < VBUS < 1.08 * VSUP
(to be tested at VBUS = 18V)
20
µA
Max
Unit
20
40
Table 24. Receiver
Symbol
Parameter
Condition
Min
Ibus_leak_dom
Input Leakage current at receiver
Driver OFF;
VBUS = 0V; VSUP = 12V; VCC = 3.3V
-1
Ibus_no_GND
VSS = VSUP; VSUP = 12V;
0V < VBUS < 18V, VCC = 3.3V
(to be tested at VBUS = 18V)
-1
Ibus_no_bat
VSUP = VSS; 0V < VBUS < 18V,
VCC = VSS
(to be tested at VBUS = 18V)
Vbus_dom
Vbus_rec
Typ
mA
1
mA
100
µA
0.4
VSUP
0.6
Vbus_cnt
Vbus_cnt = (Vth_dom + Vth_rec)/2
Vhys
Vhys = (Vth_dom – Vth_rec)
1
1
VSUP
0.475
0.525
VSUP
0.05
0.175
VSUP
1. Vth_dom : Receiver threshold of the recessive to dominant LIN bus edge
Vth_rec : Receiver threshold of the dominant to recessive LIN bus edge
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AC Electrical Characteristics.
LIN Driver, Bus load conditions (CBUS ; RBUS): 1nF; 1kΩ / 6, 8nF; 660Ω / 10nF; 500Ω
Table 25. LIN Driver
Symbol
Parameter
Condition
Min
(worst case 20Kbps transmission)
Vth_rec(max) = 0.744 x VSUP;
Vth_dom(max) = 0.581 x VSUP;
VSUP = 6.0V...18V; tbit = 50µs;
D1 = tbus_rec(min) / (2 x tbit)
0.396
(worst case 20kbps transmission)
Vth_rec (min) = 0.422 x VSUP;
Vth_dom (min) = 0.284 x VSUP;
VSUP = 6V...18V; tbit = 50µs;
D2 = tbus_rec(max) / (2 x tbit)
(worst case 10.4kbps transmission)
Vth_rec (max) = 0.778 x VSUP;
Vth_dom (max) = 0.616 x VSUP;
VSUP = 6.0V...18V; tbit = 96µs;
D3 = tbus_rec(min) / (2 x tbit)
(worst case 10.4kbps transmission)
Vth_rec (min) = 0.389 x VSUP;
Vth_dom (min) = 0.251 x VSUP;
VSUP = 6V...18V; tbit = 96µs;
D4 = tbus_rec(max) / (2 x tbit)
0.59
tdLR
VCC = 3.3V;
Propagation delay bus dominant to Rx LOW
6
µs
tdHR
VCC = 3.3V;
Propagation delay bus dominant to Rx HIGH
6
µs
tRS
Receiver delay symmetry
-2
2
µs
tWAKE
Dominant time for wake-up via LIN bus
30
150
µs
tsln
Transition from standby mode to normal
mode (clock frequency is 128KHz ±25%)
4
Clock
cycles
tnsl
Transition from normal mode to standby
mode (clock frequency is 128KHz ±25%)
6
Clock
cycles
trec_deb
Receiver de-bounce time
Cint
Internal capacitance of the LIN node
configured as a slave with a 180pF cap on
the LIN bus
D1
D2
D3
D4
Typ
Max
Unit
0.581
0.417
0.6
220
3
µs
250
pF
7.17 Timing Diagrams
Figure 15. Timing Diagram for Propagation Delays
TxD
50%
t df_TXD
t dr_TXD
V BUS
100
%
95%
BUS
50%
50%
5%
0%
t df_RXD
RxD
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t dr_RXD
50%
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Figure 16. Timing Diagram for Duty Cycle According to LIN 2.1 and J2602
tBit
tBit
TxD
tx_dom_max
tx_rec_max
tx_dom_min
VSUP
t x_rec_min
trec(min)
100
%
tdom(max)
BUS
t dom(min)
58.1%
61.6%
74.4%
77.8%
42.2%
38.9%
28.4%
25.1%
V SS
58.1%
61.6%
trec(max)
28.4%
25.1%
0%
tbit
tbit
TxD
tbus_dom(max)
tbus_rec(min)
tbus_dom(min)
tbus_rec(max)
LIN
Vth_rec(max)
Vth_dom(max)
Vth_rec(min)
Vth_dom(min)
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7.17.1 Tx Timeout Watchdog
Table 26. Tx Timeout Watchdog
Symbol
Parameter
Conditions
tlin_wdog
Timeout period for the dominant state
Min
Typ
Max
Units
0.5
1
2
s
Min
Typ
Max
Units
155
170
185
ºC
142
157
172
ºC
125
140
155
ºC
7.17.2 Temperature Limiter
Table 27. Temperature Limiter
Symbol
Parameter
Tsd
Shut down temperature
Totset
Over-temperature warning
Tret
Return temperature
Conditions
Junction temperature
7.18 Top Die Registers
The serial interface can be used for communication between AS8515 and an external microcontroller. The device is only a slave and the
microcontroller has to initiate the communication. The device can be configured by writing into the control registers and the diagnostic
information can be read out from the diagnostic registers. Pin CST is used as chip select for SPI communication.
A total of 32 registers, each of 8-bits which include configuration, diagnostic, and backup are available. The registers can be accessed using the
4-wire serial interface. Table 28 provides a description of all AS8515 Top die registers.
Table 28. AS8515 Top Die Registers
Address
Register Name
Default Value
R/W
Description
Configuration and Control Registers
0x00
Reserved
0x01
Reserved
0x02
Reserved
0x03
Device
Configuration
Register
On POR_VCC
0000_1100
R/W
D0 Reserved
D1 Voltage Attenuator Enable Bit.
0 Disabled, 1 Enabled
D2 Enable/Disable Over Temperature Monitor
0 Disabled, 1 Enabled
D3 Enable/Disable LIN Transceiver
0 Disabled, 1 Enabled
D4 Reserved
D5-D7 Reserved
0x04
Device Control
Register
On POR_VSUP
0000_0001
R/W
D0 High-slew / Low-slew control
1 High-slew, 0 Low-slew
D1-D7 Reserved
0x05
Temporary
Shutdown
Register
On POR_VCC
0000_0000
R/W
D0 Temporary shutdown control bit
1 Enter temporary shutdown
D1-D7 Reserved
0x06
Window Watch
Dog Trigger
Register
0x07
Reserved
0x0A
Reserved
0x0B
Reserved
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On POR_VCC
0000_0000
W
D0 Window Watchdog trigger bit
D1 Timeout Watchdog trigger bit
Upon a trigger, the bit will be cleared within 2 internal clock cycles.
D2-D7 Reserved
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Datasheet - A S 8 5 1 5 To p D i e O v e r v i e w
Table 28. AS8515 Top Die Registers
Address
Register Name
0x0C
Reserved
0x0D
Reserved
0x0E
Default Value
Watchdog Timer On POR_VCC
Control Register
0000_0000
0x0F
R/W
Description
R/W
D0 Timer resolution
0 1 second, 1 32 seconds
D1-D7 Timeout period.
If D0=1, then timeout period = D[7:1]*64*0.512 seconds, else timeout period
= D[7:1]*0.512 seconds
Reserved
Diagnostic Registers
0x08
0x09
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Diagnostic
Register-1
Diagnostic
Register-2
On POR_VSUP
0000_0011
On POR_VSUP
0000_0000
R
D7-D0 = DR[7:0], 8-LSB bits of the 24-bit Diagnostic Register.
D0 POR-VSUP
Set when VSUP < Vsuvr_on, cleared after µC read
D1 Under voltage VCC (UVVCC)
Set when VCC < Vuvr_on, cleared after µC read
D2 Over-temperature Reset (OTEMP170)
Set when temp > Tsd, cleared after µC read
D3 Over-temperature warning (OTEMP160)
Set when temp > Totset, cleared after µC read
D4 Overvoltage VSENSE (OVVSENSE)
Set when VSUP > Vovthh, cleared after µC read
D5 Reserved
D6 Remote wakeup (RWAKE)
Set on remote wakeup event on LIN Bus, cleared after µC read
D7 Set on failure of window Watchdog trigger, cleared after µC read
R
D7-D0 = DR[15:8], Next 8-LSB bits of the 24-bit Diagnostic Register.
D0 Tx timeout of 1sec (TXTIMEOUT)
Set on Tx low > 1sec, cleared after µC read
D1 TEMPSHUT
This bit is set on entering temporary shutdown state and cleared after µC read.
D2 Set on failure of timeout Watchdog trigger, cleared after µC read
D3 Load Dump Flag
D7-D4 Reserved
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Datasheet - A S 8 5 1 5 B o t t o m D i e O v e r v i e w
8 AS8515 Bottom Die Overview
The AS8515 Bottom die consists of two independent high resolution 16-bit SD analog to digital conversion channels. The measurement path
of these two channels integrates a programmable gain amplifier, chopper and de-chopper, sigma-delta modulator, decimator and a digital filter
for simultaneous measurement of Current and Voltage/Temperature.
The two measurement channels, namely the Current and Voltage/Temperature measurement channels have identical data path.
The input signal is amplified in the Programmable Gain Amplifier (PGA) with any of the selected gains of 1, 5, 25, 40 and 100 facilitating
measurement of a wide range of Current, voltage and temperature levels. Gain Settings for different input ranges and any associated restrictions
are explained in the Table 30.
Offset in the measurement path is minimized with the use of a chopper and a de-chopper at appropriate stages in the data path. By default the
chopper/de-chopper is ON in the measurement path. It may be disabled by programming the appropriate register.
The amplified input signal is converted into a single-bit pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass
filter filters out the quantization noise and generates 16-bit data corresponding to the input signal. The decimation ratios of 64, 128 may be
selected in the first filter stage. For reducing data rate further, the second stage decimation can be used.
An optional FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.
8.1 Current Measurement Channel
The voltage across a Shunt Resistor, connected in series with the Battery negative terminal, forms the input signal to the Current Measurement
channel. RSHH and RSHL are the Current measurement input pins. Offset in the input signal is nullified with the use of a chopper and a dechopper at appropriate stages in the data path. The programmable gain amplifier in the data path with programmable settings of 1, 5, 25, 40 and
100 enables measurement of current ranges from ±1A to ±1500A on a 100µΩ shunt. The sampled input signal is converted into a single-bit
pulse-density modulated stream by the Σ-Δ Modulator. A decimator acting as a low-pass filter filters out the quantization noise and generates 16bit data equivalent to the input current signal. The programmable input sampling rate and the decimation ratio determine the output data rates.
The data path can be programmed to provide sub 1Hz to 4kHz rates in the various modes available. An optional FIR filter specifically designed
for 1KHz sample rate is provided to offer matched low pass filter response typically required in lead acid battery sensor systems.
After enabling the current measurement channel, the delay for the availability of the first sample is two conversion cycles.
8.2 Voltage/Temperature Measurement Channel
The other two parameters of the Battery for measurement are Voltage and its Temperature. The second channel accepts signals from four
independent sources through a Multiplexer as listed below:
An attenuator battery voltage obtained through internal resistor divider from
Top die, (or)
A signal from the external temperature sensor, (or)
A signal from external reference, (or)
A signal from the internal temperature sensor.
Apart from this difference in the multiplexing of four input signals, the rest of the data path is identical to the Current measurement channel.
RSHH and RSHL are the Current measurement input pins.
The Battery Voltage which can go up to 18V is attenuated through a Resistor Divider externally and is applied to the Voltage Channel. For
Automotive Battery measurement, the PGA is to be bypassed to connect battery voltage attenuated by a factor of 21 directly to the ADC input.
The latency for the first result from the voltage measurement channel is two conversion cycles.
A second option on this measurement channel is to measure Temperature. Internally generated constant current is pumped through the
Temperature Sensor with positive temperature coefficient, and, a high- precision resistor. The voltages across the sensor and the resistor form
the inputs to the measurement channel one at a time. The difference between the two voltages which is independent of the magnitude of the
current is used to determine the temperature accurately. The voltage across the sensor is applied between the ETS and VSS pins and, the
voltage across the high-precision resistor is applied between ETR and VSS. External temperature measurement involves the acquisition of two
signals one after the other using the same constant current source. The latency for the first result from the temperature measurement channel is
two conversion cycles.
A third option on the measurement channel is to measure the internal temperature. Hence, one of the three options for measurement of Battery
Voltage, External Temperature and, internal temperature may be carried out by selection of appropriate inputs through the internal multiplexer
selection.
ETR and ETS inputs can optionally be used to measure other signal sources like external resistive attenuators for battery voltages different to
12V nominal.
ETR and ETS are single ended inputs and referenced to AVSS. Voltage drop on internal bond wire causes ~100 digits of offset with systematic
temperature dependency of another 50 LSB’s over temperature.
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8.3 Digital Implementation of Measurement Path
Figure 17. Block Diagram of Digital Implementation
R2
R1
MOD_I
N
CIC1
64 / 128
fchop * 2 / R2
fchop * 2
fmod / R1
Dechopper
fmod
MOD_CLK
fchop
FIR_MA_SEL
CIC2
fchop * 2 / R2
FIR / MA
DATAOUT
R1
R1 = First decimation ratio (64 or 128)
R2 = Second decimation ratio (1 to 32768)
CHP_CLK
CLK DIVISION
BLOCK
MOD_CLK
Figure 17 shows the digital implementation of the decimator and filter to process the 1-bit output of the Modulator. This block receives a 1-bit
pulse density modulated output (MOD_IN) from the second order sigma delta modulator along with the oversampling frequency clock
(MOD_CLK). The MOD_CLK directly goes to a clock division block, which generates chopper clock (CHOP_CLK). The CHOP_CLK can be one
of 2kHz or 4kHz selected by Register CLK_REG in Table 49. The MOD_CLK can be either 1MHz or 2MHz. The Decimation is a two phase
process. In the first phase, the R1 down sampling rate can be obtained by selecting either 64 or 128 in Registers DECREG_R1_I,
DECREG_R1_V in Table 49. The 16-bit CIC1 output is dechopped with respect to CHOP_CLK. The output of Dechopper is passed through the
CIC2 filter with a decimation ratio of 1to 32768 in steps of power of 2. This output is then processed through a FIR or Moving Average (MA) filter.
FIR Filter is provided to offer matched low pass filter response typically required in lead acid battery sensor systems. MA filter is used to provide
averaged output and the number of samples for averaging can be any integer value from 1 to 15.
8.4 Reference-Voltage
Band gap-reference voltage is used for the ADC as a reference and for the generation of the current for external temperature measurement.
8.5 Oscillators
A High-speed oscillator (HS) generates the oversampling clock. For internal state machine and Interrupt generation, a low-speed Oscillator (LS)
is also available.
8.6 Power-On Reset
The AS8515 has PORs, APOR and DPOR on analog and digital power supplies respectively. On PORs of both supplies, initialization sequence
happens and the system status is shown in state diagram (see Figure 18).
As shown in the state diagram, the system is in RESET state until DPOR output goes to logic HIGH and subsequently until APOR output goes to
logic HIGH. Once analog power supply is available, the system goes into OTP_INT state and loads the default values into the control and data
registers and goes into STOP state. If analog POR, APOR goes low at any time, the system goes into RESET state. In the STOP state, the
AS8515 can be programmed and by giving start command it starts working following the state machine.
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8.7 Modes of Operation
The device operates in four different modes, namely,
Normal Mode 1 (NOM1)
Normal Mode 2 (NOM2)
Standby Mode 1 (SBM1)
Standby Mode 2 (SBM2)
The Normal Modes are full-power modes with the exception that in Normal Mode 2, sampling is normally at a programmed lower frequency and
is increased to a higher rate only when a measured input signal level crosses the programmed threshold in the current measurement channel.
The Standby Modes are lower power modes. Sampling is normally at a very low frequency interval. In Standby Mode 2, data sampling can be
carried out only when the internal comparator detects the input current to be greater than the programmed threshold and it generates interrupt on
the INT pin.
The device enters into the “Stop” state on Power On. This is a state where in the data path is inactive and can be entered into from any of the
four Modes. The State transition Diagram involving the state of Stop and the four Modes is illustrated in the Figure 18.
!por_dvdd
Figure 18. Finite State Machine Model of AS8515 Bottom Die
por_avdd
!por_avdd
RESET
Wait for otp_load
Completes in 32 cycles
of lp_clk
otp_load
OTP_INT
STOP
s to p
1.5msec &
NORM
A_STB
SBM
sto
p
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SBM_ON
ut
eo
NO
RM
tim
1_
TT
Wait for x
number of
conversions
NORM
NORM
or
stop
1.5msec &
SBM
Analog Stablization
period
Wait for 1.5msec
rt
stop
s ta
SBM
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SBM_OFF
Wait for TT1
timeout
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Figure Notes:
1. Device soft reset can be written in any of the following states STOP, A_STB, SBM_ON, SBM_OFF by writing “0” into D[7] of the RESET
_REG (Address 0X09).
2. Measurement path of soft reset should be written in any the states, STOP, SBM_OFF by writing “0” into D[6] of the RESET _REG (Address
0X09).
3. When soft reset is used for the measurement path or for the device, external clock needs to be disabled if the system clock is external
clock in the application.
8.7.1
Normal Mode 1 (NOM1)
On Power-on-reset of the device, AS8515 goes into STOP State.
Transition to Normal mode1 (NOM1) occurs when the “START BIT” D0 of Mode Control Register MOD_CTL_REG in Table 49 is set to “1”
through the serial port SPI. Data Rate of voltage and current channels can be independently programmed and both the channels generate
interrupts for every output available from ADC. The interrupt signal is generated on the INT pin. The width of the interrupt pulse is eight cycles of
lp_clk. The data is stable up to the next interrupt. If the data rate is different for the two channels, the interrupt rate would follow the higher rate
among the two channels. Data update can be known by reading the status register. The functionality is explained in the waveform shown in
Figure 19. When the device is configured to NORMAL Mode1 from any mode the configuration should be through the STOP state only.
Figure 19. Normal Mode 1
I
IDATA
Sampling with f1
t
V,T
V,TDATA
Sampling with f2
t
STOP
START
Current Channel
DATA Register
Voltage Channel
DATA Register
INT at f1 rate from
current channel
8.7.2
Interrupt from the current channel is at f1 rate which is integer multiple of f2 rate from voltage channel
TINT
Normal Mode 2 (NOM2)
NOM2 differs from NOM1 in such a way that it allows for a relaxed data rate at a period of TMC by programming the corresponding register as
long as the amplitude of current is less than a programmed threshold ITHC. However, when, the measured input signal exceeds the programmed
threshold, the data rate is changed to the rate of NOM1 mode.
Transition to NOM2 occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 49 is set to 1 and mode control bits to
01 through SPI. In this mode the data rate should be programmed with the time of TMC. An interrupt signal is generated on INT at the rate of TMC
secs with a pulse width of eight cycles of lp_clk. The data is stable up to the next interrupt. The data sample is compared against the programmed
threshold and when it is exceeded, the data sampling rate is changed to provide data at the data rate of NOM1 mode. However, as soon as the
data sample amplitude falls below the programmed threshold, the sampling rate is restored to provide data at the rate of TMC. The functionality is
illustrated in the waveform Figure 20.
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Figure 20. Normal Mode 2
I
I < I THS
V,I,T
I DD
V,I,T
V,I,T
TMC
V,I,T
V,I,T
TMC
ITHS
t
Sampling with f
I > I THS
INT
T INT
8.7.3
Standby Mode1 (SBM1)
The low-power Standby Mode can be entered only through the STOP state. Transition to SBM1 mode occurs when the “START BIT” D0 of Mode
Control register MOD_CTL_REG in Table 49 is set to “1” and Mode Control Bits to “10” through SPI. In this mode the date rate is programmable
with the time of Ta. An interrupt signal is generated on INT at the rate of Ta seconds, and with a pulse width of eight cycles of lp_clk. The data is
stable up to the next interrupt. The functionality is illustrated in Figure. During the period of Ta, only one data sample is made available and,
during the rest of the period, the device is maintained in STOP state to reduce power consumption. The microcontroller which receives the data
on the Interrupt, is also expected to be processing the data for a short time as shown clearly in the Figure 21 to ensure the overall low-power
consumption of the data acquisition and processing system.
Figure 21. Standby Mode 1
I DD
MCU
MCU
MCU
V, I, T
V, I, T
ADC
t
Ta
sec.
Start SBM1
Channel
DATA Register
Ta
Tconv
DATA – A0
sec.
DATA – A1
Tconv
Ta
sec.
DATA – A2
Tconv
DATA – A3
INT
TINT
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8.7.4
Standby Mode2 (SBM2)
Standby Mode 2 is an extension of the Standby Mode1 to achieve even a lower power in the data acquisition system by providing interrupt to the
microcontroller only when the data sample exceeds the set current threshold. The Standby Mode can be entered only through the STOP state.
Transition to SBM2 mode occurs when the “START BIT” D0 of Mode Control register MOD_CTL_REG in Table 49 is set to “1” and Mode Control
Bits D7,D6 to “1,1” through SPI. In this mode the date rate is programmable with the time of Ta in the Ta control registers B, C. The data sample
is made available and an interrupt signal is generated on INT pin only when the input signal exceeds the threshold set in Current Threshold
Registers D,E. It should be noted here that the data is stable for Ta seconds. The functionality is illustrated in Figure 22.
Figure 22. Standby Mode 2
I DD
MCU
|I| > I Threshold I
I
ADC
Ta sec.
Tconv
Start SBM2
Channel
DATA Register
Ta sec.
DATA – A0
t
Ta sec.
Tconv
DATA – A1
Tconv
DATA – A3
DATA – A2
INT
TINT
8.8 Initialization Sequence at Power ON
Figure 23. Bottom Die Device Initialization Sequence at Power ON
VPORHID/VPORHIA
DVDD/AVDD
POR_N
Start
ADC
1.5mS
TADC
INT
500µS
CHOP_CLK
Channel Data
Register
Configure
Device
D1
D2
D3
D4
D1
0x0000
D2
D3
D4
D1
DATA1
TDATA_STATUS_RD
TDATA_VALID
D2
D3
D4
DATA2
TDATA_INVALID
Device initialization starts if the DVDD and AVDD supplies are switched ON and DVDD > VPORHID. The duration period of Initialization is 500μsec
and during this period, INT pin toggles at the rate of internal low power oscillator. Toggling on INT during the period of initialization should be
ignored in the system. Device configuration and activation should be carried out only after the initialization period.
On ADC start, device enters into analog stabilization state and takes 1.5msec for oscillator and Reference to settle. After this 1.5msec period, the
first interrupt will occur after a time period of TADC.
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TDATA_STATUS_RD is the time period during which the micro-controller should complete reading of data and status from the device. If reading is
carried out beyond this time period, then, ADC performance will degrade for next sample generation. Status register gets cleared automatically
only when micro-controller reads this register. Data in the channel registers is changed after TDATA_VALID duration. Ensure that data channel
registers and status registers are not read during the TDATA_INVALID duration.
Example:
Configuration registers are set as follows:
CLK_REG = 8’b0010_0000
DEC_REG_R1_I = 0100_0101
DEC_REG_R2_I = 1100_0101
FIR_CTL_REG_I = 0000_0100
ADC is configured to a data rate of 1KHz, CHOP_CLK to 2KHz, and Modulator clock to 1MHz, Decimation ratio of CIC1 = 64, and Decimation
ratio of CIC2 = 4. With these settings the various time periods as shown in the Figure 23 are as follows:
TDATA_STATUS_RD = 100 μsec
(TDATA_STATUS_RD = (1/mod_clk) * R1 * [((mod_clk/(2*chop_clk))*(1/R1)) - 2.5)
TDATA_INVALID = 8 μsec
TADC = 1msec
TDATA_VALID = TADC - TDATA_INVALID = 1msec - 8 μsec
CHOP_CLK and POR_N are internal signals of the device.
Table 29 provides valid combinations of Modulator clock, Chopper clock and Decimation R1 and the corresponding values of TDATA_STATUS_RD and
TADC.
Table 29. Valid Combinations of Modulator Clock, Chopper Clock and Decimation Ratio R1
Modulator Clock
Chopper Frequency
CHOP_CLK
Decimation Ratio R1
TDATA_STATUS_RD
TADC
R2/(2*CHOP_CLK)
for R2=4
1.024MHz
2KHz
64
1usec * 64 * [4 - 2.5] = 96usec
1mSec
2.048MHz
2KHz
64
2.048MHz
2KHz
128
2.048MHz
4KHz
64
8.8.1
0.5usec * 64 * [8 - 2.5] = 176usec
0.5usec * 128 * [4 - 2.5] = 96usec
0.5usec * 64 * [4 - 2.5] = 48usec
1mSec
1mSec
0.5mSec
Soft-reset of Device Using Bit D[7] of Reset Register 0x09
It is possible to soft-reset the device by writing “0” into D[7] bit of Reset Register at 0x09. On applying soft-reset, the device enters into
initialization state and D[6] bit changes back to “1”. The duration period of Initialization is 500μsec, and, during this period, INT pin toggles at the
rate of internal low power oscillator. Toggling on INT during the period of initialization should be ignored in the system. Device configuration and
activation should be carried out only after the initialization period. See Figure 24 for the timing details of the sequence of device initialization on
soft-reset.
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Figure 24. Bottom Die Device Initialization Sequence at Soft-reset
Start
ADC 1.5mS
INT
D4
D1
D3
D2
D4
500µS
D1 Soft Reset
D1
Re-Configure
Device
Using D7
D
3
D2
D4
D1
D3
D2
D4
D1
D3
D2
D4
CHOP_CLK
Channel Data
DATA-N
Register
TDATA_STATUS_RD
DATA1
DATA2
TDATA_STATUS_RD
TDATA_INVALID
TDATA_VALID
8.8.2
0x0000
DATA-N+1
TDATA_INVALID
TDATA_VALID
Soft-reset of the Measurement Path Using Bit D[7] of Reset Register 0x09
Measurement path also can be reset by using D[6] bit of Reset Register at 0x09. On applying soft-reset only signal measurement path registers
will be reset. For applying this reset, device should be in STOP state. If the device is working with external clock, at the time of soft-reset the
clock needs to be disabled.
8.8.3
Reconfiguring Gain Setting of PGA
Only PGA gain settings can be changed dynamically while ADC conversions are in progress. When PGA gain settings are changed, the first
sample from the ADC is invalid. Ignore the first interrupt after the gain re-configuration. Valid data starts from the second interrupt onwards.
Figure 25. Bottom Die - Re-configuration of Gain Setting of PGA
Gain Re-Configuration can be
carried out in this slot, skip next
interrupt and Channel Data.
Read Channel
data in this slot
VALID
DATA
TDATA_STATUS_RD
INT
D4
D1
D2
D3
D4
D1
D2
D3
D4
D1
D2
D3
D4
D1
D2
D3
D4
CHOP_CLK
Channel Data
Register
DATA-N
TDATA_STATUS_RD
TDATA_VALID
8.8.4
DATA-N+1
DATA1
TDATA_STATUS_RD
TDATA_INVALID
TDATA_VALID
DATA2
TDATA_INVALID
Configuring the Device During Normal Mode
Following registers can be programmed dynamically when the device is in operational mode (Normal mode).
ACH_CTL_REG address is 0x17 for channel selection on the voltage measurement path
PGA_CTL_REG address is 0x13 for gain setting
PD_CTL_REG2 address is 0x15 for PGA Bypass
ISC_CTL_REG address is 0x18 for current source programmability
During the operation (Normal mode) of the device, if any of the registers need to be programmed or changed other than the above mentioned
registers, then it is required to STOP the device by writing into MOD_CTL_REG “STOP” bit and configure the device as per the requirements and
start the device.
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8.8.5
Standby Mode - Power Consumption
In Standby Mode 1 there is a timer based accurate measurement every Ta seconds. The device itself stays in idle-mode as long as it does not
get a different command from the SPI interface. Internal oscillator frequency is typically foscint=262 kHz to reduce power consumption as long as
the timer runs. After every time out of Ta seconds, it performs accurate measurement of current, voltage/ temperature. Data ready is signaled to
microcontroller through an interrupt signal on INT and goes into STOP state.
In the SBM the following equations hold:
Tsbm1 = Ta= 10s (default value is 10secs); the power consumption is valid for this setting. This is the period of the repetition rate in SBM 1
and SBM2.
Tsett ≈ 2ms (depending on external capacitors). This is the time required by the analog part to settle when the new measuring period is
started. Any measurements performed during Tsett produce invalid results.
T1 = 3ms (by default setting, every third measurement is sent to microcontroller in the SBM mode 1) is the time needed to perform the first
measurement.
Tmeas =Tsett +T1 is the total active time needed to get a valid result.
DRSBM
= Tmeas/Tsbm ≈ 5ms/10s. This is the ratio of repetition time versus the active time (Device in NOM mode).
Power consumption = (DRSBM*NOM mode power consumption) + ((10s-5ms)/10s)*Stop mode power consumption)
8.9 Bottom Die Block Specifications
This section provides specification of design related key parameters.
8.9.1
Current Measurement Ranges (across 100µΩ (±5%) shunt resistor)
Table 30. Current Measurement Ranges
Symbol
Parameter
Imax
[A]
Vsh
[mV]
PGA
Gain
Nominal
Data Rate
(fOUT)
VINADC
[mV]
PSR
[dB]
I70
Input current range of 70A in NOM
±77
±8.1
100
@ 1 kHz
890
60
I200
Input current range of 200A in NOM
±235
±24.7
40
@ 1 kHz
1088
60
I400
Input current range of 400A in NOM
±400
±42
25
@ 1 kHz
1137
60
I1500
Input current range of 1500A in NOM
+2076/-1523
+218/-160
5
@ 1 kHz
1204
60
1
2
1. VINADC = Vsh * Gain, gain deviations to be considered according to Table 32 and Table 33.
2. AVDD, DVDD of 3.3V with ±5% variation.
Note: The Data Rate at the output can be calculated according to the formula:
fsout=2*fchop /R2 (R2 is down sampling ratio taking values 1, 2, 4 up to 32768 as powers of 2)
Table 31. Valid Combinations of the Chopper Clock, Oversampling Clock and Decimation Ratios
Over Sampling Frequency
Chopper Frequency
Decimation Ratio
1.024MHz
2kHz
64
2.048MHz
2kHz
64
2.048MHz
2kHz
128
2.048MHz
4kHz
64
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Datasheet - A S 8 5 1 5 B o t t o m D i e O v e r v i e w
Differential Input Amplifier for Current Channel.
Table 32. Differential Input Amplifier for Current Channel
Symbol
Parameter
Conditions
Min
VIN_AMP
Input voltage range
RSHH and RSHL
-160
RSHH and [email protected] +160mV input
voltage at 125ºC with PGA
-50
IIN_AMP
ICM
Input current
1, 11
Absolute input voltage range
Typ
2
3, 4, 9
I10
100
G = G2
Gain2
3, 4, 9
I200
40
G = G3
Gain3
3, 4, 9
I400
25
G = G4
Gain4
3, 4, 9
I1500
5
e
fP_AMP
εT1
VOSDRIFT
Vos
Vos_ch
VNdin
THD
Gain deviation
Pole frequency
i = 1, 2, 3, 4
4, 5
Input referred offset
Noise density
7, 10
6
0.9 * Gi
mV
50
nA
mV
1.1 * Gi
kHz
-20ºC to +65ºC
Gain 5, 25, referenced to room
temperature
7, 10
±0.5
350
After trim at -20deg
Chopping enabled
4, 8
Total harmonic distortion
+160
15
Gain drift with temperature
Offset drift with temperature
Units
-160
+300
2
Gain1
G = G1
Max
For 150 Hz input signal
%
µV
350
µV
0
LSB
25
nV/√Hz
70
dB
Notes:
1. Leakage test accuracy is limited by tester resource accuracy and tester hardware.
2. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
3. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are programmed independently.
4. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaranteed by design.
5. Pole frequency of input amplifier changes with GAIN. The number is valid for the gain at G1, while the bandwidth will be higher for other
ranges. This parameter is not measured in production.
6. Based on device evaluation. Not tested.
7. These offsets are cancelled if chopping enabled (default).
8. Noise density calculated by taking system bandwidth as 150Hz.
9. Refer to Measurement Ranges shown in Table 30.
10. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
11. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of
protection diode.
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Datasheet - A S 8 5 1 5 B o t t o m D i e O v e r v i e w
Differential Input Amplifier for Voltage Channel.
Table 33. Differential Input Amplifier for Voltage Channel
Symbol
Parameter
Conditions
VIN_AMP
Input voltage range
IIN_RES
Input resistance
ICM
1, 10
Min
Typ
-160
VBAT_IN, ETR, ETS @ +160mV input
voltage at 125ºC with PGA
2, 10
3
Absolute input voltage range
mV
100
G = G2
Gain2
4, 5
40
G = G3
Gain3
4, 5
25
G = G4
Gain4
4, 5
5
fP_AMP
Pole frequency
VNDIN
Noise density
5, 6
5, 7
Total harmonic distortion
εT1
Gain drift with temperature
Vos_ch
VOSDRIFT
Input referred offset
0.9 * Gi
1.1 * Gi
15
THD
VOS
mV
-160
+300
4, 5
i = 1, 2, 3, 4
+160
kΩ
Gain1
Gain deviation
Units
12.5
G = G1
e
Max
For 150Hz input signal
8
9
Offset drift with temperature
kHz
25
nV/√Hz
70
dB
-20ºC to +65ºC
Gain 5, 25, referenced to room
temperature
±0.5
%
After trim at -20ºC
350
µV
Chopping enabled
9
0
LSB
350
µV
Notes:
1. Input for the voltage channel can be as high as 1220mV, in this high input case PGA will be bypassed.
2. Leakage test accuracy is limited by tester resource accuracy and tester hardware, especially at low temperatures due to condensing
moisture.
3. For gain 100 PGA input common mode is 0V and the minimum supply is 3.15V.
4. The measurement ranges are referred only by the gain of input amplifier, while other parameters such as bandwidth etc. are programmed independently.
5. This parameter is not measured directly in production. It is measured indirectly via gain measurements of the whole path. It is guaranteed by design.
6. Pole frequency of input amplifier changes with changing the GAIN. The number is valid for the gain at G1, while the bandwidth will be
higher for other ranges. This parameter is not measured in production.
7. Noise density calculated by taking system bandwidth as 150Hz.
8. Based on device evaluation. Not tested.
9. No impact on the measurement path. If the chopping is enabled, both the offset and offset drift will be eliminated.
10. For negative input voltages up to -160mV below ground, Input leakage is typically -20nA @ 65ºC due to forward conductance of
protection diode.
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Datasheet - A S 8 5 1 5 B o t t o m D i e O v e r v i e w
Sigma Delta Analog to Digital Converter.
Table 34. Sigma Delta Analog to Digital Converter
Symbol
Parameter
Conditions
Min
6
VREF
Reference voltage
VINADC
Input range
R1
Oversampling ratio/Decimation Ratio
fOVS
Oversampling frequency
RES
Number of bits
BW
Bandwidth
S/N
Signal to noise ratio
Typ
Max
1.225
1
At VREF = 1.22V
2
0
64
V
±1.22
128
4
1
5
V
128
1024/
2048
3
Units
kHz
16
bits
500
Hz
90
dB
Notes:
Production test at ±800mV. Maximum VIN can be 1.22V with VREF=1.225V.
Programmable. It is defined with respect to the first decimator in the ΣΔ ADC.
Programmable: Internal clock is 1024/2048 kHz; external clock max is 8192 kHz.
Dependent on fovs, R1 and R2. The bandwidth is calculated according to the formula:
BW=fovs/(2*R1*R2); the sampling frequency at the output of the A/D converter is 2*BW.
5. Defined at maximum input signal, BW=500 Hz (1Hz to 500 Hz), fovs=1024 kHz, R1=64, fchop=2 kHz and R2=2.
6. Reference voltage might be forced from external.
1.
2.
3.
4.
Bandgap Reference Voltage.
Table 35. Bandgap Reference Voltage
Symbol
Parameter
Conditions
1, 2, 3
VREFTRIM
Reference Voltage after trim
VREFACC
Reference Voltage Initial Accuracy
VREFDRIFT
PSRRREF
Reference Voltage Temperature drift
Start Up Time with supply ramp
SUTPD
Start Up Time from power down
4
RNDVREF
Output resistance of band gap
ESRVREF
Bandgap reference thermal noise density
Typ
Max
1.225
Units
V
At 65ºC (0 Hour data)
±3.5
mV
Temperature range
-20ºC to 65ºC
±0.4
%
Temperature range
-40ºC to 125ºC
PSR @ dc
SUTAVDD
CLVREF
Trim at 65ºC
1, 2, 3
4
VNDVREF
Min
+0.4/
-0.6
%
80
dB
5
ms
500
4
1
ms
1000
Ω
300
nV/√Hz
100
Output Capacitor (Ceramic)
0.02
nF
1
Ω
Notes:
1.
2.
3.
4.
Accuracy at 65ºC. No DC current is allowed from this pin.
Specification does not include solder shift and life time drift.
Please refer Figure 26 for typical life time drift based on system level measurements.
This is a design parameter and not production tested.
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Datasheet - A S 8 5 1 5 B o t t o m D i e O v e r v i e w
Figure 26. Typical System-level VREF Drift
AS8515
1.2265
1.2260
Ref-Voltage [VREF]
1.2255
DUT1
1.2250
DUT2
DUT3
DUT4
1.2245
0.10%
-0.10%
1.2240
1.2235
1.2230
0
50
100
150
200
250
300
System Level Operating Time in Normal mode at 115ºC ambient [h]
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Datasheet - A S 8 5 1 5 B o t t o m D i e O v e r v i e w
Internal (Programmable) Current Source for External Temperature Measurement.
Table 36. External Temperature Measurement
Symbol
Parameter
ICURON
5-bit current source enabled
ICUROFF
5-bit current source disabled
TK_CS
Temperature coefficient of current source
VMAXETR
Voltage on pin ETR
VMAXETRMOD
Max voltage on pin ETR when PGA is
4
bypassed
VMAXETS
Voltage on pin ETS for resistor sensor
VMAXETSMOD
Max. Voltage on pin ETS when PGA is
5
bypassed
1
Conditions
Min
Typ
Max
Units
5-bit programmable current source
0
270
320
µA
Limited by leakage
2
10
nA
1000
ppm
/ ºK
3
3
1000/G
mV
1.22
V
1000/G
V
1.22
V
Notes:
1. Current value can be programmed through stop mode in steps of 8μA from 0 to 256μA with a process error of 30%.
2. Temperature coefficient is not important since external temperature measurement is a 2 step measurement. The value specified is
guaranteed by design and will not be tested in production.
3. Maximum voltage on pin ETR (reference) can be calculated by given formula, where G is the gain of PGA (G=100).
4. Maximum voltage on pin ETR, if PGA is bypassed.
5. Maximum voltage on pin ETS, if PGA is bypassed.
CMREF Circuit (VCM).
Table 37. CMREF Circuit
Symbol
Parameter
Min
Typ
Max
Units
VVCM
Output voltage
1.6
1.7
1.8
V
CL
Load capacitance
100
nF
Internal AVDD Power-on Reset.
Table 38. Internal AVDD Power-on Reset
Symbol
VPORHIA
Parameter
Power On Reset Threshold
tPORA
POR time - The duration from Power ON till
the time, internal Power On Reset signal
1
goes HIGH
IPORA
Current consumption in POR block
Min
Typ
Max
Units
2.2
2.4
2.6
V
1
2
µs
1.5
µA
1. POR pulse is always longer than tPORA whatever the slope of the supply.
2. IPORA can not be switched off.
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Internal DVDD Power-on Reset.
Table 39. Internal DVDD Power-on Reset
Symbol
Parameter
Power On Reset Threshold
VPORHID
1
VHYST
Hysteresis
tPORD
POR time - The duration from Power ON till the
time, internal Power On Reset signal goes
2
HIGH
IPORD
Current
Min
Typ
Max
Units
2.2
2.4
2.7
V
0.2
0.25
0.4
V
1
3
µs
1.5
µA
1. VPORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR.
2. VPORLO = VPORHI - VHYST where VPORLO is the lower threshold of POR.
3. IPORD can not be switched off.
Low Speed Oscillator.
Table 40. Low Speed Oscillator
Symbol
Parameter
Min
Typ
Max
Units
fLS
Frequency
262.144
kHz
fLS_ACC
Accuracy
±7
%
ILS
Supply current
5
µA
High Speed Oscillator.
Table 41. High Speed Oscillator
Symbol
Parameter
fHS
Frequency
Min
1
fHSACC
Accuracy
IHS
Supply current
Typ
Max
Units
4.096
MHz
±4
%
300
µA
Notes:
1. Accuracy after trimming.
External Clock.
Table 42. External Clock
Symbol
Parameter
fCLKEXT
Clock frequency
DIVCLKEXT
Clock division factor
DCCLKEXT
Duty Cycle of external clock
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Conditions
Min
Typ
Max
2048/
4096/
8192
to be programmed in Register 08
CLK_REG through the serial bus SPI.
kHz
2/4/8
40
Revision 0.7
Units
60
%
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Datasheet - A S 8 5 1 5 B o t t o m D i e O v e r v i e w
Internal Temperature Sensor.
Table 43. Internal Temperature Sensor
Symbol
Parameter
TINTRNG
Temperature sensor range
ΔTIN
Temperature measurement accuracy
TINTSLP
Temperature sensor slope
TINT65G5
Temperature sensor output at gain 5
8.9.2
Conditions
Min
Typ
-40
Guaranteed by design; at PGA gain 5
which is the recommended Gain for
internal temperature measurement.
40660
Max
Units
125
ºC
3
ºC
27
Digits/C
41807
43012
Digits
System Specifications
Table 44. System Specifications
Symbol
Parameter
IS
Channel to channel isolation
At
Ph
Min
Typ
Max
Units
-90
dB
Difference in channel to channel attenuation
1, 2
@600Hz
3
dB
Difference in phase shift between the two
1, 2
channels @600Hz
5
Deg
1
System Measurement Error Budget for Voltage and Current Channel.
Temperature Range: -20ºC to +65ºC; Output data rate is 1kHz, VCC = 3.3V, chopping enabled.
Table 45. System Measurement Error Budget for Gains 5 and 25
Symbol
Parameter
Err
System measurement error
Conditions
3, 4
Measurement error due to PGA gain drift
From device evaluation
Measurement error due to VREF drift
Measurement error due to non-linearity of PG
Tested by distortion measurements
Min
Typ
Max
Units
±0.6
1
%
±0.5
%
±0.4
%
±0.025
%
Notes:
1.
2.
3.
4.
These specifications are defined by taking one channel as reference and measured on the other channel.
Guaranteed by design.
System measurement error due to noise, individual block parameter drifts and non linearity. Based on evaluation, not tested.
System error due to offset is neglected because of chopper architecture.
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Datasheet - 4 - W i r e S P I I n t e r f a c e
9 4-Wire SPI Interface
The SPI interface can also be used as interface between the AS8515 and an external micro-controller to configure the device and access the
status information. Micro-controller begins communication with the SPI configured as a slave. The SPI protocol is very simple and the length of
each frame is an integer multiple of byte except when a transmission is started. Basically each frame has 1 command bits, 5 address/
configuration bits, 1 or more data bytes. SPI clock polarity settings depend on the value of the SCLK on the CS falling edge. This setting is done
on each start of the SPI transaction. During the transaction SPI clock polarity will be fixed to the settings done. On the CS falling edge the values
on SCLK signal decide setting of the active SPI clock edge for data transfer (see Table 46).
Table 46. CS and SCLK
1
SCLK
Description
FALL
LOW
Serial data transferred on rising edge of SPI clock.
Sampled at falling edge of SPI clock.
FALL
HIGH
Serial data transferred on falling edge of SPI clock.
Sampled at rising edge of SPI clock.
ANY
ANY
Serial data transfer edge is unchanged.
CS
1. Pin CST is used to program top device and pin CSB is used to program bottom device.
9.1 SPI Timing Parameters
Table 47. 4-Wire Serial Port Interface
Symbol
Parameter
Conditions
Min
Typ
Max
Units
250
Kbps
General
BRSPI
Bit rate
TSCLKH
Clock high time
2
µs
TSCLKL
Clock low time
2
µs
tDIS
Data in setup time
20
ns
tDIH
Data in hold time
10
ns
TCSH
CS hold time
20
ns
Write Timing
Read Timing
tDOD
Data out delay
tDOHZ
Data out to high impedance delay
Time for the SPI to release the SDO bus
80
ns
80
ns
Timing parameters when entering 4-Wire SPI mode (for determination of CLK polarity)
tCPS
Clock setup time
(CLK polarity)
Setup time of SCLK with respect to
CS falling edge
20
ns
tCPHD
Clock hold time
(CLK polarity)
Hold time of SCLK with respect to
CS falling edge
20
ns
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9.1.1
SPI Frame
A frame is formed by a first byte for command and address/configuration and a following bit stream that can be formed by an integer number of
bytes. Command is coded on the 1 first bit, while address is given on LSB 5 bits (see Table 48).
Table 48. Command Bits
Command Bits
C0
Reserved
Register Address or Transmission Configuration
Reserved
A4
A3
A2
A1
C0
Command
<A4:A0>
Description
0
WRITE
ADDRESS
Writes data byte on the given starting address
1
READ
ADDRESS
Reads data byte from the given starting address
A0
If the command is read or write, one or more bytes follow. When the micro-controller sends more bytes (keeping CS LOW and SCLK toggling),
the SPI interface increments the address of the previous data byte and writes/reads data to/from consecutive addresses.
9.1.2
Write Command
For Write command C0 = 0.
After the command code C0 and two reserved bits, the address of register to be written has to be provided from the MSB to the LSB. Then one
or more data bytes can be transferred, always from the MSB to the LSB. For each data byte following the first one, used address is the
incremented value of the previously written address. Each bit of the frame has to be driven by the SPI master on the SPI clock transfer edge and
the SPI slave on the next SPI clock edge samples it. These edges are selected as per clock polarity settings. In the following figures two
examples of write command (without and with address self-increment.
Figure 27. Protocol for Serial Data Write with Length = 1
CS
SCLK
SDI
0
RES1 RES0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
Transfer edge
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Sampling edge
Revision 0.7
Data D7 – D0 is moved to
Address A4..A0 here
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Datasheet - 4 - W i r e S P I I n t e r f a c e
Figure 28. Protocol for Serial Data Write with Length = 4
CS
SCLK
SDI
RE RE A A A A A D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D
0 S1 S0
4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SDO
Data D7-D0 is
moved to Address
A4-A0 here
9.1.3
Data D7-D0 is
moved to Address
A4-A0 +1 here
Data D7-D0 is
moved to Address
A4-A0 +2 here
Data D7-D0 is
moved to Address
A4-A0 +3 here
Data D7-D0 is
moved to Address
A4-A0 +4 here
Read Command
For Read command C0=1.
After the command code C0 and two reserved bits, the address of register to be read has to be provided from the MSB to the LSB. Then one or
more data bytes can be transferred from the SPI slave to the master, always from the MSB to the LSB. To transfer more bytes from consecutive
addresses, SPI master has to keep active the SPI CS signal and the SPI clock as long as it desires to read data from the slave. Each bit of the
command and address sections of the frame have to be driven by the SPI master on the SPI clock transfer edge and the SPI slave on the next
SPI clock edge samples it. Each bit of the data section of the frame has to be driven by the SPI slave on the SPI clock transfer edge and the SPI
master on the next SPI clock edge samples it. These edges are selected as per clock polarity settings. In the following figures, two examples of
read command (without and with address self-increment) have been shown.
Figure 29. Protocol for Serial Data Read with Length = 1
CS
SCLK
SDI
1
RES1
RES0
A4
A3
A2
A1
SDO
D7
Transfer edge
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A0
Sampling edge
D6
D5
Data D7 – D0 at Address A4..A0
is read here
Revision 0.7
D4
D3
D2
Transfer edge
D1
D0
Sampling edge
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Datasheet - 4 - W i r e S P I I n t e r f a c e
Figure 30. Protocol for Serial Data Read with Length = 4
CS
SCLK
SDI
1
RE RE
S1 S0
A A A A A
4 3 2 1 0
D D D D D D D D D D D D D D D D D D D D D D D D D D D DD D D D D D D D D D D D
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SDO
Data D7-D0 at
Address A4-A0
is read here
9.1.4
Data D7-D0 at
Address A4-A0 +1
is read here
Data D7-D0 at
Address A4-A0 +2
is read here
Data D7-D0 at
Address A4-A0 +3
is read here
Data D7-D0 at
Address A4-A0 +4
is read here
Timing
In the following figures timing waveforms and parameters are exposed.
Figure 31. Timing for Writing
CS
...
t CPS
SCLK
t CPHD
t SCLKH
t CSH
CLK
polarity
...
t DIS
SDI
t SCLKL
t DIH
DATAI
DATAI
DATAI
...
SDO
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...
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Datasheet - 4 - W i r e S P I I n t e r f a c e
Figure 32. Timing for Reading
CS
t SCLKH
t SCLKL
SCLK
DATAI
SDI
DATAI
t DOD
SDO
DATAO (D7)
t DOHZ
DATAO (D0)
9.2 Bottom Die Registers
This section describes the control registers used in AS8515 Bottom die. Registers can be broadly classified into the following categories.
Data access registers
Status Registers
Digital signal path control registers
Digital Control registers
Analog Control Registers
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Data Access Registers
00
DREG_I1
(ADC Data Register for Current)
0000_0000
R
D[7:0]
Denotes the Current ADC MSB Byte (ADC_I[15:8])
01
DREG_I2
(ADC Data Register for Current)
0000_0000
R
D[7:0]
Denotes the Current ADC LSB Byte (ADC_I[7:0])
02
DREG_V1
(ADC Data Register for Voltage)
0000_0000
R
D[7:0]
Denotes the Voltage ADC MSB Byte (ADC_V[15:8])
03
DREG_V2
(ADC Data Register for Voltage)
0000_0000
R
D[7:0]
Denotes the Voltage ADC LSB Byte (ADC_V[7:0])
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Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Status Registers
04
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STATUS_REG
0000_0000
R
D[7]
NOM1/NOM2 Data Ready
D[6]
NOM2 Threshold Crossover
D[5]
SBM1 Data Ready
D[4]
SBM2 Threshold Crossover
D[3]
APOR status
D[2]
Data from current channel updated
D[1]
Data from voltage channel updated
D[0]
Reserved
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Datasheet - 4 - W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Digital Signal Path Control Registers for Current Channel
D[7]
This bit selects decimation rate is used for current
channel. Default is 0 (Down Sampling Rate is 64)
0
Down Sampling Rate is 64
1
Down Sampling Rate is 128
These two bits select division ratio of oversampling
frequency clock MOD_CLK to be used as chopper
clock, CHOP_CLK.
Default is “10” (divide by 512)
D[6:5]
00
Chopper Clock Always High
01
Divide by 256
10
Divide by 512
11
Divide by 1024
These four bits select the decimation ratio of second
CIC stage. Default is “0010” (equal to 4)
05
DEC_REG_R1_I
0100_ 0101
R/W
D[4:1]
0000
1
0001
2
0010
4
0011
8
0100
16
0101
32
0110
64
0111
128
1000
256
1001
512
1010
1024
1011
2048
1100
4096
1101
8192
1110
16384
1111
32768
CIC1 Saturation Interrupt Mask Control.
Default is 1
D[0]
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Unmask
1
Mask
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Datasheet - 4 - W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
D[7]
I-Channel Enable, Default 1=enable
D[6]
V-Channel Enable, Default 1=enable
Interrupt polarity
D[5]
0
Active high
1
Active low
. Interrupt Mask Control for Current Channel Data
Ready Interrupt on INT pin (Default is 0)
D[4]
06
DEC_REG_R2_I
1100_0101
0
Unmasked
1
Masked
These two bits select the source of output 16-bit data in
Normal mode from Current channel. Default is 01
R/W
D[3:2]
00
FIR / MA Output
01
CIC2 Output
10
Dechop/Demod Output
11
CIC1 Output
These two bits select the source of output 16-bit data in
SBM mode from Current channel. Default is 01
D[1:0]
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Revision 0.7
00
FIR / MA Output
01
CIC2 Output
10
Dechop/Demod Output
11
CIC1 Output
51 - 65
AS8515
Datasheet - 4 - W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
This bit selects FIR / MA Filter in Current channel.
Default is 0 (FIR)
D[7]
0
FIR
1
MA Filter
These bits select the number of data samples for
averaging in MA filter in Current channel.
Default is 0000 (bypass)
D[6:3]
07
FIR CTL_REG_I
0000_0100
R/W
0000
bypass
0001
1
0011
3
0111
7
1111
15
These two bits select the Measurement Path
architecture in both Current and Voltage channels.
Default is 10 (Dechopper after CIC)
D[2:1]
D[0]
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Revision 0.7
00
Demodulator after CIC1
01
Demodulator before CIC1
10
Dechopper after CIC1
(preferred and suggested)
11
Demodulator before CIC1 with settled
sample
Reserved. Default 0. Do not change
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AS8515
Datasheet - 4 - W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Digital Control Registers
Oversampling frequency clock selection. Default is 00
(high speed (HS) internal Clock)
D[7:6]
00
Internal HS Clock with No Clock Output
01
Internal HS Clock with Clock Output
10
External Clock
These two bits select the division ratio for HS clock/
external clock. Default is 10 (division by 4)
D[5:4]
08
CLK_REG
(Clock Control Register)
0010_0000
R/W
00
No division
01
Divide by 2
10
Divide by 4
11
Divide by 8
These two bits select the division ratio of HS clock, by
which it should be divided before providing it on CLK
pin. Default is 00 (No Division)
D[3:2]
00
No Division
01
Divide by 2
10
Divide by 4
11
Divide by 8
This bit selects the division ratio of LS clock
D[1]
09
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RESET_REG
(Reset Control Register)
1100_0000
R/W
0
LS _CLK undivided (Low Speed clock)
1
LS _CLK divide by 2
D[0]
Reserved
D[7]
Entire device can be soft reset by writing “0” into this
register bit. This bit will take a default 1 value on coming
out of Reset
D[6]
Measurement Path can be soft reset by writing “0” into
this register bit. This bit will take a default 1 value after
Measurement Path is reset.
D[5:0]
Reserved
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AS8515
Datasheet - 4 - W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
These two bits select the operating mode of the Device.
Default is 00 (Normal Mode 1)
00
D[7:6]
Normal Mode 1
01
Normal Mode 2
10
Standby Mode 1
11
Standby Mode 2
These three bits select the number of cycles to be
ignored before comparison with the set threshold in
Standy Mode. Default is 000 (3 cycles of data)
D[5:3]
0A
MOD_CTL_REG
(Mode Control Registers)
0000_0000
R/W
D[2]
000
3 cycles of data
001
4 cycles of data
010
5 cycles of data
011
6cycles of data
100
7 cycles of data
101
8 cycles of data
110
9 cycles of data
111
10 cycles of data
This bit controls the CHOP_CLK availability on
CHOP_CLK pin.
Default is 0
0
Disabled
1
Enabled
Enabling the MEN pin to indicate transition from
Standby to Normal Mode.
D[1]
0
Disabled
1
Enabled
This bit is used to take the device from STOP state to
any of the Modes based on D[7:6] selection of this
register.
D[0]
0
Retain in STOP state
1
Enables transition to Normal or Standby
Modes.
Unit of Ta in SBM1/SBM2. Default is 1
0B
MOD_Ta_REG1
(Ta Control Register)
D[7]
1000_0000
0
Unit is in milliseconds
1
Unit is in seconds
D[6:0]
MSB value of Ta
0C
MOD_Ta_REG2
(Ta Control Register)
0000_0000
R/W
D[7:0]
Unit of Ta in SBM1/SBM2
LSB value of Ta
0D
MOD_ITH_REG1
(Current Threshold Register)
0000_0000
R/W
D[7:0]
MSB bits of 16 bits SBM2 threshold register
0E
MOD_ITH_REG2
(Current Threshold Register)
0000_0000
R/W
D[7:0]
LSB bits of 16 bits SBM2 threshold register
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Revision 0.7
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AS8515
Datasheet - 4 - W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
0F
MOD_TMC_REG1
(TMC Control Registers)
0000_0000
R/W
D[7:0]
MSB value of number of data samples to be dropped
from ADC before sending Interrupt in NOM2
10
MOD_TMC_REG2
(TMC Control Register)
0000_0000
R/W
D[7:0]
LSB value of number of data samples to be dropped
from ADC before sending Interrupt in NOM2
11
NOM_ITH_REG1
0000_0000
R/W
D[7:0]
Eight MSB bits of NOM2 current threshold register
12
NOM_ITH_REG2
0000_0000
R/W
D[7:0]
Eight LSB bits of NOM2 current threshold register
8-bit Control / Status Data
Analog Control Registers
Setting of Gain G of Current Channel PGA. Default is
01 (G = 25)
D[7:6]
13
PGA_CTL_REG
(PGA Control Registers)
0101_0000
R/W
00
5
01
25
10
40
11
100
Setting of Gain G in Voltage channel. Default is 01 (G =
25)
D[5:4]
00
5
01
25
10
40
11
100
D[3:0]
D[7]
D[6]
14
PD_CTL_REG_1
(Power Down Control Register)
1100_1111
R/W
0
Disable Chopper clock to Current channel
1
Enable Chopper clock to Current channel
0
Disable Chopper clock to Voltage channel
1
Enable Chopper clock to Voltage channel
D[5]
Reserved
D[4]
Reserved
D[3]
D[2]
D[1]
D[0]
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Reserved
Revision 0.7
0
Disable Current channel PGA
1
Enable Current channel PGA
0
Disable Current channel ΣΔ Modulator
1
Enable Current channel ΣΔ Modulator
0
Disable Voltage channel PGA
1
Enable Voltage channel PGA
0
Disable Voltage channel ΣΔ Modulator
1
Enable Voltage channel ΣΔ Modulator
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AS8515
Datasheet - 4 - W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
D[7]
D[6]
D[5]
D[4]
D[3]
15
PD_CTL_REG_2
(Power Down Control Register)
1111_0011
R/W
0
Disable CIC1 of both channels
1
Enable CIC1 of both channels
0
Disable CIC2 of both channels
1
Enable CIC2 of both channels
0
Disable Dechopper in both channels
1
Enable Dechopper in both channels
0
Disable FIR in both channels
1
Enable FIR in both channels
0
Do not bypass PGA in Current Channel
Default 0
1
Bypass PGA in Current Channel
0
Do not bypass PGA in Voltage Channel
Default 0
1
Bypass PGA in Voltage Channel
Note: For Automotive Battery
measurement, ensure that the PGA is
bypassed to connect battery voltage
(attenuated by factor of 21) directly to the
ADC input.
D[2]
D[1]
D[0]
D[7]
D[6]
D[5]
16
PD_CTL_REG_3
(Power Down Control Register)
1111_1000
Disable Current Channel Chopper
1
Enable Current Channel Chopper
0
Disable Voltage Channel Chopper
1
Enable Voltage Channel Chopper
0
Disable Common Mode Reference
1
Enable Common Mode Reference
0
Disable Internal Current Source
1
Enable Internal Current Source
0
Disable Internal temperature sensor
1
Enable Internal temperature sensor
D[4]
Reserved. (Default 1) Do not change
D[3]
Reserved. (Default 1) Do not change
D[2]
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0
0
Data Output in binary numbering system
1
Data Output in 2’s complement numbering
system
D[1]
Reserved. (Default 0) Do not change
D[0]
Reserved
Revision 0.7
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AS8515
Datasheet - 4 - W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
These bits specify the selection of voltage/temperature
in Voltage Channel
Default is 00 (Voltage Channel)
D[7:6]
00
Voltage Channel
01
External Temperature Channel ETR
10
External Temperature Channel ETS
11
Internal Temperature Channel
D[5]
Reserved. (Default 0) Do not change
Internal current source switch enable. Default is 0
17
ACH_CTL_REG
(Analog Channel Selection
Register)
0000_0000
R/W
D[4]
Note: D4 bit is used for Enabling current source to
the channel selected by bits D[7,6] of this
register.
0
Disabled
1
Enabled
Enable/disable Internal current source to RSHH pin of
Current channel
D[3]
0
Disabled
1
Enabled
Enable/disable current source switch to RSHL pin of
Current channel
D[2]
0
Disabled
1
Enabled
D[1:0]
Reserved
These three bits specify the selection of magnitude of
current from the Internal current source. Default is
00000 (0µA).
18
ISC_CTL_REG
(Current Source Setting Register)
0000_0000
R/W
D[7:3]
00000
0µA
00001
8.5µA
00010
17µA
00100
34.5µA
01000
68µA
10000
135µA
11111
270µA
D[2:0]
19
44
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OTP_EN_REG
STATUS_REG_2
0000_0000
0000_0000
R/W
R
D[7]
Reserved
1
Reserved (default = 1) Do not change
D[6:0]
Reserved
D[7]
Status indicating data saturation in Current channel
D[6]
Status indicating data saturation in Voltage channel
D[5:0]
Reserved
Revision 0.7
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AS8515
Datasheet - 4 - W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
Digital Signal path control registers for Voltage Channel
D[7]
Selection of Decimation ratio for Voltage/Temperature
channel.
Default is 0 (Down Sampling Rate is 64)
0
Down Sampling Rate is 64
1
Down Sampling Rate is 128
Division of oversampling clock, which is used as
Chopper Clock. Default is 10 (divide by 512)
D[6:5]
00
Chopper Clock Always High
01
Divide by 256
10
Divide by 512
11
Divide by 1024
Decimation ratio of CIC2. Default is 0010 (4)
45
DEC_REG_R1_V
0100_ 0101
R/W
D[4:1]
0000
1
0001
2
0010
4
0011
8
0100
16
0101
32
0110
64
0111
128
1000
256
1001
512
1010
1024
1011
2048
1100
4096
1101
8192
1110
16384
1111
32768
CIC1 Saturation Interrupt Mask Control.
Default is 1
D[0]
www.ams.com
Revision 0.7
0
Unmasked
1
Masked
58 - 65
AS8515
Datasheet - 4 - W i r e S P I I n t e r f a c e
Table 49. Control Registers
Addr in
HEX
Register Name
POR Value
R/W
8-bit Control / Status Data
D[7:5]
Reserved
Interrupt Mask Control for Voltage channel data Ready
Interrupt on INT pin (Default is 0)
D[4]
46
DEC_REG_R2_V
0000_0100
0
Unmasked
1
Masked
These two bits select the source of output 16-bit data in
Normal mode from Voltage channel. Default is 01
R/W
D[3:2]
00
FIR / MA Output
01
CIC2 Output
10
Dechop/Demod Output
11
CIC Output
D[1:0]
Reserved
This bit selects FIR / MA Filter in Voltage channel.
Default is 0 (FIR)
D[7]
47
FIR CTL_REG_V
0000_0000
0
FIR
1
MA Filter
These bits select the number of data samples for
averaging in MA filter in Voltage channel.
Default is 0000 (bypass)
R/W
D[6:3]
D[2:0]
0000
bypass
0001
1
0011
3
0111
7
1111
15
Reserved
Note: All the registers from address 0x19 to 0x2C are read-only.
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Revision 0.7
59 - 65
AS8515
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
10 Application Information
10k
Figure 33. Application Diagram
100nF
27
26
24
INT
Tx
25
CLK
28
CST
29
RESET
EN
RSHL
2
30
31
RSHH
Rx
32
1
23
VREF
SDI
VCM
MEN
22
3
21
4
100nF
AVDD
3.3V
5
CHOP_CLK
AS8515
AVSS
20
DVDD
ETR
DVSS
18
ETS
13
100nF
12V
Battery
100µohm
SCLK
VCC
200nF
VBAT
-
14
15
16
100nF
12
Diode
VSENSE_GND
11
CLIN
10
9
17
CSB
2.2µF
LIN
VSS
8
VSUP
VSENSE
SDO
VSENSE_IN
+
3.3V
19
6
7
Optional
22µF
SUP
Diode
µC
Load
Note: VSENSE_IN, VSENSE_GND, MEN, and CHOP_CLK should be left unconnected.
Note: Keep the differential input signal lines short, symmetric, and as close as possible. Use of PCB shielding layers is recommended, but
consider Eddy currents for fast changes in shunt current and related parasitic signal / ground shift generation.
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Revision 0.7
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AS8515
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
11 Package Drawings and Markings
The devices are available in a 32-pin MLF (5x5 mm) package.
Figure 34. Package Drawings and Dimensions
AS8515
YYWWVZZ
@
www.ams.com
Revision 0.7
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AS8515
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
Symbol
A
A1
A2
A3
L
θ
b
D
E
e
D1
E1
Min
0.80
0
0.30
0º
0.18
Nom
0.90
0.02
0.65
0.20 REF
0.40
0.25
5.00 BSC
5.00 BSC
0.50 BSC
4.75 BSC
4.75 BSC
Max
1.00
0.05
1.00
Symbol
D2
E2
aaa
bbb
ccc
ddd
eee
fff
N
0.50
14º
0.30
Min
3.40
3.40
-
Nom
3.50
3.50
0.15
0.10
0.10
0.05
0.08
0.10
32
Max
3.60
3.60
-
Notes:
1.
2.
3.
4.
5.
Dimensions and tolerancing conform to ASME Y14.5M -1994.
All dimensions are in millimeters. Angles are in degrees.
Bilateral coplanarity zone applies to the exposed pad as well as the terminal.
Radius on terminal is optional.
N is the total number of terminals.
Marking: YYWWVZZ.
YY
WW
V
ZZ
@
Last two digits of the
manufacturing year
Manufacturing Week
Plant Identifier
Traceability Code
Sublot identifier
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Revision 0.7
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AS8515
Datasheet - R e v i s i o n H i s t o r y
Revision History
Revision
Date
Owner
Description
0.1
Dec 16, 2011
zmo/mbr
Initial draft
0.2
Jan 25, 2012
0.3
Mar 07, 2012
0.4
Aug 14, 2012
0.5
Nov 22, 2012
0.6
Mar 22, 2013
0.7
Jul 26, 2013
Jul 31, 2013
Updated table information on LIN Driver (page 24)
Pins 10, 11 updated in the file (Pin Assignments, Figure 33)
zmo
Updated power dissipation info in Absolute Maximum Ratings (page 7)
Updated Table 14, Figure 33.
Updated Operating Conditions, Electrical Characteristics, Ordering
Information, Figure 12. Table 30, Table 32, Table 33, Table 45.
zmo/mbr
Table 1 and Table 6 updated.
zmo
Updated Table 30, added Figure 26 and notes to Table 35, modified
Table 30, updated information in Figure 26.
mbr
Updated AS8515 Block Diagram Figure 1.
Note: Typos may not be explicitly mentioned under revision history.
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Revision 0.7
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AS8515
Datasheet - O r d e r i n g I n f o r m a t i o n
12 Ordering Information
The devices are available as the standard products shown in Table 50.
Table 50. Ordering Information
Ordering Code
Description
Delivery Form
AS8515-ZMFP
Data acquisition system with power management
and LIN transceiver
Tape & Reel (5000 pcs)
AS8515-ZMFM
Tape & Reel (500 pcs)
Package
32-pin MLF (5x5 mm)
Note: All products are RoHS compliant and ams green.
Buy our products or get free samples online at ICdirect: http://www.ams.com/ICdirect
Technical Support is available at http://www.ams.com/Technical-Support
For further information and requests, please contact us mailto: [email protected]
or find your local distributor at http://www.ams.com/distributor
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Revision 0.7
64 - 65
AS8515
Datasheet - C o p y r i g h t s
Copyrights
Copyright © 1997-2013, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights
reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the
copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior
to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal
commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability
applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing
by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard
production flow, such as test flow or test location.
The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third
party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the
technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other
services.
Contact Information
Headquarters
ams AG
Tobelbaderstrasse 30
A-8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.ams.com/contact
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Revision 0.7
65 - 65