LP38855 1.5A Fast-Response High-Accuracy LDO Linear Regulator with Enable General Description Features The LP38855 is a high-current, fast-response regulator which can maintain output voltage regulation with an extremely low input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: VBIAS provides power for the internal bias and control circuits, as well as drive for the gate of the N-MOS power transistor, while VIN supplies power to the load. The use of an external bias rail allows the part to operate from ultra low VIN voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an NMOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. The fast transient response of this device makes it suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The LP38855 is available in TO-220 and TO-263 5-Lead packages. Dropout Voltage: 130 mV (typical) at 1.5A load current. Low Ground Pin Current: 14 mA (typical) at 1.5A load current. Shutdown Current: 1 µA (typical) IIN(GND) when EN pin is low. Precision Output Voltage: ±1.0% for TJ = 25°C and ±2.0% for 0°C ≤ TJ ≤ +125°C, across all line and load conditions ■ ■ ■ ■ ■ ■ ■ ■ ■ Standard VOUT values of 0.8V and 1.2V Wide VBIAS Supply operating range of 3.0V to 5.5V Stable with 10 µF ceramic capacitors Dropout voltage of 130 mV (typical) at 1.5A load current Precision Output Voltage across all line and load conditions: — ±1.0% for TJ = 25°C — ±2.0% for 0°C ≤ TJ ≤ +125°C — ±3.0% for -40°C ≤ TJ ≤ +125°C Over-Temperature and Over-Current protection Available in 5 lead TO-220 and TO-263 packages Custom VOUT values between 0.8V and 1.2V are available -40°C to +125°C Operating Temperature Range Applications ■ ASIC Power Supplies In: - Desktops, Notebooks, and Graphics Cards, Servers - Gaming Set Top Boxes, Printers and Copiers ■ Server Core and I/O Supplies ■ DSP and FPGA Power Supplies ■ SMPS Post-Regulator Typical Application Circuit 20202601 © 2007 National Semiconductor Corporation 202026 www.national.com LP38855 1.5A Fast-Response High-Accuracy LDO Linear Regulator with Enable December 2006 LP38855 Ordering Information VOUT * Order Number Package Type Package Drawing LP38855S-0.8 TO263-5 TS5B Rail of 45 0.8V LP38855SX-0.8 TO263-5 TS5B Tape and Reel of 500 LP38855T-0.8 TO220-5 T05D Rail of 45 1.2V Supplied As LP38855S-1.2 TO263-5 TS5B Rail of 45 LP38855SX-1.2 TO263-5 TS5B Tape and Reel of 500 LP38855T-1.2 TO220-5 T05D Rail of 45 * For custom VOUT values between 0.8V and 1.2V please contact the National Semiconductor Sales Office. Connection Diagrams 20202603 20202602 TO-220, Top View TO-263, Top View Pin Descriptions TO220–5 and TO263–5 Packages Pin # Pin Symbol 1 EN The device Enable pin. 2 IN The unregulated input voltage pin 3 GND Ground 4 OUT The regulated output voltage pin 5 BIAS The supply for the internal control and reference circuitry TAB TAB The TAB is a thermal connection that is physically attached to the backside of the die, and is used as a thermal heat-sink connection. See the Application Information section for details www.national.com Pin Description 2 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Range Lead Temperature Soldering, 5 seconds ESD Rating Human Body Model (Note 2) Power Dissipation (Note 3) VIN Supply Voltage (Survival) VBIAS Supply Voltage (Survival) −65°C to +150°C Operating Ratings 260°C −0.3V to +6.0V −0.3V to +6.0V Internally Limited −40°C to +150°C (Note 1) VIN Supply Voltage VBIAS Supply Voltage VEN Enable Input Voltage IOUT Junction Temperature Range (Note 3) ±2 kV Internally Limited −0.3V to +6.0V −0.3V to +6.0V (VOUT + VDO) to VBIAS 3.0V to 5.5V 0.0V to VBIAS 0 mA to 1.5A −40°C to +125°C Electrical Characteristics Unless otherwise specified: VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF, CBIAS = 1µF, VEN = VBIAS. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Symbol Parameter Conditions VOUT(NOM) + 1V ≤ VIN ≤ VBIAS, 3.0V ≤ VBIAS ≤ 5.5V, 10 mA ≤ IOUT ≤ 1.5A VOUT Output Voltage Tolerance MIN TYP MAX -1.0 -3.0 0 +1.0 +3.0 VOUT(NOM) + 1V ≤ VIN ≤ VBIAS, 3.0V ≤ VBIAS ≤ 5.5V, 10 mA ≤ IOUT ≤ 1.5A, Units % -2.0 0 +2.0 0°C ≤ TJ ≤ 125°C Line Regulation, VIN (Note 4) VOUT(NOM) + 1V ≤ VIN ≤ VBIAS - 0.04 - %/V ΔVOUT/ΔVBIAS Line Regulation, VBIAS (Note 4) 3.0V ≤ VBIAS ≤ 5.5V - 0.10 - %/V ΔVOUT/ΔIOUT Output Voltage Load Regulation (Note 5) 10 mA ≤ IOUT ≤ 1.5A - 0.2 - %/A Dropout Voltage VIN − VOUT (Note 6) IOUT = 1.5A - 130 165 180 mV - 7.0 8.5 9.0 ΔVOUT/ΔVIN VDO LP38855-0.8 10 mA ≤ IOUT ≤ 1.5A IGND(IN) IGND(BIAS) Ground Pin Current Drawn from VIN Supply Ground Pin Current Drawn from VBIAS Supply LP38855-1.2 10 mA ≤ IOUT ≤ 1.5A - 11 VEN ≤ 0.5V - 1.0 10 300 µA 10 mA ≤ IOUT ≤ 1.5A - 3.0 3.8 4.5 mA VEN ≤ 0.5V - 100 170 200 µA 2.20 2.00 2.45 2.70 2.90 V 60 50 150 300 350 mV - 4.5 - A UVLO Under-Voltage Lock-Out Threshold VBIAS rising until device is functional UVLO(HYS) Under-Voltage Lock-Out Hysteresis VBIAS falling from UVLO threshold until device is non-functional Output Short-Circuit Current VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, VOUT = 0.0V ISC mA 12 15 3 www.national.com LP38855 VEN Voltage (Survival) VOUT Voltage (Survival) IOUT Current (Survival) Junction Temperature Absolute Maximum Ratings (Note 1) LP38855 Symbol Parameter Conditions MIN TYP MAX - 0.01 - VEN = 0.0V, VBIAS = 5.5V -19 -13 -30 -40 -51 Units ENABLE Pin VEN = VBIAS IEN ENABLE pin Current µA VEN(ON) Enable Voltage Threshold VEN rising until Output = ON 1.00 0.90 1.25 1.50 1.55 V VEN(HYS) Enable Voltage Hysteresis VEN falling from VEN(ON) until Output = OFF 50 30 100 150 200 mV tOFF Turn-OFF Delay Time RLOAD × COUT << tOFF - 20 - tON Turn-ON Delay Time RLOAD × COUT << tON - 15 - VIN = VOUT +1V, f = 120 Hz - 80 - VIN = VOUT + 1V, f = 1 kHz - 65 - VBIAS = VOUT + 3V, f = 120 Hz - 58 - VBIAS = VOUT + 3V, f = 1 kHz - 58 - f = 120 Hz - 1 - BW = 10 Hz − 100 kHz - 150 - BW = 300 Hz − 300 kHz - 90 - Thermal Shutdown Junction Temperature - 160 - Thermal Shutdown Hysteresis - 10 - µs AC Parameters PSRR (VIN) PSRR (VBIAS) Ripple Rejection for VIN Input Voltage Ripple Rejection for VBIAS Voltage Output Noise Density en Output Noise Voltage dB dB µV/√Hz µVRMS Thermal Parameters TSD TSD(HYS) θJA Thermal Resistance, Junction to Ambient(Note 3) TO220-5 - 60 - TO263-5 - 60 - θJC Thermal Resistance, Junction to Case(Note 3) TO220-5 - 3 - TO263-5 - 3 - °C °C/W Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. Note 2: The Human Body Model (HBM) is a 100 pF capacitor discharged through a 1.5k resistor into each pin. Test method is per JESD22-A114. The HBM rating for device pin 1 (EN) is ±1.5 kV. Note 3: Device power dissipation must be de-rated based on device power dissipation (TD), ambient temperature (TA), and package junction to ambient thermal resistance (θJA). Additional heat-sinking may be required to ensure that the device junction temperature (TJ) does not exceed the maximum operating rating. See the Application Information section for details. Note 4: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Note 5: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Note 6: Dropout voltage is defined the as input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to drop 2% from the nominal value. www.national.com 4 VBIAS Ground Pin Current (IGND(BIAS)) vs VBIAS VBIAS Ground Pin Current (IGND(BIAS)) vs Temperature 20202687 20202661 VIN Ground Pin Current (IGND(IN)) vs Temperature Load Regulation vs Temperature 20202662 20202663 Dropout Voltage (VDO) vs Temperature Output Current Limit (ISC) vs Temperature 20202665 20202666 5 www.national.com LP38855 Typical Performance Characteristics Unless otherwise specified: TJ = 25°C, VIN = VOUT(NOM) + 1V, VBIAS = 3.0V, IOUT = 10 mA, CIN = COUT = 10 µF Ceramic, CBIAS = 1 µF Ceramic, VEN = VBIAS. LP38855 VOUT vs Temperature UVLO Thresholds vs Temperature 20202668 20202667 Enable Thresholds (VEN) vs Temperature Enable Pull-Down Current (IEN) vs Temperature 20202672 20202673 Enable Pull-Up Resistor (rEN) vs Temperature VIN Line Transient Response 20202674 www.national.com 20202677 6 LP38855 VIN Line Transient Response VBIAS Line Transient Response 20202678 20202679 Load Transient Response, COUT = 10 μF Ceramic VBIAS Line Transient Response 20202680 20202681 Load Transient Respose, COUT = 10 μF Ceramic Load Transient Response, COUT = 100 μF Ceramic 20202682 20202683 7 www.national.com LP38855 Load Transient Response, COUT = 100 μF Ceramic Load Transient Response, COUT = 100 μF Tantalum 20202684 20202685 Load Transient Response, COUT = 100 μF Tantalum VBIAS PSRR 20202686 20202670 VIN PSRR Output Noise 20202671 www.national.com 20202669 8 LP38855 Block Diagram 20202605 9 www.national.com LP38855 SUPPLY SEQUENCING There is no requirement for the order that VIN or VBIAS are applied or removed. However, the output voltage cannot be guaranteed until both VIN and VBIAS are within the range of guaranteed operating values. If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommend for this diode clamp. Application Information EXTERNAL CAPACITORS To assure regulator stability, capacitors are required on the input, output and bias pins as shown in the Typical Application Circuit. Output Capacitor A minimum output capacitance of 10 µF, ceramic, is required for stability. The amount of output capacitance can be increased without limit. The output capacitor must be located less than 1 cm from the output pin of the IC and returned to the device ground pin with a clean analog ground. Only high quality ceramic types such as X5R or X7R should be used, as the Z5U and Y5F types do not provide sufficient capacitance over temperature. Tantalum capacitors will also provide stable operation across the entire operating temperature range. However, the effects of ESR may provide variations in the output voltage during fast load transients. Using the minimum recommended 10 µF ceramic capacitor at the output will allow unlimited capacitance, Tantalum and/or Aluminum, to be added in parallel. REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. The NMOS pass element, by design, contains no body diode. This means that, as long as the gate of the pass element is not driven, there will not be any reverse current flow through the pass element during a reverse voltage event. The gate of the pass element is not driven when VBIAS is below the UVLO threshold, or the EN pin is held low. When VBIAS is above the UVLO threshold, and the EN pin is above the VEN(ON) threshold, the control circuitry is active and will attempt to regulate the output voltage. Since the input voltage is less than the output voltage the control circuit will drive the gate of the pass element to the full VBIAS potential when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin, limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 μF in this manner will not damage the device as the current will decay rapidly. However, continuous reverse current should be avoided. Input Capacitor The input capacitor must be at least 10 µF, but can be increased without limit. It's purpose is to provide a low source impedance for the regulator input. A ceramic capacitor, X5R or X7R, is recommended. Tantalum capacitors may also be used at the input pin. There is no specific ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytic capacitors can be used, but are not recommended as their ESR increases very quickly at cold temperatures. They are not recommended for any application where the ambient temperature falls below 0°C. ENABLE OPERATION The Enable pin (EN) provides a mechanism to enable, or disable, the regulator output stage. The Enable pin has an internal pull-up, through a typical 180 kΩ resistor, to VBIAS. If the Enable pin is actively driven, pulling the Enable pin above the VEN threshold of 1.25V (typical) will turn the regulator output on, while pulling the Enable pin below the VEN threshold will turn the regulator output off. There is approximately 100 mV of hysteresis built into the Enable threshold provide noise immunity. If the Enable function is not needed this pin should be left open, or connected directly to VBIAS. If the Enable pin is left open, stray capacitance on this pin must be minimized, otherwise the output turn-on will be delayed while the stray capacitance is charged through the internal resistance (rEN). Bias Capacitor The capacitor on the bias pin must be at least 1 µF. It can be any good quality capacitor (ceramic is recommended). INPUT VOLTAGE The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage, which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is used for VBIAS. BIAS VOLTAGE The bias voltage (V BIAS) is a low current external voltage rail required to bias the control circuitry and provide gate drive for the N-FET pass transistor. The bias voltage must be in the range of 3.0V to 5.5V to ensure proper operation of the device. POWER DISSIPATION AND HEAT-SINKING A heat-sink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is the sum of three different points of dissipation in the device. The first part is the power that is dissipated in the NMOS pass element, and can be determined with the formula: UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V. As the bias voltage rises above the UVLO threshold the device control circuitry become active. There is approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity. When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the device will be functional, but the operating parameters will not be within the guaranteed limits. www.national.com PD(PASS) = (VIN - VOUT) × IOUT 10 (1) PD(BIAS) = VBIAS × IGND(BIAS) (2) where IGND(BIAS) is the portion of the operating ground current of the device that is related to VBIAS. The third part is the power that is dissipated in portions of the output stage circuitry, and can be determined with the formula: PD(IN) = VIN × IGND(IN) (3) where IGND(IN) is the portion of the operating ground current of the device that is related to VIN. The total power dissipation is then: PD = PD(PASS) + PD(BIAS) + PD(IN) (4) The maximum allowable junction temperature rise (ΔTJ) depends on the maximum anticipated ambient temperature (TA (MAX)) for the application, and the maximum allowable operating junction temperature (TJ(MAX)): 20202625 FIGURE 1. θJA vs Copper (1 Ounce) Area for the TO-263 package As shown in Figure 1, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the TO-263 package mounted to a PCB is 32°C/W. Figure 2 shows the maximum allowable power dissipation for TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. (5) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: (6) Heat-Sinking The TO-220 Package The TO-220 package has a θJA rating of 60°C/W, and a θJC rating of 3°C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. The thermal resistance of a TO-220 package can be reduced by attaching it to a heat-sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for TO-263 package. The heat-sink to be used in the application should have a heat-sink to ambient thermal resistance, θHA: (7) where θJA is the required total thermal resistance from the junction to the ambient air, θCH is the thermal resistance from the case to the surface of the heat sink, and θJC is the thermal resistance from the junction to the surface of the case. For this equation, θJC is about 3°C/W for a TO-220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. Consult the heat-sink manufacturer datasheet for details and recommendations. 20202626 FIGURE 2. Maximum Power Dissipation vs Ambient Temperature for TO-263 package Heat-Sinking The TO-263 Package The TO-263 package has a θJA rating of 60°C/W, and a θJC rating of 3°C/W. These ratings are for the package only, no additional heat-sinking, and with no airflow. 11 www.national.com LP38855 The TO-263 package uses the copper plane on the PCB as a heat-sink. The tab of this package is soldered to the copper plane for heat-sinking. The graph below shows a curve for the θJA of TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat-sinking. The second part is the power that is dissipated in the bias and control circuitry, and can be determined with the formula: LP38855 Physical Dimensions inches (millimeters) unless otherwise noted TO220 5-lead, Molded, Stagger Bend Package (TO220-5) NS Package Number T05D TO263 5-Lead, Molded, Surface Mount Package (TO263-5) NS Package Number TS5B www.national.com 12 LP38855 Notes 13 www.national.com LP38855 1.5A Fast-Response High-Accuracy LDO Linear Regulator with Enable Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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