APA2071 Stereo 3.1W Non-inverting Audio Power Amplifier(with DC Volume Control) General Description Features • • • Non-Inverting Audio Power Amplifier The APA2071 is a monolithic integrated circuit, which Low Operating Current about 9mA (Typical) provides precise DC volume control, and a stereo bridged audio power amplifiers capable of producing Improved Depop Circuitry to Eliminate Turn-On 2.6W (2W) into 4Ω with less than 10% (1.0%) THD+N. The attenuator range of the volume control in APA2071 is and Turn-Off Transients in Outputs • 32-Step Volume Adjustable by DC Voltage from 18dB (VVOLUME=0V) to -80dB (VVOLUME=3.54V) with 32 steps. The advantage of internal gain setting can be less with Hysteresis • Output Power components and PCB area. Both the depop circuitry and the thermal shutdown protection circuitry are integrated at 1% THD+N - 2.4W, at VDD=5V, BTL Mode, RL=3Ω in the APA2071, that reduce pops and clicks noise during power up or shutdown mode operation. It also im- - 2W, at VDD=5V, BTL Mode, RL=4Ω proves the power off pop noise and protects the chip being destroyed by over temperature and short current at 10% THD+N - 3.1W, at VDD=5V, BTL Mode, RL=3Ω failure. To simplify the audio system design, the APA2071 combines a stereo bridge-tied load (BTL) mode for - 2.6W, at VDD=5V, BTL Mode, RL=4Ω • Two Output Modes: BTL and SE Modes Selected • by SE/BTL Pin speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are Low Current Consumption in Shutdown Mode easily switched by the SE/BTL input control pin signal. (1µA, Typical) • • Short Circuit Protection Thermal Shutdown Protection and Over Current Applications Protection Circuitry • • • The OUTN Signal and the INN Signal are Inphase • Notebook PC Power Enhanced Package (DIP-16 / DIP-16A) • LCD Monitor or TV Lead Free and Green Devices Available (RoHS Compliant) Simplified Application Circuit L-CH Input LINN R-CH Input RINN LOUTN Stereo Speaker Stereo Headphone LOUTP APA2071 ROUTN DC Volume Control VOLUME ROUTP ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 1 www.anpec.com.tw APA2071 Ordering and Marking Information Package Code J : DIP-16 / DIP-16A Operating Ambient Temperature Range I : - 40 to 85 °C Handling Code TU : Tube Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APA2071 Assembly Material Handling Code Temperature Range Package Code APA2071 J : APA2071 XXXXX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration SHUTDOWN BYPASS RINN GND GND LINN VOLUME SE/BTL 1 2 3 4 5 6 7 8 APA2071 Absolute Maximum Ratings Symbol VDD TA TJ ROUTP VDD ROUTN GND GND LOUTN VDD LOUTP (Note 1) Parameter Rating Unit -0.3 to 6 V Input Voltage (SE/BTL, SHUTDOWN, VOLUME, RINN, LINN to GND) -0.3 to VDD+ 0.3 V Output Voltage (LOUTN, LOUTP, ROUTP, ROUTN to GND) -0.3 to VDD+ 0.3 V Supply Voltage (VDD to GND) Operating Ambient Temperature Range Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds PD 16 15 14 13 12 11 10 9 -40 to 85 ο 150 ο C C ο -65 to +150 Power Dissipation C ο 260 C Internally Limited W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Typical Value Junction-to-Ambient Resistance in Free Air (Note 2) Junction-to-Case Resistance in Free Air (Note 3) Unit 45 o 8 o C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3: The case temperature is measured at the center of the GND pin on the beside of the DIP-16 / DIP-16A package. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 2 www.anpec.com.tw APA2071 Recommended Operating Conditions Symbol VDD VIH VIL (Note 4) Parameter Range Supply Voltage Unit 3.3 ~ 5.5 High Level Threshold Voltage Low Level Threshold Voltage SHUTDOWN 0.4VDD ~ VDD SE/BTL 0.8VDD ~ VDD SHUTDOWN 0 ~ 1.0 SE/BTL 0 ~ 1.0 VCIM Common Mode Input Voltage TA Ambient Temperature Range -40 ~ 80 TJ Junction Temperature Range -40 ~ 125 RL Speaker Resistance RL Headphone Resistance V ~ VDD-1.0 ο C 3~ Ω 16 ~ Note 4 : Refer to the typical application circuit Electrical Characteristics Unless otherwise specified, these specifications apply over VDD=5V, VGND=0V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol IDD ISD TSTART-UP Ri Parameter APA2071 Test Conditions Unit Min. Typ. Max. VSE/BTL =0V - 9 20 VSE/BTL=5V - 4 10 Shutdown Current VSE/BTL=0V, VSHUTDOWN =0V - 1 - Start-Up Time from Shutdown CBYPASS=2.2µF - 1.6 - s - 20 - kΩ VDD=5.5V,THD+N=3%, RL=3Ω - 3.1 - THD+N=10%, RL=3Ω - 3.1 - THD+N =10%, RL=4Ω - 2.6 - THD+N =10%, RL=8Ω - 1.6 - THD+N =1%, RL=3Ω - 2.4 - THD+N =1%, RL=4Ω - 2 - THD+N =0.5%, RL=8Ω 1 1.3 - PO=1.2W, RL=4Ω, fin=1kHz - 0.09 - PO=0.9W, RL=8Ω, fin=1kHz - 0.12 - - 60 - dB - 90 - dB Supply Current Input Resistance mA BTL MODE. VDD=5V, GAIN=6dB (UNLESS OTHERWISE NOTED) PO THD+N PSRR Crosstalk Output Power, fin=1kHz Total Harmonic Distortion Pulse Noise Power Supply Rejection Ratio Channel Separation Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 W % VDD Ripple=0.1Vrms, RL=8Ω, CBYPASS=2.2µF, fin=217Hz CBYPASS=2.2µF, RL=8Ω, fin=1kHz 3 www.anpec.com.tw APA2071 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VDD=5V, VGND=0V and TA= -40 ~ 85 oC. Typical values are at TA=25oC. Symbol Parameter APA2071 Test Conditions Min. Unit Typ. Max. BTL MODE. VDD=5V, GAIN=6dB (UNLESS OTHERWISE NOTED) (CONT.) VOS Output Offset Voltage S/N Signal to Noise Ratio RL=4Ω - 5 - mV PO=1.1W, RL=8Ω, A_weighting - 95 - dB THD+N=10%, RL=16Ω - 220 - THD+N =10%, RL=32Ω - 120 - THD+N =1%, RL=16Ω - 160 - THD+N =1%, RL=32Ω - 95 - PO=125mW, RL=16Ω, fin=1kHz - 0.12 - PO=65mW, RL=32Ω, fin=1kHz - 0.11 - - 60 - dB SE MODE. VDD=5V, GAIN=0dB Po THD+N PSRR Crosstalk Output Power, fin=1kHz Total Harmonic Distortion Pulse Noise Power Supply Rejection Ratio VDD Ripple =0.1Vrms, RL=32Ω, CBYPASS =2.2µF, fin=217Hz mW % Channel Separation CBYPASS=2.2µF, RL=32Ω, fin=1kHz - 60 - dB VOS Output Offset Voltage RL=32Ω - 5 - mV S/N Signal to Noise Ratio PO=75mW, RL=32Ω, A_weighting - 100 - dB Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 4 www.anpec.com.tw APA2071 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 10 RL = 4Ω THD+N (%) 1 VDD = 5V AV =12dB fin = 1kHz SE Mode RL = 3Ω THD+N (%) VDD = 5V AV =18dB fin = 1kHz BTL Mode RL = 8Ω 0.1 0.01 1 RL = 16Ω RL = 32Ω 0.1 0 0.5 1 1.5 2 2.5 Output Power (W) 3 0.01 3.5 0 40m THD+N vs. Output Power 10 VDD = 5V AV =18dB RL =3Ω BTL Mode VDD = 5V fin =1kHz RL =3Ω BTL Mode THD+N (%) THD+N (%) 160m 200m 240m 120m Output Power (W) THD+N vs. Output Power 10 80m 1 AV = 18dB fin = 20kHz 1 fin= 20Hz 0.1 fin= 1kHz AV = 6dB 0.01 0 0.5 1 1.5 2 2.5 Output Power (W) 0.1 3 0.05 10m 3.5 THD+N vs. Frequency VDD = 5V RL =3Ω PO = 1.8W BTL Mode 1 AV=18dB 0.1 VDD = 5V AV = 6dB RL =3Ω BTL Mode 1 PO=1.8W 0.1 AV=6dB 0.01 20 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 5 THD+N vs. Frequency 10 THD+N (%) THD+N (%) 10 100m 1 Output Power (W) PO=0.9W 0.01 10k 20k 5 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2071 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 THD+N (%) VDD = 5V fin =1kHz RL =4Ω BTL Mode THD+N (%) 1 AV = 18dB fin = 20Hz 0.1 0.1 fin = 1kHz VDD = 5V AV =18dB RL =4Ω BTL Mode 0.01 10m 100m 1 Output Power (W) AV = 6dB 0.01 fin= 20kHz 1 0 0.5 1 1.5 2 2.5 3 3.5 Output Power (W) THD+N vs. Frequency THD+N vs. Frequency 10 10 VDD = 5V AV= 6dB RL=4Ω BTL Mode 1 1 THD+N (%) THD+N (%) VDD = 5V RL=4Ω PO=1.5W BTL Mode AV=6dB 0.1 PO=1.5W 0.1 AV=18dB 0.01 20 100 PO=0.8W 1k 0.01 10k 20k 20 100 Frequency (Hz) VDD = 5V fin= 1kHz RL=8Ω BTL Mode THD+N (%) THD+N (%) 10k 20k THD+N vs. Output Power 10 1 AV = 6dB VDD = 5V AV = 18dB RL=8Ω BTL Mode 1 fin = 20kHz fin = 20Hz 0.1 0.1 fin = 1kHz AV = 18dB 0.01 1k Frequency (Hz) THD+N vs. Output Power 10 5 0 0.5 1 1.5 2 2.5 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 3 0.01 10m 3.5 100m 1 5 Output Power (W) 6 www.anpec.com.tw APA2071 Typical Operating Characteristics (Cont.) THD+N vs. Frequency THD+N vs. Frequency 10 VDD = 5V AV = 6dB RL=8Ω BTL Mode THD+N (%) THD+N (%) 10 1 PO=0.5W VDD=5V RL=8Ω PO=0.9W BTL Mode 1 AV=6dB 0.1 0.1 AV=18dB PO=0.9W 0.01 20 100 1k Frequency (Hz) 0.01 10k 20k 20 VDD=5V fin=1kHz RL=16Ω SE Mode 1 AV = 0dB 0.1 VDD=5V AV=12dB RL=16Ω CO=1000µF 1 SE Mode fin = 20kHz 0 fin = 1kHz 0.01 40m 80m 120m 160m 200m 240m 10m 50m 100m 200m 300m Output Power (W) Output Power (W) THD+N vs. Frequency THD+N vs. Frequency 10 VDD=5V RL=16Ω PO=125mW CO=1000µF SE Mode 1 THD+N (%) THD+N (%) 10 AV=0dB 0.1 VDD=5V AV=0dB RL=16Ω CO=1000µF SE Mode 1 PO=125mW 0.1 AV=12dB 0.01 fin = 20Hz 0.1 AV = 12dB 0.01 10k 20k 10 THD+N (%) THD+N (%) 1k Frequency (Hz) THD+N vs. Output Power THD+N vs. Output Power 10 100 20 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 PO=60mW 0.01 10k 20k 7 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2071 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 VDD=5V AV=12dB RL=32Ω CO=1000µF SE Mode VDD=5V fin=1kHz RL=32Ω SE Mode THD+N (%) THD+N (%) 10 1 AV = 0dB 1 fin = 20Hz fin = 20kHz 0.1 0.1 AV = 12dB 0.01 40m 0 80m fin = 1kHz 0.01 10m 120m 160m 200m 240m 50m THD+N vs. Frequency THD+N (%) THD+N (%) THD+N vs. Frequency 10 VDD=5V RL=32Ω PO=65mW CO=1000µF SE Mode 1 200m300m Output Power (W) Output Power (W) 10 100m AV=0dB VDD=5V AV=12dB RL=32Ω CO=1000µF SE Mode 1 PO=65mW 0.1 0.1 AV=12dB 0.01 20 PO=30mW 0.01 100 1k Frequency (Hz) 10k 20k 20 100 Frequency Response 1k Frequency (Hz) 10k 20k Frequency Response +20 +20 +80 +80 Amplitude( 14dB) +0 Phase( 6dB) +8 +4 +0 -40 VDD=5V RL=4Ω PO=0.8W BTL Mode 10 100 Amplitude( 6dB) 1k 10k 200k Amplitude(dB) Phase( 14dB) +12 +16 Phase (Degrees) Amplitude(dB) +40 Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 Phase( 14dB) +12 +8 +4 -120 +0 10 8 +0 Phase( 6dB) -80 Frequency (Hz) +40 -40 VDD=5V RL=8Ω PO=0.5W BTL Mode 100 Amplitude( 6dB) 1k 10k Frequency (Hz) Phase (Degrees) Amplitude( 14dB) +16 -80 200k -120 www.anpec.com.tw APA2071 Typical Operating Characteristics (Cont.) Frequency Response Frequency Response +14 +40 +10 +0 Phase(0dB) +0 -40 Amplitude(0dB) VDD=5V RL=16Ω CO=1000µF PO=60mW SE Mode -4 -8 10 100 +80 1k 10k Frequency (Hz) 200k +0 +4 Phase(0dB) -40 +0 -80 -4 -120 -8 Amplitude(0dB) VDD=5V RL=32Ω CO=1000µF PO=30mW SE Mode 10 Crosstalk(dB) Corsstalk(dB) -120 Right to Left Left to Right 20 100 1k +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 Left to Right -120 20 10k 20k 100 -30 VDD=5V RL=16Ω CO=1000µF PO=125mW SE Mode -10 -20 -40 Right to Left -60 Left to Right -30 -50 -80 -80 -90 -90 -100 20 -100 Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 9 Right to Left -60 -70 10k 20k VDD=5V RL=32Ω CO=1000µF PO=65mW SE Mode -40 -70 100 1k Frequency (Hz) 10k 20k Crosstalk vs. Response +0 -50 1k Frequency (Hz) Corsstalk(dB) Corsstalk(dB) -20 -120 Right to Left Crosstalk vs. Response -10 200k VDD=5V RL=4Ω PO=1.5W BTL Mode Frequency (Hz) +0 10k Crosstalk vs. Frequency -50 -60 -70 -110 1k Frequency (Hz) VDD=5V RL=8Ω PO=0.9W BTL Mode -80 -90 -100 -80 100 Crosstalk vs. Frequency +0 -10 -20 -30 -40 +40 Phase(12dB) Phase (Degrees) +4 Amplitude(dB) Phase(12dB) Phase (Degrees) Amplitude(dB) +14 Amplitude(12dB) Amplitude(12dB) +10 +80 Left to Right 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2071 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency Output Noise Voltage vs. Frequency 100µ Output Noise Voltage(dB) Output Noise Voltage(dB) 100µ Filter BW<22kHz 20µ A-weighting 10µ VDD=5V AV=6dB RL=4Ω BTL Mode 1µ 20 100 1k Filter BW<22kHz 20µ 10µ A-weighting 1µ 20 10k 20k VDD=5V AV=0dB RL=32Ω SE Mode 100 Frequency (Hz) PSRR vs. Frequency PSRR vs. Frequency +0 PSRR(dB) VDD=5V RL=4Ω VIN=200mV AV=18dB BTL Mode -10 -20 -30 PSRR(dB) -20 -30 -40 -50 -60 -50 -60 -70 -80 -80 -90 -90 20 100 1k -100 20 10k 20k VDD=5V RL=32Ω VIN=200mV AV=12dB SE Mode -40 -70 -100 100 Frequency (Hz) 10k 20k Shutdown Attenuation vs. Frequency +0 VDD=5V RL=8Ω VIN=1Vrms AV=6dB BTL Mode Shutdown Attenuation(dB) Mute Attenuation(dB) 1k Frequency (Hz) Mute Attenuation vs. Frequency +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 10k 20k Frequency (Hz) +0 -10 1k -10 -20 -30 -40 VDD=5V RL=8Ω VIN=1Vrms AV=6dB BTL Mode -50 -60 -70 -80 -90 -100 -110 20 100 1k 10k -120 20 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 100 10k 20k 1k Frequency (Hz) 10 www.anpec.com.tw APA2071 Typical Operating Characteristics (Cont.) Gain vs. Volume Voltage Supply Current vs. Supply Voltage 20 10.0 No Load 10 9.0 Down -10 Gain(dB) Supply Current (mA) 0 -20 Up -30 -40 -50 -60 VDD=5V No Load BTL Mode -70 BTL 8.0 7.0 6.0 5.0 SE 4.0 3.0 -80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 3.0 3.5 DC Voltage (V) 200 1.8 180 RL=3Ω 1.4 RL=4Ω 1.2 1.0 0.8 RL=8Ω 0.6 0.4 0.0 0.5 1.0 1.5 5.0 5.5 RL=8Ω 160 140 120 RL=16Ω 100 80 RL=32Ω 60 40 VDD=5V BTL Mode 0.2 0.0 4.5 Power Dissipation vs. Output Power Power Dissipation(mW) Power Dissipation(W) Power Dissipation vs.Output Power 2.0 1.6 4.0 Supply Voltage(V) 2.0 2.5 3.0 VDD=5V SE Mode 20 0 3.5 Output Power (W) 0 50 100 150 200 250 Output Power(mW) Output Power vs. Supply Voltage 4.0 Output Power (W) 3.5 3.0 RL=3Ω,THD+N=10% RL=4Ω,THD+N=10% RL=3Ω,THD+N=1% 2.5 2.0 1.5 1.0 0.5 0.0 BTL Mode RL=8Ω,THD+N=1% AV=6dB RL=8Ω,THD+N=10% RL=4Ω,THD+N=1% 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 11 www.anpec.com.tw APA2071 Pin Description PIN FUNCTION NO. NAME 1 SHUTDOWN 2 BYPASS 3 RINNN 4,5,12,13 GND Ground connection. Connect all of the GND pins to ground plane. 6 LINN Left channel input terminal 7 VOLUME 8 SE/BTL Output mode control input, high for SE output mode and low for BTL mode. 9 LOUTP Left channel positive output in BTL mode and high impedance in SE mode. 10,15 VDD 11 LOUTN Left channel negative output in BTL mode and SE mode. 14 ROUTN Right channel negative output in BTL mode and SE mode. 16 ROUTP Right channel positive output in BTL mode and high impedance in SE mode. Shutdown control pin. Pulling low the voltage on this pin shuts off the IC. In shutdown mode, the IC only draws 1µA (typical) of supply current. Bypass capacitor connection pin for the bias voltage generator. Right channel input terminal DC voltage input pin for internal volume gain setting (DC Volume control). Supply voltage input pin. Connect all of the VDD pins to supply voltage. Block Diagram LOUTN LINN DC Volume Control LOUTP RINN Bias Voltage Generator BYPASS ROUTN VOLUME ROUTP SE/BTL SHUTDOWN SE/BTL Mode Selection VDD Power and Depop Circuit Shutdown Circuit Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 12 GND www.anpec.com.tw APA2071 Typical Application Circuit VDD CS 0.1µ F VDD Ci 1µF L-CH Input 100 µ F GND 220 µ F LINN Control Pin Ring SE/BTL Signal LOUTP RINN R-CH Input CBYPASS Bias Voltage Generator 100k Ω 2.2 µ F 4Ω Shutdown SHUTDOWN Signal CC 220 µ F VOLUME SE/BTL Sleeve Tip Headphone Jack BYPASS ROUTN VDD 50k Ω 100kΩ 1kΩ 4Ω DC Volume Control Ci 1 µF VDD CC LOUTN SE/BTL Mode Selection 1k Ω ROUTP Shutdown Circuit Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 13 www.anpec.com.tw APA2071 DC Volume Control Table_BTL Mode G a in(dB) V o ltage Range (% of V D D ) V o ltage Range (V D D = 5 V ) H igh(%) L o w (%) Recommended (%) H igh(V) L o w (V) Recommended (V) 18 2.40 0 .00 0 .00 0 .12 0 .00 0.00 17.5 4.60 3 .40 4 .00 0 .23 0 .17 0.20 17 6.80 5 .60 6 .20 0 .34 0 .28 0.31 16.5 9.20 7 .80 8 .60 0 .46 0 .39 0.43 16 11.40 10.20 10.80 0 .57 0 .51 0.54 15.5 13.80 12.40 13.00 0 .69 0 .62 0.65 15 16.00 14.60 15.40 0 .80 0 .73 0.77 14.5 18.20 16.80 17.60 0 .91 0 .84 0.88 14 20.60 19.20 19.80 1 .03 0 .96 0.99 13 22.80 21.40 22.00 1 .14 1 .07 1.10 12 25.00 23.60 24.40 1 .25 1 .18 1.22 10 27.40 25.80 26.60 1 .37 1 .29 1.33 8 29.60 28.20 28.80 1 .48 1 .41 1.44 6 31.80 30.40 31.20 1 .59 1 .52 1.56 4 34.20 32.60 33.40 1 .71 1 .63 1.67 2 36.40 34.80 35.60 1 .82 1 .74 1.78 0 38.60 37.00 37.80 1 .93 1 .85 1.89 -2 41.00 39.40 40.20 2 .05 1 .97 2.01 -4 43.20 41.60 42.40 2 .16 2 .08 2.12 -7 45.60 43.80 44.60 2 .28 2 .19 2.23 -1 0 47.80 46.00 47.00 2 .39 2 .30 2.35 -1 3 50.00 48.40 49.20 2 .50 2 .42 2.46 -1 6 52.40 50.60 51.40 2 .62 2 .53 2.57 -1 9 54.60 52.80 53.80 2 .73 2 .64 2.69 -2 2 56.80 55.00 5 6.00 2 .84 2 .75 2.80 -2 5 59.20 57.40 58.20 2 .96 2 .87 2.91 -2 8 61.40 59.60 60.40 3 .07 2 .98 3.02 -3 1 63.60 61.80 62.80 3 .18 3 .09 3.14 -3 4 66.00 64.00 65.00 3 .30 3 .20 3.25 -3 7 68.20 66.40 67.20 3 .41 3 .32 3.36 -4 0 70.40 68.60 69.60 3 .52 3 .43 3.48 -8 0 100.00 70.80 100.00 5 .00 3 .54 5.00 Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 14 www.anpec.com.tw APA2071 Function Description Bridge-Tied Load (BTL) Operation need for an output coupling capacitor which is required in a single supply, SE configuration. The APA2071’s output stage of each channel, which consists of one pair of operational amplifiers, provides op- Single-Ended (SE) Operation tion for BTL operation shown as figure 1. To consider the single-supply SE configuration shown in Typical Application Circuit, a coupling capacitor is required to block the DC offset voltage from reaching the load. OUTN Volume Control amplifier output signal These capacitors can be quite large (approximately 33µF to 1000µF), so they tend to be expensive, occupy valu- OP1 able PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to RL the Output Coupling Capacitor). The rules described still OUTP Bias Voltage Generator hold with the addition of the following relationship: 1 ≤ 1 << 1 (1) Cbypass x 130kΩ 2RiCi 2RLCC OP2 Figure 1: APA2071 Internal Configuration (each channel) SE/BTL Mode Selection Function The power amplifier’s (OP1) gain is set by internal unity The best cost saving feature of APA2071 is that it can be switched easily between BTL and SE modes. This fea- gain and input audio signal comes from internal volume control amplifier while the second amplifier (OP2) is in- ture eliminates the requirement for an additional headphone amplifier in applications where internal stereo ternally fixed in a unity-gain, inverting configuration. Figure 1 shows that the output of OP1 is connected to the input to OP2, which results in the output signals of both amplifiers with identical in magnitude but out of phase speakers are driven in BTL mode but external headphone or speakers must be accommodated. Inside of the APA2071, two separated amplifiers drive OUTP and OUTN (See Figure 1). The SE/BTL input con- 180°. Consequently, the differential gain for each channel is 2 x (Gain of SE mode). The OUTN signal and the trols the operation of the follower amplifier that drives LOUTP and ROUTN. INN signal are inphase, and the OUTP signal and the INN signal are out of phase. By driving the load differentially through outputs OUTP and OUTN, an amplifier configuration is commonly re- When SE/BTL keeps low, the OP2 turns on and the APA2071 is in the BTL mode. • • ferred to bridged mode is established. BTL mode operation is different from the classical single-ended (SE) am- When SE/BTL keeps high, the OP2 is in a high output impedance state, which configures the APA2071 as SE driver from OUTP. IDD is reduced by approximately one-half in SE mode. plifier configuration where one side of its load is connected to the ground. A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the The control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack with switch pin as shown in the Typical Application Circuit. load, thus doubles the output swing for a specified supply voltage. When placed under the same conditions, a BTL amplifier has four times the output power of a SE amplifier. A BTL 1kΩ VDD 100kΩ configuration, such as the one used in APA2071, also creates a second advantage over SE amplifiers. Since Ring SE/BTL the differential outputs, ROUTP, ROUTN, LOUTP, and LOUTN, are biased at half-supply, it’s not necessary for Tip Sleeve Headphone Jack DC voltage to be across the load. This eliminates the Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 Control Pin Figure 2: SE/BTL Input Selection by Phonejack Plug 15 www.anpec.com.tw APA2071 Function Description (Cont.) SE/BTL Mode Selection Function (Cont.) For the highest accuracy, the voltage shown in the ‘recommended voltage’column of the table is used to select In Figure 2, input SE/BTL operates as below: When the phonejack plug is inserted, the 1kΩ resistor is a desired gain. This recommended voltage is exactly halfway between the two nearest transitions. The gain levels disconnected and the SE/BTL input is pulled high to enable the SE mode. Meanwhile, the OUTN amplifier shuts are 32 steps from 18dB to -40dB in BTL mode, and the last step at -80dB as mute mode. down which turns the speaker to be mute. The OUTP amplifier then drives through the output capacitor into the Shutdown Function headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is In order to reduce power consumption while not in use, the APA2071 contains a shutdown pin to externally turn connected from the signal pin, and the voltage divider is set up by resistors 100kΩ and 1kΩ. Resistor 1kΩ then is off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the pulled low the SE/BTL pin, enabling the BTL function. SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It would be better to DC Volume Control Function switch between the ground and the supply VDD to provide maximum device performance. The APA2071 has an internal stereo volume control whose setting is the function of the DC voltage applied to the By switching the SHUTDOWN pin to low, the amplifier VOLUME input pin. The APA2071 volume control consists of 32 steps that are individually selected by a variable DC enters a low-current state, IDD<1µA. APA2071 is in shutdown mode. On normal operation, SHUTDOWN pin is voltage level on the VOLUME control pin. The range of the steps, controlled by the DC voltage, are from 18dB pulled to high level to keep the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a defi- to -80dB. Each gain step corresponds to a specific input voltage range, as shown in table. To minimize the effect of nite voltage to avoid unwanted state changing. noise on the volume control pin, which can affect the selected gain level, hysteresis and clock delay are Thermal Protection The thermal protection circuit limits the junction temperature of the APA2071. When the junction temperature ex- implemented. The amount of hysteresis corresponds to half of the step width, as shown in the volume control ceeds T J = +150 oC, a thermal sensor turns off the amplifier, allowing the devices to cool. The thermal sen- graph. sor allows the amplifier to start-up after the junction temperature down about 125 oC. The thermal protection is APA2071 DC Volume Control Curve (BTL) 20 designed with a 25oC hysteresis to lower the average TJ during continuous thermal overload conditions, which is 10 0 increasing lifetime of the IC. Gain (dB) -10 Forward -20 -30 Over-Current Protection Backward The APA2071 monitors the output current. When the cur- -40 rent exceeds the current-limit threshold, the APA2071 turns off the output to prevent the IC from damages in over- -50 -60 current or short-circuit condition. When the over-current occurs in power amplifier, the output buffer’s current will -70 -80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 be foldbacked to a low setting level, and it will release when over-current situation is no long existence. On the DC Volume (V) contrary, if the over-current period is long enough and the IC’s junction temperature reaches the thermal protection Figure 3: Gain setting vs. VOLUME pin voltage threshold, the IC will enter thermal protection mode. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 16 www.anpec.com.tw APA2071 Application Information Input Capacitor (Ci) than 0.485VDD, the APA2071 will enter mute condition. The value of VBYPASS can be calculated as blew: In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the fixed input impedance Ri form a high-pass filter with the VBYPASS = 0.5VDD - ILeakage × 130k Ω (4) corner frequency is determined in the following equation: fC(highpass ) = 1 2 πR iC i Where (2) ILeakage =Leakage current of CBYPASS The value of Ci must be considered carefully because it directly affects the low frequency performance of the Therefore, it is recommended that CBYPASS ’s leakage current should be no more than 0.5µA for properly work of circuit. Consider the example where Ri is 20kΩ and the specification calls for a flat bass response down to 40Hz. the APA2071. To avoid the start-up pop noise, the bypass voltage should rise slower than the input bias voltage and the relation- The equation is reconfigured below : Ci = ship shown in equation should be maintained. 1 2 π R i fc (3) 1 1 << ( C BYPASS X130k Ω ) C i X20k Ω Consider the variation of input resistance (Ri), the value of Ci should be 0.2µF. Therefore, it’s better to choose a (5) value in the range from 0.22µF to 1.0µF. A further consideration for this capacitor is the leakage path from the in- The capacitor is fed from a 130kΩ resistor inside of the amplifier and the 20kΩ is the fixed input resistance. put source through the input network (Ri + Rf, Ci) to the Bypass capacitor, C BYPASS, values of 2.2µF to 10µF ceramic or tantalum low-ESR capacitors are recom- load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, es- mended for the best THD+N and noise performance. The bypass capacitance also affects the start-up time. It pecially in high gain applications. For this reason, a lowleakage tantalum or ceramic capacitor is the best choice. is determined in the following equation: When polarized capacitors are used, the positive side of the capacitors should face the amplifiers’ inputs in most Tstart up = 5X(C BYPASS X130k Ω ) applications because the DC level of the amplifiers’ inputs are held at VDD/2. Please note that it is important to (6) Output Coupling Capacitor (CC) In the typical single-supply SE configuration, an output confirm the capacitor polarity in the application. coupling capacitor (CC) is required to block the DC bias at the output of the amplifier thus preventing DC currents in Effective Bypass Capacitor (CBYPASS) A power amplifier, proper supply bypassing, is critical for low noise performance and high power supply rejection. the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high- The capacitor location on the BYPASS pin should be as close to the device as possible. The effect of a larger pass filter governed by the equation. supply bypass capacitor is to improve PSRR due to increased half-supply stability. Two critical criteria of by- FC(highpass) = st 1 2πRLCC (7) pass capacitor (CBYPASS): 1 , it depends upon desired PSRR requirements and click-and-pop performance; 2 nd, the For example, a 330µF capacitor with an 8Ω speaker would leakage current of CBYPASS will induce the voltage drop of VBYPASS (voltage of BYPASS pin), and if the VBYPASS is less attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 17 www.anpec.com.tw APA2071 Application Information (Cont.) Output Coupling Capacitor (CC) (Cont.) impedance is typically small, which drives the low-frequency corner higher degrading the bass response. This capacitor discharges through the internal 10kΩ resistors. Depending on the size of CC, the time constant Large values of CC are required to pass low frequencies into the load. can be relatively large. To reduce transients in SE mode, an external 1kΩ resistor can be placed in parallel with the internal 10kΩ resistor. The tradeoff for using this resistor Power Supply Decoupling Capacitor (CS) The APA2071 is a high-performance CMOS audio ampli- is an increase in quiescent current. In the most cases, choosing a small value of Ci in the range of 0.33µF to fier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is 1µF, CBYPASS being equal to 4.7µF and an external 1kΩ resistor should be placed in parallel with the internal 10kΩ as low as possible. Power supply decoupling also prevents the oscillations caused by long lead length between resistor should produce a virtually clickless and popless turn-on. the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that tar- A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain, so it is advanta- get on different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash geous to use low-gain configurations. on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF, is placed as close BTL Amplifier Efficiency as possible to the device VDD lead works best. For filtering lower-frequency noise signals, it is recommended to An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power sup- place a large aluminum electrolytic capacitor of 10µF or greater near the audio power amplifier ply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. Optimizing Depop Circuitry Circuitry has been included in the APA2071 to minimize the amount of popping noise at power-up and when com- Efficiency = ing out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to elimi- PO P SUP (8) Where nate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the de- PO = vice or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops (Refer to VO, RMS = Effective Bypass Capacitance). The bypass voltage ramp up should be slower than input bias voltage. Although the P SUP = V DD × I DD , AVG = V DD × VO,RMS 2 RL = VP2 2R L VP (9) 2 2VP πR L (10) bypass pin current source cannot be modified, the size of Efficiency of a BTL configuration : CBYPASS can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of CBYPASS, turn-on pop can be reduced. However, the PO = P SUP tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relation- VP2 πV P 2R L = 2VP 4V DD V DD × πR L (11) Table 1 is for calculating efficiencies for four different out- ship between the size of CBYPASS and the turn-on time. In a SE configuration, the output coupling capacitor (CC), is of put power levels. particular concern. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 18 www.anpec.com.tw APA2071 Application Information (Cont.) BTL Amplifier Efficiency (Cont.) BTL mode : PD, MAX = Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load 4VDD2 2π2RL (13) Since the APA2071 is a dual channel power amplifier, the is increased resulting in a nearly flat internal power dissipation over the normal operating range. In addition, the maximum internal power dissipation is 2 times that both of equations depend on the mode of operation. Even with internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific this substantial increase in power dissipation, the APA2071 does not require extra heatsink. The power dis- system is the key to proper power supply design. For a stereo 1W audio system with 8Ω loads and a 5V supply, sipation from equation (14), assuming a 5V-power supply and an 8Ω load, must not be greater than the power the maximum draw on the power supply is almost 3W. A final point to remember about linear amplifiers (either dissipation that results from the equation (16): SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note PD, MAX = that in equation, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, TJ, MAX - TA θJA (14) For DIP-16 / DIP-16A package, the thermal resistance (θJA) is equal to 45οC/W. Since the maximum junction temperature (TJ,MAX) of the use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Po (W) Efficiency (%) IDD(A) VPP(V) PD (W) APA2071 is 150οC and the ambient temperature (TA) is defined by the power system design, the maximum power 0.25 31.25 0.16 2.00 0.55 dissipation which the IC package is able to handle can be obtained from equation16. 0.50 47.62 0.21 2.83 0.55 1.00 66.67 0.30 4.00 0.5 Once the power dissipation is greater than the maximum limit (P D,MAX ), either the supply voltage (V DD) must be decreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. 1.25 78.13 0.32 4.47 0.35 Thermal Consideration Linear power amplifiers dissipate a significant amount of **High peak voltages cause the THD+N to increase. heat in the package under normal operating conditions. The first consideration to calculate maximum ambient Table 1. Efficiency vs. Output Power in 5-V/8Ω BTL Systems Power Dissipation temperatures is the numbers from the Power Dissipation vs. Output Power graphs are per channel values, so Whether the power amplifier is operated in BTL or SE mode, power dissipation is the major concern. Equation the dissipation of the IC heat needs to be doubled for two-channel operation. Given θJA, the maximum allow- (14) states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving able junction temperature (TJMAX), and the total internal dissipation (PD), the maximum ambient temperature can a specified load. be calculated with the following equation. The maximum recommended junction temperature for the APA2071 is SE mode: PD, MAX = VDD2 2π2RL (12) 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus, the maximum power dis- TAMax = TJMax -θJAPD 150 - 45(0.8*2) = 78°C sipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 (15) 19 www.anpec.com.tw APA2071 Application Information (Cont.) Thermal Consideration (Cont.) The APA2071 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150°C to prevent damaging the IC. Layout Consideration Via diameter =0.3mm x 24 4mm 3mm 20mm Ground plane for GND pin 16mm Figure 5: APA 2071 Land Pattern Recommendation 1. All components should be placed close to the APA2071. For example, the input capacitor (Ci) should be close to APA2071’s input pins to avoid causing noise coupling to APA2071’s high impedance inputs; the decoupling capacitor (CS) should be placed by the APA2071’s power pin to decouple the power rail noise. 2. The output traces should be short, wide (>50mil), and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should be greater than 50mil. 5. The APA2071’s GND pin should be soldered on ground plane of the PCB. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 20 www.anpec.com.tw APA2071 Package Information DIP-16 E1 D 0.38 A L A1 A2 E b D1 b2 e c eA eB S Y M B O L DIP-16 MILLIMETERS MIN. INCHES MIN. MAX. A MAX. 0.210 5.33 0.015 A1 0.38 A2 2.92 4.95 0.115 0.195 b 0.36 0.56 0.014 0.022 0.070 b2 1.14 1.78 0.045 c 0.20 0.35 0.008 0.014 D 18.6 20.31 0.732 0.800 D1 0.13 E 7.62 8.26 0.300 0.325 E1 6.10 7.11 0.240 0.280 0.005 e 2.54 BSC 0.100 BSC eA 7.62 BSC 0.300 BSC eB L 0.430 10.92 2.92 0.115 3.81 0.150 Note : 1. Followed from JEDEC MS-001AB 2. Dimension D, D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 10 mil. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 21 www.anpec.com.tw APA2071 Package Information DIP-16A E1 D L A1 0.38 A A2 E b D1 b2 e c eA eB S Y M B O L DIP-16A MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 5.33 0.210 0.015 A1 0.38 A2 2.92 4.95 0.115 0.195 b 0.36 0.56 0.014 0.022 b2 1.14 1.78 0.045 0.070 0.014 0.800 c 0.20 0.35 0.008 D 18.6 20.31 0.732 D1 0.13 E 7.62 8.26 0.300 0.325 E1 6.10 7.11 0.240 0.280 0.005 e 2.54 BSC 0.100 BSC eA 7.62 BSC 0.300 BSC eB L 0.430 10.92 2.92 0.115 3.81 0.150 Note : 1. Followed from JEDEC MS-001AB 2. Dimension D, D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 10 mil. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 22 www.anpec.com.tw APA2071 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 23 www.anpec.com.tw APA2071 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 Package Thickness Volume mm <350 <2.5 mm 240 +0/-5°C ≥2.5 mm 225 +0/-5°C 3 Volume mm ≥350 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Nov., 2008 24 www.anpec.com.tw