APA2614 15W Stereo Class-D Audio Power Amplifier Features • • General Description Supply Voltage is 8V ~ 26V The APA2614 is a stereo, high efficiency, Class-D audio Class D operation eliminates heat sink & reduce power supply requirement amplifier available in TSSOP-28Pand QFN4x4-28 pins packages. 20,26, 32, 36, 4 steps gain setting 15W/ch into an 8Ω Loads at 10% THD+N from a 16- The Class-D power amplifier has higher efficiency compare to the tradition Class-AB power amplifier. The filter- • V supply 10W/ch into 8Ω Loads at 10% THD+N from a 13V free Class-D architecture eliminates the external low pass filters. The internal gain setting can minimum the exter- • supply 30W into a 4Ω Mono Load at 10% THD+N from a nal component counts, and for the flexible application the gain can be set to 4-step 20, 26, 32, 36dB by gain control • 16V Supply Adjustable Power limit function plus DC Protec- ins (GAIN0 and GAIN1). The power limit function cans protection the speaker when output signal excess the • tion Thermal and Over-Current Protections with Auto- speaker limit rating. The integration of Class-D power amplifier is a best so- Recovery option TSSOP-28P with thermal pad packages lution for power efficiency and lower the total BOM costs. The operating voltage is from 8V to 26V. The APA2614 QFN4x4-28 with thermal pad packages power amplifiers are capable of driving 15 W at VDD=16V into 8Ω speaker, and provides thermal and over-current • • • • protections also can detection the DC that prevent to destroy the speaker voice coil. Applications • • Pin Configuration LCD Monitor AIO Simplified Application Circuit SD 1 28 LPVDD FLAG 2 27 LPVDD 26 LBSP LINP 3 25 LOUTP LINN 4 APA2614 LOUTP Left Channel Input Right Channel Input LINP LINN RINN LOUTN ROUTN RINP ROUTP 24 PGND GAIN0 5 23 LOUTN GAIN1 6 FERRITE BEAD FILTER FERRITE BEAD FILTER AVDD 7 Left Channel Speaker AGND 8 APA2614 TSSOP-28P 21 RBSN 20 ROUTN VCLAMP 9 Right Channel Speaker 22 LBSN PLIMT 10 19 PGND RINN 11 18 ROUTP RINP 12 17 RBSP NC 13 16 RPVDD MONO 14 15 RPVDD (Top View) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 1 www.anpec.com.tw APA2614 22 PGND 23 ROUTN 24 RBSN 25 NC 26 LBSN 28 PGND 27 LOUTN Pin Configuration(Cont.) 21 ROUTP LOUTP 1 LBSP 2 LPVDD 3 20 RBSP 19 RPVDD APA2614 QFN4x4-28 SD 4 FLAG 5 LINP 6 18 MONO 17 NC 16 RINP 15 RINN PLIMIT 14 VCLAMP 13 AGND 12 AVDD 11 GAIN1 10 NC 8 GAIN0 9 LINN 7 (Top View) Ordering and Marking Information APA2614 Package Code R : TSSOP-28P QA : QFN4x4-28 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device Assembly Material Handling Code Temperature Range Package Code APA2614 R : APA2614 QA : APA2614 XXXXX XXXXX - Date Code XXXXX - Date Code APA2614 XXXXX Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 2 www.anpec.com.tw APA2614 Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol VDD Parameter Rating Supply Voltage (PVDD, AVDD) -0.3 to 30 Input Voltage (SD, GAIN0 and GAIN1, MONO and FLAG) VI TJ Unit -0.3 to VDD+0.3 PLIMIT -0.3 to 6.3 LINP, LINN, RINP, RINN -0.3 to 6.3 Maximum Junction Temperature V ο 150 TSTG Storage Temperature Range TSDR Soldering Temperature Range, 10 Seconds 260 STEREO Mode : VDD＞15V 4.8 RL STEREO Mode: VDD ≦15V 3.2 PD Power Dissipation C -65 to +150 MONO mode Ω 3.2 Internally Limited W Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Typical Value Unit Thermal Resistance -Junction to Ambient (Note 2) TSSOP-28P QFN4x4-28 45 40 TSSOP-28P QFN4x4-28 8 7 ο C/W Thermal Resistance -Junction to Case (Note 3) Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of TSSOP-28P is soldered directly on the PCB. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the TSSOP-28P package. Recommended Operating Conditions Symbol Parameter Min. Max. 8.0 26.0 SD 2.2 - GAIN0, GAIN1, MONO 2.0 - SD - 0.8 GAIN0, GAIN1, MONO - 0.8 Unit VDD Supply Voltage VIH High Level Threshold Voltage VIL Low Level Threshold Voltage TA Ambient Temperature Range -40 85 o TJ Junction Temperature Range -40 125 o RL Speaker Resistance 3.5 - Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 3 V C C Ω www.anpec.com.tw APA2614 Electrical Characteristics VDD=12V, GND=0V, AV=36dB, TA= 25οC (unless otherwise noted). Symbol Parameter APA2614 Test Conditions Min. Typ. Max. 4.5 5 5.5 - Unit Regulated Voltage IO=2mA, VDD=8~26V TJ = -40oC ~ 125oC Maximum Output Voltage Under PLIMIT Control VPLIMIT = 1V, Vl = 1Vrms - 5.5 TSD(ON) Shutdown Turn-On Time SD =2.2V - 16 - ms TSD(OFF) Shutdown Turn-Off Time SD =0.8V - 2 - µs IDD Quiescent Supply Current No Load - 20 35 mA ISD Quiescent Supply Current in shutdown mode SD = 0V - 10 100 Input Current SD , GAIN0, GAIN1, MONO - 5 50 400 500 600 kHz VDD = 12V, IL= 0.5A - 240 - mΩ Gain 0 = 0, Gain 1 = 0 - 20 - Gain 0 = 1, Gain 1 = 0 - 26 - Gain 0 = 0, Gain 1 = 1 - 32 - VCLAMP VO II FOSC Internal Oscillator Frequency RDSON Static Drain-Source On-State Resistance AV tDCDET Gain DC Derect Time Gain 0 = 1, Gain 1 = 1 - 36 - VINP=5V, VINN=0V - 500 - V µA dB ms Stereo Mode VDD=12V, GND=0V, AV=36dB, TA= 25οC (unless otherwise noted). Symbol Parameter APA2614 Test Conditions Unit Min. Typ. Max. - 12 - W - 0.1 - % VDD = 24V, TA = 25° C Po THD+N Crosstalk PSRR Output Power VDD=16V THD+N=1%, FIN=1kHz RL=8Ω Total Harmonic Distortion Pulse Noise VDD=16V FIN=1kHz, Po=7.5W Channel Separation VO=1Vrms, FIN =1kHz, Gain=20dB - -85 - Power Supply Rejection Ratio RL=4Ω, input AC-Ground, fin=1kHz Maximum output at THD+N<1%, FIN=1kHz, Gain = 20dB, A-weighted - -65 - - 95 - dB SNR Signal-To-Noise Ratio Attshutdown Shutdown Attenuation FIN=1kHz, RL = 8Ω, Vin = 1VPP - -100 - Offset Voltage AV=20dB - - 15 mV Noise Output Voltage With A-weighted Filter (AV = 20dB) - 160 - µV (rms) VDD=13V THD+N = 1% FIN=1kHz RL=8Ω - 8 - VDD=13V THD+N = 10% FIN=1kHz RL=8Ω - 10 - VDD=13V FIN=1kHz RL = 8Ω PO = 5W - 0.1 - I VOS I Vn VDD = 12V TA = 25° C PO THD+N Output Power Total Harmonic Distortion Plus Noise Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 4 W % www.anpec.com.tw APA2614 Stereo Mode (Con.t) VDD=12V, GND=0V, AV=36dB, TA= 25οC (unless otherwise noted). Symbol Parameter Test Conditions APA2614 Min. Typ. Max. Unit VDD = 12V TA = 25° C Crosstalk PSRR Channel Separation VO=1Vrms, FIN =1kHz, Gain=20dB - -90 - Power Supply Rejection Ratio RL=4Ω, input AC-Ground, fin=1kHz Maximum output at THD+N<1%, FIN=1kHz, Gain = 20dB, A-weighted - -65 - - 95 - -100 - dB SNR Signal-To-Noise Ratio Attshutdown Shutdown Attenuation FIN=1kHz, RL = 8Ω, Vin = 1VPP - Offset Voltage AV=20dB - - 15 mV Noise Output Voltage With A-weighted Filter (AV = 20dB) - 160 - µV (rms) I VOS I Vn Mono Mode VDD=12V, GND=0V, AV=36dB, TA= 25οC (unless otherwise noted). Symbol Parameter Test Conditions APA2614 Min. Typ. Max. - 24 - Unit VDD = 12V TA = 25° C PO Output Power THD+N Total Harmonic Distortion Plus Noise PSRR Power Supply Rejection Ratio VDD=16V THD+N = 1% FIN=1kHz RL = 4Ω VDD=16V THD+N = 10% FIN=1kHz RL = 4Ω - 30 - VDD=16V FIN=1kHz RL = 4Ω PO = 6W - 0.1 - RL=4Ω, input AC-Ground, fin=1kHz Maximum output at THD+N<1%, FIN=1kHz, Gain = 20dB, A-weighted - -65 - - 95 - -100 - W % dB SNR Signal-To-Noise Ratio Attshutdown Shutdown Attenuation FIN=1kHz, RL = 8Ω, Vin = 1Vrms - VOS Offset Voltage AV = 20dB - - 15 mV Vn Noise Output Voltage With A-weighted Filter (AV = 20dB) - 160 - µV (rms) Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 5 www.anpec.com.tw APA2614 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=8V VDD=19V VDD=8V VDD=12V VDD=12V VDD=24V Fin=1kHz RL=8Ω AV=20dB AUX-0025 AES-17(20kHz) 0.1 0.01 0 5 10 15 20 25 30 35 Fin=1kHz RL=4Ω AV=20dB AUX-0025 AES-17(20kHz) 0.1 0.01 0 40 Output Power (W) 5 10 20 25 30 35 40 45 THD+N vs. Frequency 10 10 VDD=8V 1 VDD=12V THD+N (%) THD+N (%) VDD=19V 1 Fin=1kHz RL=4Ω AV=20dB AUX-0025 AES-17(20kHz) MONO mode 0.1 0 10 20 30 40 VDD=12V RL=8Ω AV=20dB AUX-0025 AES-17(20kHz) PO=1W 0.01 0.001 20 50 THD+N vs. Frequency 100 10k 20k THD+N vs. Frequency 1 PO=10W THD+N (%) VDD=19V RL=8Ω AV=20dB AUX-0025 AES-17(20kHz) 0.1 PO=1W VDD=12V RL=4Ω AV=20dB AUX-0025 AES-17(20kHz) MONO mode PO=6W 0.1 PO=1W 0.01 0.01 0.001 20 1k Frequency (Hz) 10 10 1 PO=4W 0.1 Output Power (W) THD+N (%) 15 Output Power (W) THD+N vs. Output Power 0.01 VDD=19V 1 THD+N (%) THD+N (%) 1 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 0.001 20 10k 20k 6 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2614 Typical Operating Characteristics Efficiency vs. Ouput Power THD+N vs. Frequency 10 100 THD+N (%) 1 90 80 PO=10W VDD=24V 70 Efficiency (%) VDD=19V RL=4Ω AV=20dB AUX-0025 AES-17(20kHz) MONO mode 0.1 PO=1W VDD=19V VDD=12V 60 VDD=8V 50 Fin=1kHz RL=8Ω THD+N≦10% AV=20dB AUX-0025 AES-17(20kHz) stereo mode 40 30 0.01 20 10 0.001 20 100 1k 0 0 10k 20k 2 4 6 Frequency (Hz) 12.0 VDD=12V RL=8Ω AV=20dB 90 10.0 80 Output Power (W) 70 60 VDD=8V 50 VDD=12V Fin=1kHz RL=4Ω THD+N≦10% AV=20dB AUX-0025 AES-17(20kHz) MONO mode 40 30 20 10 0 0 2 4 6 8.0 6.0 4.0 2.0 0.0 8 10 12 14 16 18 20 22 24 26 28 30 0.0 0.5 1.0 1.5 Output Power (W) Crosstalk vs. Frequency Output Power vs. PLIMIT Voltage -40 VDD=19V RL=8Ω AV=20dB -50 -60 20.0 Crosstalk (dB) Output Power (W) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VPLIMT (V) 28.0 24.0 10 12 14 16 18 20 22 24 Output Power vs. PLIMIT Voltage Efficiency vs. Ouput Power 100 Efficiency (%) 8 Output Power (W) 16.0 12.0 -70 VDD=12V RL=8Ω PO=1W Ci=1µF Av=20dB AUX-0025 AES-17(20kHz) -80 Left channel to Right channel -90 8.0 -100 4.0 -110 Right channel to Left channel -120 20 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VPLIMT (V) Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 100 1k 10k 20k Frequency (Hz) 7 www.anpec.com.tw APA2614 Typical Operating Characteristics Output Noise Voltage vs. Frequency Crosstalk vs. Frequency -40 Crosstalk (dB) -60 -70 -80 VDD=12V RL=8Ω Ci=1µF AUX-0025 AES-17(20kHz) A-Weighting 400 Output Noise Voltage (µV) -50 450 VDD=24V RL=8Ω PO=1W Ci=1µF Av=20dB AUX-0025 AES-17(20kHz) Right channel to Left channel -90 350 300 AV=32dB 250 -100 Left channel to Right channel -120 20 AV=20dB 200 -110 1k 10k 20k 20 100 400 350 Output Noise Voltage vs. Frequency VDD=24V RL=8Ω Ci=1µF AUX-0025 AES-17(20kHz) A-Weighting PSRR vs. Frequency VDD=12V RL=8Ω AV=20dB Vrr=0.2Vrms AUX-0025 AES-17(20kHz) -20 AV=36dB -30 AV=32dB 250 AV=26dB -40 L-channel -50 -60 -70 200 AV=20dB 100 1k R-channel -80 -90 20 10k 20k 100 PSRR vs. Frequency Frequency Response +150 Gain, AV=26dB +24 +22 -50 +100 Gain, AV=20dB +50 +20 +0 +18 -60 +16 -70 +14 -80 +12 -90 20 +200 +26 Gain (dB) -40 VDD=12V RL=8Ω AV=20dB Vrr=0.2Vrms AUX-0025 AES-17(20kHz) MONO mode Phase, AV=26dB VDD=12V RL=8Ω Ci=1µF AUX-0025 AES-17(20kHz) -50 Phase, AV=20dB 1k 20 10k 20k 10k 20k 1k 100k -200 Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 100 -100 -150 +10 100 Phase (Degree) -30 10k 20k +28 0 -20 1k Frequency (Hz) Frequency (Hz) -10 10k 20k 0 -10 300 150 20 1k Frequency (Hz) PSRR (dB) Output Noise Voltage (µV) 450 AV=26dB 150 100 Frequency (Hz) PSRR (dB) AV=36dB 8 www.anpec.com.tw APA2614 Typical Operating Characteristics Shutdown Attenuation vs. Frequency Frequency Response +36 +34 -50 +150 -60 +100 +50 +30 +0 +28 +26 Phase, AV=36dB VDD=12V RL=8Ω Ci=1µF AUX-0025 AES-17(20kHz) +24 +22 -50 Phase (Degree) Gain, AV=32dB +32 Gain (dB) Gain, AV=36dB +200 Shutdown Attenuation (dB) +38 1k 10k 20k -130 100k L-channel R-channel 100 20 1k 10k 20k Frequency (Hz) Frequency (Hz) Supply Current vs. Supply Voltage Shutdown Current vs. Supply Voltage 30 1.0 0.9 No Load 25 No Load 0.8 Shutdown Current (µA) Supply Current (mA) -90 -120 -200 100 20 -80 -110 -150 +20 -70 -100 -100 Phase, AV=32dB VDD=12V RL=8Ω Ci=1µF AV=20dB AUX-0025 AES-17(20kHz) 20 15 10 5 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0.0 0 2 4 0 6 8 10 12 14 16 18 20 22 24 26 28 30 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Supply Voltage (V) 9 www.anpec.com.tw APA2614 Pin Description PIN I/O/P FUNCTION NO. TSSOP -28P QFN4x4 -28 NAME 1 4 SD I 2 5 FLAG O 3 6 LINP I Positive audio input for left channel. Biased at VCLAMP/2. 4 7 LINN I Negative audio input for left channel. Biased at VCLAMP/2. 5 9 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to AVDD. 6 10 GAIN1 I Gain select least significant bit. TTL logic levels with compliance to AVDD. Shutdown logic input for audio amp (Low=outputs disabled, High=output enabled). TTL logic levels with compliance to AVDD. Protection flag output (open drain). Connecting FLAG and SD can be set to auto-recovery. Otherwise need to reset by cyding AVDD 7 11 AVDD P Analog supply. 8 12 AGND P Analog signal ground. Connect to the thermal pad. 9 13 VCLAMP O 10 14 PLIMIT I Regulated voltage, Nominal voltage is 5V. Power limit level adjust. Connect a resistor divider from VCLAMP to GND to set power limit. Connect directly to VCLAMP for no power limit. 11 15 RINN I Negative audio input for right channel. Biased at VCLAMP/2. 12 16 RINP I Positive audio input for right channel. Biased at VCLAMP/2. 13 8, 17, 25 NC 14 18 MONO I Parallel BTL mode switch. 15,16 19 RPVDD P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connected internally. 17 20 RBSP I Bootstrap I/O for right channel, positive high-side FET. 18 21 ROUTP O Class-D H-bridge positive output for right channel. 19, 24 22, 28 PGND P Power ground for the H-bridges. 20 23 ROUTN O Class-D H-bridge negative output for right channel. 21 24 RBSN I Bootstrap I/O for right channel, negative high-side FET. 22 26 LBSN I Bootstrap I/O for left channel, negative high-side FET. 23 27 LOUTN O Class-D H-bridge negative output for left channel. 25 1 LOUTP O Class-D H-bridge positive output for left channel. 26 2 LBSP I Bootstrap I/O for left channel, positive high-side FET. 27,28 3 LPVDD P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connected internally. Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 Not connected. 10 www.anpec.com.tw APA2614 Block Diagram LBSP VCLAMP LPVDD LPVDD LOUTP FB MONO Select Gate Drive LOUTP FB LOUTP LINP Gain Control PWM Logic PLIMIT PGND VCLAMP LPVDD LBSN LPVDD LINN LOUTN FB LOUTN FB Gate Drive LOUTN FLAG Biases and References SD TTL Buffer GAIN0 GAIN1 GAIN Control PLIMIT Reference PLIMIT RAMP GEN. PGND SD Detect DC Detect LPVDD Thermal Detect RPVDD Startup Protection Logic UVLO/OCLO RBSN VCLAMP LDO Regulator AVDD RPVDD RPVDD VCLAMP VCLAMP Gate Drive ROUTN FB ROUTN ROUTN FB RINN Gain Control PLIMIT PWM Logic PGND VCLAMP RPVDD RBSP RPVDD RINP ROUTP FB MONO Select Gate Drive ROUTP ROUTP FB MONO TTL Buffer MONO Select PGND AGND Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 11 www.anpec.com.tw APA2614 Typical Application Circuit VDD 100µF Shutdown Control 1µF SD 1 28 LPVDD FLAG 2 LINP 3 27 LPVDD 26 LBSP 25 LOUTP LINN 4 GAIN0 5 1µF Gain Setting 1µF 1µF 23 LOUTN AVDD 7 22 LBSN 10kΩ 10kΩ VCLAMP 9 APA2614 1µF BEAD 1000pF BEAD 0.22µF 0.22µF 21 RBSN 1000pF BEAD 20 ROUTN PLIMIT 10 1µF Right Channel Input Signal 0.22µF 24 PGND GAIN1 6 AGND 8 1µF 1000 pF (Recommmanded) 1kΩ (Recommmanded) Left Channel Input Signal 0. 1µF 100kΩ 10Ω 1000pF 19 PGND RINN 11 18 ROUTP RINP 12 17 RBSP NC 13 16 RPVDD MONO 14 15 RPVDD BEAD 1000 pF 0.22µF 100 µF 0. 1µF 1000 pF 29 GND Stereo VDD VDD 100µF Shutdown Control SD 1 28 LPVDD FLAG 2 27 LPVDD 26 LBSP 25 LOUTP LINP 3 LINN 4 GAIN0 5 Gain Setting 1µF 24 PGND 0.47µF GAIN1 6 23 LOUTN AVDD 7 22 LBSN AGND 8 VCLAMP 9 APA2614 BEAD 1000pF 21 RBSN BEAD 20 ROUTN PLIMIT 10 Right Channel Input Signal 1000 pF (Recommmanded) 1kΩ (Recommmanded) 1µF 0. 1µF 100kΩ 10Ω 1000pF 19 PGND 1µF RINN 11 18 ROUTP 1µF RINP 12 17 RBSP NC 13 16 RPVDD MONO 14 15 RPVDD 0.47µF 100 µF 0. 1µF 1000 pF 29 GND MONO Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 12 VDD www.anpec.com.tw APA2614 Function Description Class-D Operation the switching period, reducing the switching current, which reduces any I2R losses in the load. Output = 0 Gain Setting Operation VOUTP VOUTN VOUT (VOUTP-VOUTN) GAIN1 GAIN0 Gain Ri(Ω) 0 0 20dB 60k 0 1 26dB 30k 1 0 32dB 15k 1 1 36dB 9k Table 1 : The Gain Setting The APA2614’s gain can be set by GAIN0, GAIN1. The detail gain setting value is list at table 1. IOUT Output > 0 Shutdown Operation VOUTP In order to reduce power consumption while not in use, the APA2614 contains a shutdown function to externally turn off the amplifier bias circuitry. This shutdown feature VOUTN turns the amplifier off when logic low is placed on the SD pin for APA2614. The trigger point between a logic high VOUT (VOUTP-VOUTN) and logic low level is typically 2.2V. It is best to switch between ground and the supply voltage VDD to provide IOUT maximum device performance. By switching the SD pin to low level, the amplifier enters a low-consumption- cur- Output < 0 VOUTP rent state, IDD for APA2614 is in shutdown mode. On normal operating, APA2614’s SD pin should pull to high level VOUTN to keeping the IC out of the shutdown mode. The SD pin should be tied to a definite voltage to avoid unwanted state changes. VOUT (VOUTP-VOUTN) Power Limit Operation The voltage at pin 10 can used to limit the power to levels below that which is possible based on the supply rail. IOUT Add a resistor divider from Vclamp to ground to set the voltage at the PLIMIT pin. An external reference may also Figure1. The APA2614 Output Waveform be used if tighter tolerance is required. Also add a 1µF capacitor from pin 10 to ground. The APA2614 uses a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load. Each output is switching from 0 volts to the supply voltage. The VOUTP and VOUTN are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of VOUTP is greater than 50% and VOUTN is less than 50% for positive output voltages. The duty cycle of VOUTP is less than 50% and VOUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0V throughout most of Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 13 www.anpec.com.tw APA2614 Function Description (Cont.) Power Limit Operation (Cont.) DC Detect The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to When a DC signal applies to the input of APA2614 and the time excesses 500ms, the APA2614’s DC detect fault will be reported on the FLAG pin as a low state. The DC fixed maximum value. This limit can be thought of as a “virtual” voltage rail which is lower than the supply con- Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. To clear the DC nected to PVDD. This “virtual” rail is 5.6 times the voltage at the PLIMIT pin. This output voltage can be used to Detect it is necessary to cycle the PVDD supply. Cycling SD will NOT clear a DC detect fault. calculate the maximum output power for a given maximum input voltage and speaker impedance. . VP = 5.6 × PLIMIT voltage if PLIMIT < 2.5 V Test Condition PVDD=12V, Rl=8 Ω PVDD=12V, Rl=4 Ω Over-Current Protection MAX Output @ PLIMIT Voltage THD+N=1% THD+N=10% 1.13V 1.58W 2W 1.4V 2.29W 3W 1.68V 3.235W 4W 1.86V 4.03W 5W 0.91V 2W 2.6W 1.16V 3W 3.96W 1.38V 4W 5.1W 1.57V 5W 6.3W 1.85V 7W 8.5W APA2614 has protection from over-current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FLAG pin as a low state. The amplifier outputs are switched to a Hi-Z state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SD pin through the low state. Connect FLAG to SD pin, the over current protection will be auto recovery. Thermal Protection Thermal protection on the APA2614 prevents damage to the device when the internal die temperature exceeds Table2. PLIMIT Typical Operation 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the VCLAMP Supply The VCLAMP is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched voltage divider circuit. Add a 1µF capacitor to ground at this pin. fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C. The device begins normal Stereo/mono switching Operation APA2614 offers the feature of Stereo operation with two outputs of each channel connected directly. If the MONO pin (pin 14) is tied high, the positive and negative outputs operation at this point with no external system interaction. Thermal protection faults are NOT reported on the FLAG terminal. of each channel (left and right) are synchronized and in phase. To operate in this mono mode, apply the input signal to the RIGHT input and place the speaker between the LEFT and RIGHT outputs. Connect the positive and negative output together for best efficiency. MONO mode can increase more output power compare to the stereo mode single channel’s output power. Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 14 www.anpec.com.tw APA2614 Application Information Input Resistance, Ri A ferrite bead may need if it’s failing the test for FCC or CE tested without the LC filter. The figure 2 is the sample for Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 9 kΩ ±20%, to the added ferrite bead; the ferrite show choosing high impedance in high frequency. largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or cutoff frequency may change when changing gain steps. Ferrite OUTP Bead Input Capacitor, Ci 1nF In the typical application, an input capacitor Ci is required to allow the amplifier to bias the input signal to the proper Ferrite OUTN Bead dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (RI) form a high-pass 4Ω 1nF filter with the corner frequency determined in Equation 1. fC(hipass ) = 1 2πRiCi (1) Figure 3. Ferrite Bead Output Filter The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider the Figure 4 and Figure 5 are examples for added the LC filter (Butterworth), it’s recommended for the situation that the trace form amplifier to speaker is too long, and needs example where RI is 60 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 1 is to eliminate the radiated emission or EMI. reconfigured as Equation 2. Ci = 1 2πRi fc (2) In this example, CI is 0.13 µF; so, one would likely choose a value of 0.15 µF as this value is commonly used. If the OUTP 33µH 1µF gain is known and is constant, use RI from Table 1 to calculate CI. A further consideration for this capacitor is OUTN 33µH the leakage path from the input source through the input network CI and the feedback network to the load. This 8Ω 1µF leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially Figure 4. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 8Ω in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at V /2, which is CLAMP likely higher than the source dc level. Note that it is impor- OUTP 2.2µF tant to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset volt- OUTN 15µH ages and it is important to ensure that boards are cleaned properly. 4Ω 2.2µF Output Low-Pass Filter If the traces form APA2614 to speaker are short, it doesn’t require output filter for FCC & CE standard. Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 15µH Figure 5. Typical LC Output Filter, Cutoff Frequency of 27 kHz, Speaker Impedance = 4Ω 15 www.anpec.com.tw APA2614 Application Information (Cont.) 1.The high frequency decoupling capacitors should be Power-Supply Decoupling Capacitor, CS placed as close to the PVDD and AVDD terminals as possible. Large (100µF or greater) bulk power supply The APA2614 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to decoupling capacitors should be placed near the APA2614 on the LPVDD and RPVDD supplies. Local, ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents high-frequency bypass capacitors should be placed as close to the PVDD pins as possible. These caps the oscillations being caused by long lead length between the amplifier and the speaker. can be connected to the thermal pad directly for an excellent ground connection. Consider adding a small, The optimum decoupling is achieved by using two different types of capacitors that target on different types of good quality low ESR ceramic capacitor between 1000 pF and 10nF and a larger mid-frequency cap of value noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low between 0.1µF and 1µF also of good quality to the PVDD connections at each end of the chip. equivalent-series-resistance (ESR) ceramic capacitor, typically 1µF placed as close as possible to the device 2.Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to AVDD pin . PGND as small and tight as possible. The size of this current loop determines its effectiveness as an BSN and BSP Capactiors The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors antenna. 3.Grounding— The AVDD (pin 7) decoupling capacitor for the high side of each output to turn on correctly. A 0. 22µF ceramic capacitor, rated for at least 25 V, must be should be grounded to analog ground (AGND). The PVDD decoupling capacitors should connect to PGND. connected from each output to its corresponding bootstrap input. Specifically, one 0.22µF capacitor must be connected from OUTP to BSP, and one 0.22µF capacitor Analog ground and power ground should be connected at the thermal pad, which should be used as a central ground connection or star ground for the APA2614. must be connected from OUTN to BSN. The bootstrap capacitors connected between the BSP or 4.Output filter— The ferrite EMI filter (Figure 3) should be placed as close to the output terminals as possible for BSN pins and corresponding output function as a floating power supply for the high-side N-channel power the best EMI performance. The LC filter (Figure 4 and Figure 5) should be placed close to the outputs. The MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source capacitors used in both the ferrite and LC filters should be grounded to power ground. voltage high enough to keep the high-side MOSFETs turned on. 5.Thermal Pad— The thermal pad must be soldered to the PCB for proper thermal performance and optimal reliability. The dimensions of the thermal pad and thermal land should be 6.46 mm by 2.35mm. Seven rows Layout Recommendation of solid vias (three vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the The APA2614 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the Class-D switching edges are fast, it is neces- thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom sary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. EMC requirements. Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 16 www.anpec.com.tw APA2614 Layout Recommendation(Cont.) 2.0mm 0.7mm 3.0mm 2.7mm 0.65mm 1.5mm 6.5mm 0.254mm 2.5mm 0.45mm Via diameter = 0.3mm x 8 Via diameter = 0.3mm x 9 6.4mm QFN4x4-28 Land Pattern Recommendation TSSOP-28P Land Pattern Recommendation Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 17 www.anpec.com.tw APA2614 Package Information TSSOP-28P D SEE VIEW A E2 EXPOS ED PAD E1 E D1 c 0.25 b S Y M B O L VIEW A L GAUGE PLANE SEATING PLANE 0 A1 A2 A e TSSOP-28P INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.20 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 0.008 c 0.09 0.20 0.004 D 9.60 9.80 0.378 0.386 D1 4.50 6.00 0.177 0.236 0.260 E 6.20 6.60 0.244 E1 4.30 4.50 0.169 0.177 E2 2.50 3.50 0.098 0.138 0.75 0.018 8o 0o e 0.65 BSC L 0.45 0 0o 0.026 BSC 0.030 8o Note : 1. Followed from JEDEC MO-153 AET. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 18 www.anpec.com.tw APA2614 Package Information QFN4x4-28 D b E A Pin 1 A1 A3 D2 L K E2 Pin 1 Corner e S Y M B O L QFN4x4-28 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.17 0.27 0.007 0.011 D 3.90 4.10 0.154 0.161 D2 2.10 2.50 0.083 0.098 E 3.90 4.10 0.154 0.161 2.50 0.083 0.098 0.45 0.014 E2 2.10 e 0.45 BSC L 0.35 K 0.20 Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 0.016 BSC 0.018 0.008 19 www.anpec.com.tw APA2614 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application QFN4x4-28 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 (mm) Devices Per Unit Package Type QFN4x4-28 Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 Unit Tape & Reel Quantity 3000 20 www.anpec.com.tw APA2614 Carrier Tape & Reel Dimensions P1 P2 P0 D0 B0 W F E1 A D1 K0 A0 B A B SECTION A-A SECTION B-B H A d T1 Application TSSOP-28P A H T1 C d D W E1 F 330.0±2.00 50 MIN. 16.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 16.0±0.30 1.75±0.10 7.50±0.10 P0 P1 P2 D0 D1 T A0 B0 K0 4.00±0.10 12.00±0.10 2.00±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.9±0.20 10.20.±0.20 1.50±0.20 (mm) Devices Per Unit Package Type TSSOP-28P Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 Unit Tape & Reel Quantity 2000 21 www.anpec.com.tw APA2614 Taping Direction Information TSSOP-28P USER DIRECTION OF FEED QFN4x4-28 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 22 www.anpec.com.tw APA2614 Classification Profile Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 23 www.anpec.com.tw APA2614 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3 °C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 24 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2614 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Jan., 2013 25 www.anpec.com.tw