ANPEC APL5324BI-TRL

APL5324
Adjustable Low Dropout 300mA Linear Regulator
Features
General Description
•
•
The APL5324 is a P-channel low dropout linear regulator
which needs only one input voltage from 2.7 to 6V, and
Wide Operating Voltage: 2.7~6V
Low Dropout Voltage:
delivers current up to 300mA to set output voltage. It also
can work with low ESR ceramic capacitors and is ideal for
300mV(Typical) @ 300mA
•
•
•
•
•
•
•
using in the battery-powered applications such as notebook computers and cellular phones. Typical dropout volt-
Guaranteed 300mA Output Current
Adjustable Output Voltage: 0.8~5.5V
age is only 300mV at 300mA loading.
Current limit with current foldback and thermal shutdown
Current-Limit Protection with Foldback Current
functions protect the device against current over-loads
and over temperature. The APL5324 is available in a SOT-
Over-Temperature Protection
Stable with Low ESR Ceramic Capacitor
23-5 package.
SOT-23-5 Package
Lead Free and Green Devices Available
Pin Configuration
(RoHS Compliant)
Applications
VIN 1
GND 2
5 VOUT
4 SET
SHDN 3
•
•
•
Cellular Phones
SOT-23-5
Portable and Battery-Powered Equipment
Notebook and Personal Computers
Simplified Application Circuit
APL5324
VIN
1
CIN
3
VIN
VOUT
5
SHDN
SET 4
GND
VOUT
COUT
2
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2013
1
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APL5324
Ordering and Marking Information
Package Code
B: SOT-23-5
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
L : Lead Free Device
G : Halogen and Lead Free Device
APL5324
Assembly Material
Handling Code
Temperature Range
Package Code
APL5324
B:
24RX
X - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
VIN
VSHDN
(Note 1)
Rating
Unit
VIN Supply Voltage (VIN to GND)
Parameter
-0.3 ~ 6.5
V
SHDN Input Voltage (SHDN to GND)
-0.3 ~ 6.5
V
PD
Power Dissipation
TJ
Junction Temperature
Internally Limited
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
W
-40 ~ 150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol
Parameter
θJA
Thermal Resistance-Junction to Ambient
θJC
Thermal Resistance-Junction to Case
Typical Value
Unit
(Note 2)
SOT-23-5
SOT-23-5
240
o
130
o
C/W
C/W
Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol
VIN
Parameter
VIN Supply Voltage
Range
Unit
2.7 ~ 6
V
VOUT
Output Voltage
0.8 ~ 5.5
V
IOUT
VOUT Output Current
0 ~ 300
mA
CIN
Input Capacitor
0.22 ~ 100
µF
Output Capacitor
1.5 ~ 100
µF
Junction Temperature
-40 ~ 125
o
COUT
TJ
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APL5324
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN = VOUT+1V, IOUT=0~300mA, CIN = 1µF, COUT = 2.2µF, TA = -40 to 85oC.
Typical values are at TA = 25oC.
Symbol
VIN
VOUT
Parameter
APL5324
Test Conditions
Unit
Min.
Typ.
Max.
Input Voltage
2.7
-
6
V
Output Voltage Range
0.8
-
5.5
V
IQ
Quiescent Current
IOUT =10mA ~300mA
-
135
160
µA
VREF
Reference Voltage
Measured on SET, VIN=3V, IOUT=10mA
-
0.8
-
V
Output Voltage Accuracy
IOUT=10mA
-2
-
+2
%
Line Regulation
∆VOUT%/∆VIN, IOUT=10mA
-0.06
-
+0.06
%/V
∆VOUT%/∆IOUT
-0.2
-
+0.2
%/A
VOUT = 2.5V, IOUT = 300mA
-
500
650
VOUT = 3.3V, IOUT = 300mA
-
300
400
Power Supply Ripple Rejection Ratio
f = 10kHz, IOUT = 300mA
-
45
-
dB
Noise
f = 80Hz to 100kHz, IOUT = 300mA
-
160
-
µVRMS
450
550
-
mA
-
80
-
mA
SHDN Input Voltage High
1.6
-
-
SHDN Input Voltage Low
-
-
0.4
REGLINE
REGLOAD Load Regulation
VDROP
PSRR
Dropout Voltage
ILIMIT
Current Limit
ISHORT
Foldback Current
VOUT = 0V
mV
V
VOUT Discharge MOSFET RDS(ON)
SHDN = Low
-
60
-
Ω
Shutdown VIN Supply Current
SHDN = Low, VIN = 6V
-
0.1
1
µA
SHDN Pull Low Resistance
-
3
-
MΩ
Over Temperature Threshold
-
160
-
o
o
Over Temperature Hysteresis
SET Input Bias Current
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2013
VSET=0.8V
3
-
40
-
-100
-
100
C
C
nA
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APL5324
Typical Operating Characteristics
Quiescent Current vs. Supply Voltage
Quiescent Current vs. Junction Temperature
160
138
IOUT= 0mV
136
Quiescent Current, IQ (µA)
Quiescent Current, IQ (µA)
140
120
100
80
60
40
134
132
130
128
20
126
-50
0
0
1
2
3
4
5
6
7
-25
Supply Voltage, V IN (V)
50
75
100
125
(o C)
Dropout Voltage vs. Output Current
400
0
Dropout Voltage, VDROP(mV)
VIN=3.3V, VOUT=1.2V,
COUT=2.2µF,IOUT=300mA
-10
-20
PSRR(dB)
25
Junction Temperature, T J
PSRR vs. Frequency
-30
-40
-50
-60
VOUT=3.3V
350
o
TJ=125oC TJ=75 C
300
250
200
150
100
TJ=-50oC
50
-70
TJ=25oC
0
-80
1000
10000
100000
0
100
200
300
Output Current, I OUT(mA)
Frequency(Hz)
Current Limit vs. Junction Temperature
Dropout Voltage vs. Output Current
700
600
VOUT=2.5V
600
VIN=5V
o
TJ=125oC
500
TJ=75 C
Current Limit, ILIMIT(mA)
Dropout Voltage, VDROP(mV)
0
400
300
200
TJ=-50oC
100
550
500
VIN=3.3V
450
TJ=25oC
400
-50
0
0
100
200
300
0
25
50
Junction Temperature,
Output Current, IOUT(mA)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2013
-25
4
75
100
125
T J(oC)
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APL5324
Typical Operating Characteristics (Cont.)
Phase vs. Frequency
Loop Gain vs. Frequency
160
50
VIN=3.3V, VOUT=1.2V,
CIN=1µF, COUT=2.2µF
40
IOUT=100mA
20
10
0
-10
80
60
IOUT=100mA
20
-30
-40
IOUT=300mA
100
40
IOUT=300mA
-20
VIN=3.3V, VOUT=1.2V,
CIN=1µF, COUT=2.2µF
120
Phase (degree)
Loop Gain (dB)
30
140
0
1000
10000
100000
1000
1000000
100000
1000000
Frequency (Hz)
Frequency (Hz)
Copyright  ANPEC Electronics Corp.
Rev. A.1 - Jan., 2013
10000
5
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APL5324
Operating Waveforms
Enable
CH1
Shutdown
SHDN
SHDN
CH1
VIN
VIN
CH2
CH2
CH3
VOUT
VOUT
CH3
I OUT
IOUT
CH4
CH4
CH1 : SHDN , 5V/div
CH2 : VIN , 5V/div
CH3 : VOUT , 2V/div
CH4 : IOUT , 100mA/div
Time : 200µs/div
CH1 : SHDN , 5V/div
CH2 : VIN , 5V/div
CH3 : VOUT , 2V/div
CH4 : IOUT , 100mA/div
Time : 10µs/div
Load Transient
V IN=5V ; C I N=1µF ;
C OUT =2.2µF ; T R =1µs
Line Transient
C IN=1 µF ; C OUT =2.2µF ;
T R =5µs ; I OUT =10mA
VOUT
CH1
V IN
VOUT
I OUT
CH2
CH2
CH1
CH1 : VIN , 1V/div DC
CH2 : VOUT , 50mV/div AC
Time : 20µs/div
CH1 : VOUT , 50mV/div AC
CH2 : IOUT , 100mA/div
Time : 20µs/div
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APL5324
Operating Waveforms (Cont.)
Power On
Power Off
VIN
VOUT
VOUT
CH2
CH2
I OUT
CH3
VIN
CH1
CH1
IOUT
CH3
CH1 : VIN , 2V/div
CH2 : VOUT , 2V/div
CH3 : IOUT , 100mA/div
Time : 2ms/div
CH1 : VIN , 2V/div
CH2 : VOUT , 2V/div
CH3 : IOUT , 100mA/div
Time : 10ms/div
Pin Description
PIN
FUNCTION
NO.
NAME
1
VIN
Voltage supply input pin.
2
GND
Ground pin.
3
SHDN
4
SET
5
VOUT
Shutdown control pin, logic high: enable; logic low: shutdown.
Connect this pin to an external resistor divider to adjust output voltage.
Regulator output pin.
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APL5324
Block Diagram
UVLO &
Shutdown
Logic
SHDN
VIN
Thermal
Shutdown
Foldback
Current
Limit
+
0.8V
3MΩ
VOUT
SET
GND
Typical Application Circuit
VIN
1
VIN
3
CIN
1µF
VOUT
SET
SHDN
GND
VOUT
5
4
R1
COUT
2.2µF
2
Enable
R2
Shutdown
R1 

VOUT = 0.8 ⋅  1 +

 R2 
Designation
CIN
CIN
COUT
COUT
Supplier
Murata
Murata
Murata
Murata
Part Number
GRM185R61A105KE36
GRM188R71A105KA61
GRM188R61A225KE34
GRM188R71A225KE15
Specification
0603, X5R, 10V, 1µF
0603, X7R, 10V, 1µF
0603, X5R, 10V, 2.2µF
0603, X7R, 10V, 2.2µF
Reference: www.murata.com
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APL5324
Function Description
Output Voltage Regulation
The APL5324 is an adjustable low dropout linear
regulator. The output voltage set by the resistor-divider is
determined by:
R1 

VOUT = 0.8 ⋅  1 +

R2 

Where R1 is connected from VOUT to SET with Kelvin
sensing and R2 is connected from SET to GND. The recommended value of R2 is in the range of 100 to100kΩ.
An error amplifier works with a temperature compensated
0.8V reference and an output PMOS regulates the output
to the presetting voltage. The error amplifier is designed
with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the
reference with the feedback voltage and amplifies the difference to drive the output PMOS which provides load
current from VIN to VOUT.
Thermal Shutdown
A thermal shutdown circuit limits the junction temperature of APL5324. When the junction temperature exceeds
+160οC, a thermal sensor turns off the output PMOS, allowing the device to cool down. The regulator regulates
the output again through initiation of a new soft-start cycle
after the junction temperature is cooled down by 40oC.
The thermal shutdown is designed with a 40oC hysteresis to lower the average junction temperature during
continuous thermal overload conditions, extending lifetime of the device.
For normal operation, device power dissipation should
be externally limited so that junction temperature will not
exceed 125oC.
Shutdown Control
The APL5324 has an active-low shutdown function. Force
SHDN high (>1.6V) enables the VOUT; force SHDN low
(<0.4V) disables the VOUT. SHDN is internally pulled low
by a resistor (3mΩ typical). If it is not used, connect to VIN
for normal operation.
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APL5324
Application Information
Input Capacitor
Operation Region and Power Dissipation
The APL5324 requires proper input capacitors to supply
surge current during stepping load transients to prevent
The APL5324 maximum power dissipation depends on
the thermal resistance and temperature difference be-
the input rail from dropping . Because the parasitic inductor from the voltage sources or other bulk capacitors to
tween the die junction and ambient air. The power dissipation PD across the device is:
the VIN limit the slew rate of the surge current, place the
Input capacitors near VIN as close as possible. Input ca-
PD = (TJ - TA) / θJA
where (TJ-TA) is the temperature difference between the
junction and ambient air. θ JA is the thermal resistance
pacitors should be larger than 1µF and a minimum ceramic capacitor of 1µF is necessary.
Output Capacitor
between Junction and ambient air. Assuming the
TA=25 oC and maximum TJ=160 oC (typical thermal limit
The APL5324 needs a proper output capacitor to maintain circuit stability and to improve transient response over
threshold), the maximum power dissipation is calculated as:
temperature and current. In order to insure the circuit
stability, the proper output capacitor value should be larger
PD(max)=(160-25)/240
= 0.56(W)
than 2.2µF. With X5R and X7R dielectrics, 2.2µF is sufficient at all operating temperatures. Large output capaci-
For normal operation, do not exceed the maximum junction temperature rating of TJ = 125 oC. The calculated power
dissipation should less than:
tor value can reduce noise and improve load-transient
response and PSRR, however, it also affects power on
PD =(125-25)/240
= 0.41(W)
issue. Equation (1) shows the relationship between the
maximum COUT value and the VOUT.
C OUT(max) = 101 −
The GND provides an electrical connection to the ground
and channels heat away. Connect the GND to the ground
by using a large pad or a ground plane.
19.5
VOUT
Layout Consideration
Where the unit of COUT is µF and VOUT is V. Figure 1 shows
the curve of maximum output capacitor over the output
Figure 2 illustrates the layout. Below is a checklist for
voltage. The output voltage range is from 0.8 to 5.5V and
the output capacitor value should under the line. Output
your layout:
1. Please place the input capacitors close to the VIN.
capacitors must be placed at the load and the ground pin
as close as possible and the impedance of the layout
2. Ceramic capacitors for load must be placed near the
load as close as possible.
must be minimized.
3. To place APL5324 and output capacitors near the load
is good for performance.
Output Capacitor (µF)
120
4. Large current paths, the bold lines in figure 2, must
have wide tracks.
110
5. Divider resistor R1 and R2 must be placed near the
SET as close as possible.
100
90
80
70
60
0
1
2
3
4
5
6
Output Voltage (V)
Figure 1
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APL5324
Application Information (Cont.)
Layout Consideration (Cont.)
CIN
APL5324
VIN
VOUT
SET
VIN
1
VOUT
5
4
R1
COUT
GND
2
LOAD
R2
Figure 2
Recommended Minimum Footprint
SOT-23-5
1.27
2.54
1.9
0.95
0.50
Unit : mm
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APL5324
Package Information
SOT-23-5
D
e
E
E1
SEE
VIEW A
b
c
0.25
A
L
0
GAUGE PLANE
SEATING PLANE
A1
A2
e1
VIEW A
S
Y
M
B
O
L
SOT-23-5
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
MAX.
A
0.057
1.45
0.00
0.15
0.000
0.006
A2
0.90
1.30
0.035
0.051
b
0.30
0.50
0.012
0.020
0.009
A1
c
0.08
0.22
0.003
D
2.70
3.10
0.106
0.122
E
2.60
3.00
0.102
0.118
1.80
0.055
0.071
E1
1.40
e
0.95 BSC
e1
0.037 BSC
1.90 BSC
0.075 BSC
L
0.30
0.60
0
0°
8°
0.012
0°
0.024
8°
Note : 1. Follow JEDEC TO-178 AA.
2. Dimension D and E1 do not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil
per side.
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APL5324
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
SOT-23-5
A
H
T1
C
d
D
W
E1
F
178.0±2.00
50 MIN.
8.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
8.0±0.30
1.75±0.10
3.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±0.10
4.0±0.10
2.0±0.05
1.5+0.10
-0.00
1.0 MIN.
0.6+0.00
-0.40
3.20±0.20
3.10±0.20
1.50±0.20
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOT-23-5
Tape & Reel
3000
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APL5324
Taping Direction Information
SOT-23-5
USER DIRECTION OF FEED
Classification Profile
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APL5324
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
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Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APL5324
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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