APW7158 Dual Synchronous Buck PWM Controllers Features General Description • Two Synchronous Buck Converters(OUT1,OUT2) • Converter Input Voltage Range up to 12V The APW7158 has two synchronous buck PWM controllers with high precision internal references voltage to of- • 0.6V Reference for OUT1 with 0.8% Accuracy • 3.3V Reference for OUT2 with 0.8% Accuracy • Both Outputs have Independent Soft-Start and fer accurate outputs. The PWM controllers are designed to drive two N-channel MOSFETs in synchronous buck topology. The device requires 12V and 5V power supplies. If the 5V supply is not available, the device can offer an optional shunt regulator 5.8V for 5V supply. Both outputs have independent soft-start and enable func- Enable Functions • Internal 300kHz Oscillator and Programmable Frequency Range from 70 kHz to 800kHz • tions combined on the SS/EN pin. Connecting a capacitor from each SS/EN pin to the ground for setting the soft- 180 Degrees Phase Shift etween OUT1 and OUT2 start time, and pulling the SS/EN pin voltage below 1V to • Short-Circuit Protection • disable regulator. The device also offers 180°phase shift Thermally Enhanced SOP-20 Package function between OUT1 and OUT2. • Lead Free and Green Devices Available The default switching frequency is 300kHz (keep the FS pin open or short to GND), and the device also provides (RoHS Compliant) the programmable switching frequency function to adjust the switching frequency from 70kHz to 800kHz. Con- Applications necting a resistor from FS pin to GND increases the switching frequency. Conversely, connecting a resistor • Graphic Cards • Low-Voltage Distributed Power Supplies • SMPS Application from FS pin to VCC12 decreases the switching frequency. There is no current sensing or under-voltage sensing on the APW7158. However, it provides a simple short-circuit protection by monitoring the COMP1 pin and COMP2 pin for over-voltage. When any of two pins exceed their trip point and the condition keeps for 1-2 internal clock cycles Simplified Application Circuit (3-6us at 300kHz), all regulators are latched off. VIN1 VOUT1 VOUT2 VCC Pin Configuration VCC12 APW7158 VOUT1 FB1 1 VIN2 19 BOOT1 COMP2 3 18 UGATE1 FB2 4 VOUT2 REFIN REFOUT SS1/EN1 SS2/EN2 20 VCC COMP1 2 17 VCC12 REFIN 5 16 LGATE1 REFOUT 6 15 LGATE2 SS1/EN1 7 14 PGND SS2/EN2 8 13 BOOT2 VREF 9 FS10 12 UGATE2 11 GND S ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 1 www.anpec.com.tw APW7158 Ordering and Marking Information Package Code K : SOP-20 Operating Ambient Temperature Range E : -20 to 70 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7158 Assembly Material Handling Code Temperature Range Package Code APW7158 K: APW7158 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1) Symbol VCC12 VCC, Separate Supply VUGATE1, VUGATE2, VBOOT1, VBOOT2 VLGATE1, VLGATE2 VFS VREFIN, VREFOUT, VREF VFB1, VCOMP1, VFB2, VCOMP2 VSS1/EN1, VSS2/EN2 TA TJ TSTG TSDR Parameter Rating Unit VCC12 to GND Voltage -0.3 to 20 V VCC, Separate Supply to GND Voltage -0.3 to 5.5 V UGATE1, UGATE2, BOOT1, BOOT2 to PGND Voltage -0.3 to 30 V LGATE1, LGATE2 to GND Voltage -0.3 to 20 V FS to GND Voltage -0.3 to 20 V REFIN, REFOUT, VREF to GND Voltage -0.3 to VCC V FB1, COMP1, FB2, COMP2 to GND Voltage -0.3 to VCC V SS1/EN1, SS2/EN2, to GND Voltage -0.3 to VCC V PGND to GND Voltage -0.3 to +0.3 Operating Temperature Range -20 to +70 o C +150 o C -65 to +150 o C 260 o C Maximum Junction Temperature Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA θJC Parameter Junction-to-Ambient Resistance in Free Air Typical Value Unit (Note 2) SOP-20 Junction-to-Case Resistance in Free Air (Note 3) SOP-20 75 o 20 o C/W C/W Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-20 package. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 2 www.anpec.com.tw APW7158 Recommended Operating Conditions (Note 4) Symbol VCC12 Parameter VCC12 Supply Voltage Range Unit 10.8 to 13.2 V VCC VCC Supply Voltage 4.5 to 5.5 V VIN Converter Input Voltage 2.2 to 13.2 V V VOUT Converter Output Voltage 0.6 to 5 IOUT Converter Output Current 0 to 20 A TA Ambient Temperature Range -20 to 70 o TJ Junction Temperature Range -20 to 125 o C C Note 4: Refer to the typical application circuit Electrical Characteristics Operating Conditions: VCC = 5V, VCC12 = 12V, TA = -20 to 70°C. Typical values are at TA =25°C. Unless Otherwise Specified. Symbol Parameter APW7158 Test Conditions Unit Min. Typ. Max. OUT1 and OUT2 disabled - 4 - mA UGATEs, LGATEs CL = 1nF, 300kHz - 7 - mA OUT1 and OUT2 disabled - 6 - mA UGATEs, LGATEs CL = 1nF, 300kHz - 50 - mA 5.6 5.8 6.0 V - - 60 mA 4.15 4.23 4.4 V VCC Falling 3.9 4.0 4.15 V VCC12 Rising 7.55 7.8 8 V VCC12 Falling 7.1 7.3 7.55 V OUT1 Reference Voltage - 0.6 - V OUT1 System Accuracy -0.8 - 0.8 % -20 - 20 % 300 360 kHz INPUT SUPPLY POWER IVCC IVCC12 VCC Input Supply Current VCC12 Input Supply Current Shunt Regulator Output Voltage 20mA current; Equivalent to 300Ω resistor from VCC to VCC12 Maximum Shunt Regulator Current VCC Rising Power-On-Reset Threshold Voltage SYSTEM ACCURACY OSCILLATOR Oscillator Accuracy FS Oscillator Frequency FS pin is open 240 Oscillator Adjustment Range FS pin: resistor to GND; resistor to VCC12 70 - 800 kHz Oscillator Sawtooth Amplitude - 2.1 - V Oscillator Duty-Cycle Range 0 - 85 % ERROR AMPLIFIER (OUT1 AND OUT2) Open-Loop Gain RL = 10kΩ to ground - 85 - dB Open-Loop Bandwidth CL = 100pF, RL = 10kΩ to ground - 15 - MHz Slew Rate CL = 100pF, RL = 10kΩ to ground - 4 - V/µS ERROR AMPLIFIER Offset Voltage COMP1/2 to FB1/2; compare to internal VREF/REFIN - 2 - mV Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 3 www.anpec.com.tw APW7158 Electrical Characteristics (Cont.) Operating Conditions: VCC = 5V, VCC12 = 12V, TA = -20 to 70°C. Typical values are at TA =25°C. Unless Otherwise Specified. Symbol Parameter APW7158 Test Conditions Unit Min. Typ. Max. ERROR AMPLIFIER (OUT1 AND OUT2) (CONT.) Maximum COMP High Voltage COMP1/2, RL = 10kΩ to ground; (may trip short-circuit) - VCC - V COMP Source Current COMP1/2, VCOMP=2V - -50 - mA COMP Sink Current COMP1/2, VCOMP=2V - 45 - mA Short-Circuit Protection Threshold VCOMP1 and VCOMP2 rising - 3.3 - V Short-Circuit Protection Filter Time Based on internal oscillator clock frequency (nominal 300kHz = 3.3µs clock period) 1 - 2 Clock pulses - 3.3 - V -0.8 - 0.8 % - - 2.0 mA PROTECTION AND MONITOR VREF VREF VREF Output Voltage VREF Output Accuracy VREF Source Current REFOUT VREFOUT REFOUT Output Voltage 0.6 - 3.3 V REFOUT Offset Voltage Determined by REFIN voltage -10 - 10 mV REFOUT Source Current - - 20 mA - - 0.48 mA 0.4 0.1 2.2 µF V REFOUT Sink Current REFOUT Output Capacitance ENABLE/SOFT-START (SS/EN 1,2) Enable Threshold Voltage High level input voltage 2 - - Low level input voltage - - 0.4 - -30 - µA End of ramp - 3.5 - V VUGATE1, VLGATE1=3V, VBOOT=12V - 1.8 - A SS/EN Pin Soft-Start Current Soft-Start High Voltage GATE DRIVERS OUT1 GATE Driver Source OUT2 GATE Driver Source VUGATE2, VLGATE2=3V, VBOOT=12V - 1 - A OUT1 GATE Driver Sink VUGATE1, VLGATE1=3V, VCC12=12V - 2.5 - Ω OUT2 GATE Driver Sink VUGATE2, VLGATE2=3V, VCC12=12V - 4 - Ω Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 4 www.anpec.com.tw APW7158 Typical Operating Characteristics REFOUT Voltage vs. Source Current VREF Voltage vs. Source Current 3.32 3.35 3.33 VREF Voltage, VREF (V) REFOUT Voltage, VREFOUT (V) 3.34 3.32 3.31 3.3 3.29 3.28 3.27 3.31 3.3 3.29 3.26 3.28 3.25 0 5 10 15 0 20 0.5 2 UGATE1 Source Current vs. Voltage UGATE1 Sink Current vs. Voltage 2.4 2.2 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 Source Current (A) Sink Current (A) 1.5 Source Current (mA) Source Current (mA) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 0 12 UGATE1 Voltage, VUGATE1 (V) 2 4 6 8 10 12 UGATE1 Voltage, VUGATE1 (V) LGATE1 Sink Current vs. Voltage 2.4 2.2 2.4 LGATE1 Source Current vs. Voltage 2.2 2 2 1.8 1.8 1.6 1.4 Source Current (A) Sink Current (A) 1 1.2 1 0.8 0.6 0.4 0.2 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 0 2 4 6 8 10 12 0 LGATE1 Voltage, VLGATE1 (V) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 2 4 6 8 10 12 LGATE1 Voltage, VLGATE1 (V) 5 www.anpec.com.tw APW7158 Typical Operating Characteristics (Cont.) UGATE2 Sink Current vs. Voltage UGATE2 Source Current vs. Voltage 1.6 1.4 BOOT=12V 1.4 BOOT=12V 1.2 Source Current (A) Sink Current (A) 1.2 1 0.8 0.6 0.4 0.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 0 12 0 UGATE2 Voltage, VUGATE2 (V) 1.6 1.4 1.4 1.2 1.2 1 Source Current (A) 1 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0 0 0 2 4 6 8 10 12 0 2 LGATE2 Voltage, VLGATE2 (V) 4 6 8 10 12 LGATE2 Voltage, VLGATE2 (V) FS Resistance vs. Switching Frequency Shunt Regulator Sink Current vs. Voltage 60 1000 FS to VCC12 900 50 800 700 Sink Current (mA) FS Resistance (kΩ) 12 LGATE2 Source Current vs. Voltage LGATE2 Sink Current vs. Voltage Sink Current (A) 2 4 6 8 10 UGATE2 Voltage, VUGATE2 (V) 600 500 400 FS to GND 300 200 100 40 30 20 10 0 0 100 200 300 400 500 600 700 800 0 3 Switching Frequency (kHz) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 6 3.5 4 4.5 5 5.5 6 Shunt Regulator Voltage (V) 6.5 7 www.anpec.com.tw APW7158 Typical Operating Characteristics (Cont.) COMP Source Current vs. Voltage 70 50 60 Source Current (mA) Sink Current (mA) COMP Sink Current vs. Voltage 60 40 30 20 50 40 30 20 10 10 0 0 0 0.5 1 1.5 2 2.5 3 0 1 COMP Voltage (V) 3 4 610 VREF Voltage vs. Junction Temperature 3.35 608 3.34 606 3.33 604 VREF Voltage (V) FB Voltage (mV) FB Voltage vs. Junction Temperature 2 COMP Voltage (V) 602 600 598 596 3.32 3.31 3.3 3.29 3.28 594 3.27 592 3.26 590 3.25 0 25 50 75 100 125 150 0 Junction Temperature (°C) Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 25 50 75 100 125 150 Junction Temperature (°C) 7 www.anpec.com.tw APW7158 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. OUT1 Power On 1 2 OUT2 Power On VCC12 1 VCC VCC 2 VOUT1 3 4 VCC12 3 VOUT2 VSS2/EN2 VSS1/EN1 4 CH1: VCC12, 5V/Div, DC CH1: VCC12, 5V/Div, DC CH2: VCC, 2V/Div, DC CH3: VOUT1, 2V/Div, DC CH4: VSS1/EN1, 2V/Div, DC CH2: VCC, 2V/Div, DC CH3: VOUT2, 2V/Div, DC CH4: VSS2/EN2, 2V/Div, DC TIME: 5ms/Div TIME: 5ms/Div Phase Shift 180 Degress VREF Output Voltage Power On VUGATE1 1 2 3 VCC12 1 VCC 2 VREF 3 VLGATE1 VUGATE2 VLGATE2 4 VSS2/N2 4 CH1: VCC12, 5V/Div, DC CH1: VUGATE1, 10V/Div, DC CH2: VCC, 2V/Div, DC CH3: VREF, 2V/Div, DC CH4: VSS2/EN2, 2V/Div, DC CH2: VLGATE1, 10V/Div, DC CH3: VUGATE2, 10V/Div, DC CH4: VLGATE2, 10V/Div, DC TIME: 5ms/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 TIME: 2μs/Div 8 www.anpec.com.tw APW7158 Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. OUT2 Short Circuit Protection OUT1 Short Circuit Protection VCOMP1 1 VCOMP2 VSS1/EN1 1 VUGATE1 VSS2/EN2 VUGATE2 2 2 3 3 CH1: VCOMP1, 2V/Div, DC CH1: VCOMP2, 2V/Div, DC CH2: VSS1/EN1, 2V/Div, DC CH3: VUGATE1, 20V/Div, DC TIME: 20μs/Div CH2: VSS2/EN2, 2V/Div, DC CH3: VUGATE2, 20V/Div, DC TIME: 20μs/Div OUT1 Load Transient IOUT1=0A->10A->0A IOUT1 rising/falling time=5μs OUT2 Load Transient IOUT2=0A->10A->0A IOUT2 rising/falling time=5μs VOUT1 1 VOUT1 1 VOUT2 VOUT2 2 2 IOUT1 IOUT1 3 3 CH1: VOUT1, 200mV/Div, AC CH1: VOUT1, 200mV/Div, AC CH2: VOUT2, 200mV/Div, AC CH3: IOUT1, 10A/Div, DC TIME: 50μs/Div CH2: VOUT2, 200mV/Div, AC CH3: IOUT2, 10A/Div, DC TIME: 50μs/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 9 www.anpec.com.tw APW7158 Operating Waveforms (Cont.) Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified. UGATE1 Voltage Rising UGATE1 Voltage Falling VUGATE1 VUGATE1 1 1 VPHASE1 VPHASE1 2 2 VLGATE1 3 3 VLGATE1 CH1: VUGATE1, 10V/Div, DC CH1: VUGATE1, 10V/Div, DC CH2: VPHASE1, 10V/Div, DC CH3: VLGATE1, 10V/Div, DC TIME: 100ns/Div CH2: VPHASE1, 10V/Div, DC CH3: VLGATE1, 10V/Div, DC TIME: 100ns/Div UGATE2 Voltage Falling UGATE2 Voltage Rising VUGATE2 VUGATE2 1 2 1 VPHASE2 VPHASE2 2 VLGATE2 VLGATE2 3 3 CH1: VUGATE2, 10V/Div, DC CH1: VUGATE2, 10V/Div, DC CH2: VPHASE2, 10V/Div, DC CH3: VLGATE2, 10V/Div, DC TIME: 100ns/Div CH2: VPHASE2, 10V/Div, DC CH3: VLGATE2, 10V/Div, DC TIME: 100ns/Div Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 10 www.anpec.com.tw APW7158 Pin Description PIN FUNCTION NO. NAME 1 FB1 2 COMP1 These pins are the outputs of error amplifiers of their respective regulators. They are used to set the compensation components. 3 COMP2 These pins are the outputs of error amplifiers of their respective regulators. They are used to set the compensation components. 4 FB2 These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components. 5 REFIN This pin is the reference input voltage of error amplifier of OUT2. It also provides the voltage into a buffer, which is out on the REFOUT pin. 6 REFOUT 7 SS1/EN1 8 SS2/EN2 9 VREF This pin provides a 3.3V reference voltage, which can be used by the REFIN pin or other ICs as a voltage reference. A 1µF capacitor to ground is recommended for stability. 10 FS This pin is used to adjust the switching frequency. Connecting a resistor from FS pin to GND increases the switching frequency. Conversely, connecting a resistor from this pin to VCC12 reduces the switching frequency. 11 GND 12 UGATE2 13 BOOT2 These pins provide the bootstrap voltage to the gate driver for driving the upper MOSFETs. A boostrap circuit may be used to create a BOOT voltage. 14 PGND This pin is the power ground for the gate driver circuits. It should be tied to the GND. 15 LGATE2 16 LGATE1 17 VCC12 18 UGATE1 These pins provide the gate driver for the upper MOSFETs of OUT1 and OUT2 respectively. 19 BOOT1 These pins provide the bootstrap voltage to the gate driver for driving the upper MOSFETs. A boostrap circuit may be used to create a BOOT voltage. 20 VCC These pins are the inverting inputs of the error amplifiers of their respective regulators. They are used to set the output voltage and the compensation components. This pin provides a buffed voltage, which is from REFIN pin. A 0.1µF capacitor to ground is recommended for stability. These pins provide two functions. Connect a capacitor to the GND for setting the soft-start time. Use an open drain logic signal to pull the SS/EN pin low to disable the respective output, leave it open to enable the respective output. This pin is the signal ground pin for the IC. These pins provide the gate driver for the upper MOSFETs of OUT1 and OUT2 respectively. These pins provide the gate driver for the lower MOSFETs of OUT1 and OUT2. Power Supply Input Pin. Connect a nominal 12V power supply to this pin for the gate driver circuits. A decoupling capacitor (1 to 10µF) to GND is recommended for noise decoupling. Power Supply Input Pin. Connect a nominal 5V power supply to this pin for the control circuits, or connect a resistor (nominally 300Ω) to VCC12 to function this pin as a shunt regulator (typical 5.8V). A decoupling capacitor (1 to 10µF) to GND is recommended for noise decoupling. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 11 www.anpec.com.tw APW7158 Block Diagram VCC VREF VCC12 5.8V 30µA Power-On-Reset and Control SS1/EN1 3.3V BOOT1 Bias Current 0.6V 3.3V Gate Control Logic 1 30µA UGATE1 LGATE1 SS2/EN2 Oscillator COMP1 BOOT2 0.6V FB1 Gate Control Logic 2 UGATE2 3.3V LGATE2 REFIN 1-2 Clock Cycle Filter FS FB2 REFOUT COMP2 GND Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 PGND 12 www.anpec.com.tw APW7158 Typical Application Circuit 12V R2 300Ω R3 300Ω C7 1µF R1 5.1Ω C5 1µF 12V VCC R4 8.2kΩ R6 1kΩ D1 BAT54A VCC12 COMP1 R7 12kΩ C9 33nF VOUT1 UGATE1 C3 2200µF ALE C4 2200µF ALE VOUT1 5V L2 7.3µH LGATE1 Q2 APM2566N COMP2 R9 12kΩ C15 33nF C2 10µF MLCC C8 Q1 0.1µF APM2510N R5 1.1kΩ C6 22nF C1 10µF MLCC C25 0.1µF BOOT1 FB1 C16 5.6nF VOUT2 L1 1µH 12V_FLTR C13 5.6nF C14 2200µF D3 BSCD24 R8 2.2Ω C10 1µF C11 2200µF ALE C12 2200µF ALE R10 8.2kΩ FB2 R12 NC R11 1kΩ C17 22nF VCC12 APW7158 12V_FLTR D2 BAT54A R16 0Ω VREF C26 0.1µF REFIN C27 0.1µF C24 0.1µF Q3 APM2510N VOUT2 3.3V L3 7.3µΗ REFOUT LGATE2 R13 360kΩ C23 10µF MLCC BOOT2 R17 NC UGATE2 VCC12 C22 10µF MLCC Q4 APM2566N VREF D4 BSCD24 C28 2200µF C29 1µF C31 2200µF ALE C30 2200µF ALE R14 2.2Ω FS/SYNC SS1/EN1 SS2/EN2 C18 C21 0.1µF 1µF R15 C19 NC 0.1µF C20 0.1µF GND Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 PGND 13 www.anpec.com.tw APW7158 Function Description Phase Shift Until the VSS reaches about 3.0V, the internal reference completes the soft-start interval and reaches to 0.6V, and The device offers 180° phase shift function between OUT1 then VOUT is in regulation. The VSS still rises to 3.5V and then stops. and OUT2. The advantage of Phase shift is to avoid overlapping the switching current spikes of the two channels or interaction between the channels; it also reduces the VOLTAGE RMS current of the input capacitors, allowing fewer caps to be employed. However, because the phase shift between the rising edge of VLGATE1 and VLGATE2 (See Figure 1.) depends on the duty cycles, the falling edges of the VSS/EN 3V two channels might overlap. Therefore, the user should check it. V UGATE 1 VOUT 1V V LGATE 1 t0 V UGATE 2 t1 t2 TIME Figure 2. Soft-Start Interval V LGATE 2 0o TSOFT − START = t 2 − t1 = 180 o Figure 1. Phase of VLGATE2 with respect to rising edge of VLGATE1 CSS ⋅ 2V ISS Where: CSS = external Soft-Start capacitor ISS = Soft-Start current = 30µ A Soft-Start/Enable The SS/EN pins control the soft-start and enable or dis- Shunt Regulator able the controller. The two regulators have independent soft-start and enable functions. Connect a soft-start ca- The APW7158 must have two power supplies VCC (5V) and VCC12 (12V) to drive the IC; VCC (5V) is for the control circuits and VCC12 (12V) is for the drivers of outputs. The pacitor from each SS/EN pin to the GND to set the softstart interval, and an open drain logic signal for each SS/ shunt regulator is designed for these systems like figure 3 that do not have a 5V power supply; the range of the EN pin will enable or disable the respective output. Figure 2 shows the soft-start interval. When both VCC and shunt regulator voltage (5.8V, typical) is designed over the usual range 4.5V to 5.5V of typical 5V power supplies. VCC12 reach their Power-On-Reset threshold 4.23V and 7.8V, a 30µA current source starts to charge the capacitor. Connect a resistor from VCC12 pin to VCC pin for shunt When the VSS reaches the enabled threshold about 1V, the internal 0.6V reference starts to rise and follows the regulator and for the supply current; the typical value, 300Ω of the resistor is recommended. VSS; the error amplifier output (VCOMP) suddenly raises to 1.1V, which is the valley of the oscillator’s triangle wave, and leads the VOUT to start up. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 14 www.anpec.com.tw APW7158 Function Description (Cont.) Shunt Regulator (Cont.) Short-Circuit Protection VCC(5.8V) The APW7158 has a simple short-circuit protection to monitor COMP1 pin and COMP2 pin for OUT1 and OUT2. VCC12 R When output voltage has a short, the FB pin should start to follow output since it is a resistor divider from the output. The FB pin is the inverting input of Error-Amp. When FB pin is lower than the Error-Amp reference, the VCOMP will rise to increase the duty-cycle of the upper MOSFET gate driver, and this allows output to get higher voltage. If the VCC VCC12 short-circuit condition is long enough, the VCOMP will exceed the trip point 3.3V and the duty circle will hit the APW7158 maximum. This means that either Over-Current or Under-Voltage condition is detected. If any of the VCOMP1 and Figure 3. Optional R for Shunt Regulator VCOMP2 exceed their trip points and hold over a filter time (1-2 clock cycles of switching frequency), all regulators Oscillator will shut down and require a POR on either of VCC or The APW7158 provides the oscillator switching frequency adjustment. Connect a resistor from FS pin to the ground; VCC12 pin to restart. the nominal 300kHz oscillator switching frequency is increased according to the value of the resistor. Thus, the adjustment range of the switching frequency is nominal 300kHz to 800kHz. Conversely, connecting a resistor from FS pin to the VCC12 pin reduces the switching frequency according to the value of the resistor. Thus, the adjustment range of the switching frequency is 70kHz to nominal 300kHz. (See Figure 4.). 1000 FS to VCC12 900 FS Resistance (kΩ) 800 700 600 500 400 FS to GND 300 200 100 0 0 100 200 300 400 500 600 700 800 Switching Frequency (kHz) Figure 4. FS Resistance vs. Frequency Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 15 www.anpec.com.tw APW7158 Application Information PWM Compensation The PWM modulator is shown in Figure. 7. The input is the output of the error amplifier and the output is the The output LC filter of a step down converter introduces a double pole, which contributes with –40dB/decade gain PHASE node. The transfer function of the PWM modulator is given by: slope and 180 degrees phase shift in the control loop. A compensation network between V COMP, VFB and VOUT should GAIN PWM = be added. The compensation network is shown in Fig. 8. The out- VIN put LC filter consists of the output inductor and output capacitors. The transfer function of the LC filter is given Driver PWM Comparator by: GAINLC = VOSC 1 + s × ESR × C OUT s 2 × L × COUT + s × ESR × C OUT + 1 Output of Error Amplifier The poles and zero of this transfer function are: FLC = FESR VPHASE 1 2 × π × L × COUT Driver 1 = 2 × π × ESR × C OUT Figure 7. The PWM Modulator The FLC is the double poles of the LC filter, and FESR is The compensation circuit is shown in Figure 8. It provides a close loop transfer function with the highest zero the zero introduced by the ESR of the output capacitor. VPHASE VIN ∆VOSC crossover frequency and sufficient phase margin. L VOUT The transfer function of error amplifier is given by: COUT GAIN AMP ESR 1 1 // R2 + sC1 sC2 VCOMP = = VOUT 1 R1// R3 + sC3 1 1 s + × s + R2 × C2 (R1 + R3) × C3 R1 + R3 = × R1× R3 × C1 C1 + C2 1 s s + × s + R2 × C1× C2 R3 × C3 Figure 5. The Output LC Filter The poles and zeros of the transfer function are: FLC -40dB/dec FZ1 = 1 2 × π × R2 × C2 FZ2 = 1 2 × π × (R1 + R3) × C3 FP1 = 1 C1 × C2 2 × π × R2 × C1 + C2 FP 2 = 1 2 × π × R3 × C3 Gain FESR -20dB/dec Frequency Figure 6. The LC Filter Gain & Frequency Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 16 www.anpec.com.tw APW7158 Application Information (Cont.) PWM Compensation (Cont.) 5. Set the second pole FP2 at half the switching frequency and also set the second zero FZ2 at the output LC filter C1 R3 C3 R2 double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the com- C2 pensation gain at FP2 with the capabilities of the error amplifier. VOUT R1 VFB VCOMP FP2 = 0.5xFO FZ2 = FLC Combine the two equations will get the following component calculations: + VREF Figure 8. Compensation Network The closed loop gain of the converter can be written as: GAIN LC × GAIN PWM × GAIN AMP R3 = R1 FS −1 2 × FLC C3 = 1 π × R3 × FS Figure 9. Shows the asymptotic plot of the closed loop Open Loop Error Amp Gain converter gain and the following guidelines will help to design the compensation network. Using the below Gain guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade FZ1=0.75FLC FP1=FESR FP2=0.5FS FZ2=FLC slope and a phase margin greater than 45 degree. 20log (R2/R1) 1. Choose a value for R1, usually between 1K and 5K. 2. Select the desired zero crossover frequency FO: (1/5 ~ 1/10) x FS >FO>FESR 0 FLC Use the following equation to calculate R2: R2 = ∆VOSC VIN × FO FLC 20log (VIN/ VOSC) Compensation Gain × R1 FO FESR PWM & Filter Gain 3. Place the first zero FZ1 before the output LC filter double pole frequency FLC. Converter Gain Frequency FZ1 = 0.75 x FLC Figure 9. Converter Gain & Frequency Calculate the C2 by the equation: C2 = Output Inductor Selection 1 2 × π × R2 × FLC × 0.75 The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR value reduces the inductor’s ripple current and induces lower output ripple voltage. The ripple current and ripple Calculate the C1 by the equation: voltage can be approximated by: C2 C1 = 2 × π × R2 × C2 × FESR − 1 IRIPPLE = VIN − VOUT FS × L × VOUT VIN ∆VOUT = IRIPPLE × ESR Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 17 www.anpec.com.tw APW7158 Application Information (Cont.) Output Inductor Selection (Cont.) they are surge tested by the manufactures. If in doubt, Where Fs is the switching frequency of the regulator. Although increase the inductor value and frequency reduce consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1uF can be connected the ripple current and voltage, but there is a tradeoff exists between the inductor’s ripple current and the regula- between the drain of upper MOSFET and the source of lower MOSFET. tor load transient response time. A smaller inductor will give the regulator a faster load MOSFET Selection The selection of the N-channel power MOSFETs are de- transient response at the expense of higher ripple current. Increasing the switching frequency (FS) also reduces the termined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement. The losses in ripple current and voltage, but it will increase the switching loss of the MOSFET and the power dissipation of the the MOSFETs have two components: conduction loss and transition loss. For the upper and lower MOSFET, the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose losses are approximately given by the following : PUPPER=IOUT(1+TC)(RDS(ON))D+(0.5)(IOUT)(VIN)(tSW)FS the ripple current to be approximately 30% of the maximum output current. PLOWER=IOUT(1+TC)(RDS(ON))(1-D) Where Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak cur- I is the load current OUT TC is the temperature dependency of RDS(ON) rent without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple F is the switching frequency S t is the switching interval current will increase abruptly when it saturates. This will result in a larger output ripple voltage. sw D is the duty cycle Note that both MOSFETs have conduction losses while the upper MOSFET include an additional transition loss. Output Capacitor Selection The switching internal, tsw, is a function of the reverse transfer capacitance CRSS. Higher Capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore select high performance low ESR capacitors that are intended for The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) switching regulator applications. In some applications, multiple capacitors have to be parallel to achieve the de- vs Temperature” curve of the power MOSFET. sired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the Short Circuit Protection they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. The APW7158 provides a simple short circuit protection function, and it is not easy to predict its performance, since many factors can affect how well it works. Therefore, the limitations and suggestions of this method must be provided for users to understand how to work it well. Input Capacitor Selection • voltage rating of the output capacitors are also must be considered. If tantalum capacitors are used, make sure for the output in initial short condition. In this case, the The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select short circuit protection may not work, and damage the MOSFETs. If the circuit still works, remove the short can the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. cause an inductive kick on the phase pin, and it may damage the IC and MOSFETs. The maximum RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power • up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 The short circuit protection was not designed to work If the resistance of the short is not low enough to cause protection, the regulator will work as the load has 18 www.anpec.com.tw APW7158 Application Information (Cont.) • Short Circuit Protection (Cont.) upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the increased, and continue to regulate up until the MOSFETs is damaged. The resistance of the short should include output capacitor GND and the lower MOSFET GND. • The drain of the MOSFETs (VIN and phase nodes) wiring, PCB traces, contact resistances, and all of the return paths. • The input capacitor should be near the drain of the should be a large plane for heat sinking. The higher duty cycle will give a higher COMP voltage level, and it is easy to touch the trip point. The compensa- VIN tion components also affect the response of COMP APW7158 UG voltage; smaller caps may give a faster response. • CBOOT The output current has faster rising time during short; FB the COMP pin will have a sharp rise. However, if the cur- CREFOUT rent rises too fast, it may cause a false trip. The output capacitance and its ESR can affect the rising time of the CVREF current during short. REFOUT Layout Consideration Q2 LG VREF PGND VCC SS VCC12 CSS VOUT Q1 BOOT L1 CIN COUT L O A D CVCC12 CVCC GND In high power switching regulator, a correct layout is im- Figure 10. Layout Guidelines portant to ensure proper operation of the regulator. In general, interconnecting impedances should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and finally combined using ground plane construction or single point grounding. Figure 10 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout : • The metal plate of the bottom of the packages (SOP- 20) must be soldered to the PCB and connected to the GND plane on the backside through several thermal vias. • Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. • The traces from the gate drivers to the MOSFETs (UGATE1, LGATE1, UGATE2, LGATE2) should be short and wide. • Decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and SS capacitors should be close their pins. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 19 www.anpec.com.tw APW7158 Package Information SOP-20 D h X 45o E1 E SEE VIEW A e c A L 0 GAUGE PLANE SEATING PLANE A1 A2 0.25 b VIEW A S Y M B O L SOP-20 MILLIMETERS MIN. MAX. MIN. MAX. 2.65 A A1 INCHES 0.104 0.012 0.004 0.30 0.10 0.081 A2 2.05 b 0.31 0.51 0.012 0.020 c 0.20 0.33 0.008 0.013 D 12.60 13.00 0.496 0.512 E 10.10 10.50 0.398 0.413 7.60 0.291 0.299 E1 7.40 e 1.27 BSC 0.050 BSC h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 0 0o 8o 0o 8o Note : 1. Follow from JEDEC MS-013 AC. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 20 www.anpec.com.tw APW7158 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-20 A H T1 C 24.40+2.00 13.0+0.50 -0.00 -0.20 d D W E1 F 1.5 MIN. 20.2 MIN. 24.0±0.30 1.75±0.10 11.5±0.10 330.0±2.00 50 MIN. P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 12.0±0.10 2.0±0.10 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 10.9±0.20 13.3±0.20 3.1±0.20 (mm) Devices Per Unit Package Type Unit Quantity SOP-20 Tape & Reel 1000 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 21 www.anpec.com.tw APW7158 Taping Direction Information SOP-20 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 22 www.anpec.com.tw APW7158 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 23 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APW7158 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Aug., 2009 24 www.anpec.com.tw