APW7181 Full-Bridge Inverter Gate Driver Features General Description • Wide Input Voltage Range: 4.5V to 13.2V • Drives a Full-Bridge Inverter(High-Side P- The APW7181 is designed to drive two high-side P-channel MOSFETs and two low-side N-channel MOSFETs in a full-bridge configuration. The outputs are independently controlled by PWM1 and PWM2 input signals. Channel MOSFETs and Low-Side N-Channel MOSFETs) • Thermal Shutdown Protection • VCC Power-On-Reset • SOP-8 Package • Lead Free and Green Devices Available The other features include VCC power-on-reset and thermal shutdown. Simplified Application Circuit VIN (RoHS Compliant) PGATE1 Applications • NGATE1 LCD Monitor and LCD TV PWM2 PWM2 PGATE2 1 8 PGATE1 PWM1 2 7 NGATE1 VIN PGATE2 PWM CONTROLLER APW7181 GND 3 PWM1 LAMP Pin Configuration PWM1 NGATE2 6 VCC PWM2 4 5 NGATE2 APW7181 SOP-8 TOP VIEW Ordering and Marking Information Package Code K: SOP-8 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW7181 Assembly Material Handling Code Temperature Range Package Code APW7181 K: APW7181 XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 1 www.anpec.com.tw APW7181 Absolute Maximum Ratings Symbol VCC (Note 1) Parameter Rating Unit -0.3 to 16 V -0.3 to VCC+0.3 V VCC Pin to GND PGATEs, NGATEs Pins to GND PWM1, PWM2 Pins to GND TJ -0.3 to 16 Maximum Junction Temperature TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds V 150 o -65 to 150 o 260 o C C C Note 1 : Stresses beyond the absolute maximum rating may damage the device and exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics (Note 2) Symbol θJA Parameter Typical Value Unit 150 °C/W Junction to Ambient Thermal Resistance SOP-8 Note 2 :θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. Recommended Operating Conditions Symbol VCC VPWM1, VPWM2 CVCC Parameter VCC to GND PWM1, PWM2 Pins to GND VCC Pin Input Capacitor (MLCC) Range Unit 4.5 to 13.2 V 0 to 13.2 V 1 to 10 µF TJ Junction Temperature -40 to 125 °C TA Ambient Temperature -40 to 85 °C Electrical Characteristics Refer to the typical application circuit. These specifications apply over VCC=12V, TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter Test Conditions Min. APW7181 Typ. Max. Unit POWER SUPPLY VPWM1=VPWM2=0V - 400 600 µA VPWM1=VPWM2=VCC - 550 750 µA VCC POR Threshold VCC rising 2 3 4.1 V VIH PWMs Logic High Threshold VCC=4.5V to 13.2V 3.2 - - V VIL PWMs Logic Low Threshold VCC=4.5V to 13.2V - - 1.2 V PWMs Input Current VPWMs=13.2V - 13.2 - µA IQ VCC Quiescent Current LOGIC INPUT IPWMs Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 2 www.anpec.com.tw APW7181 Electrical Characteristics (Cont.) Refer to the typical application circuit. These specifications apply over VCC=12V, TA= -40~85°C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter Test Conditions APW7181 Min. Typ. Max. Source Current=0.1A, VCC=12V - 3.1 4.9 Source Current =0.1A, VCC=5V - 5 8 Sink Current=0.1A, VCC=12V - 5.3 9.1 Sink Current =0.1A, VCC=5V - 8.5 14.6 Unit TOP DRIVER Gate Source Resistance Gate Sink Resistance Ω BOTTOM DRIVER Gate Source Resistance Gate Sink Resistance Source Current =0.1A, VCC =12V - 6.2 10 Source Current =0.1A, VCC =5V - 10 16 Sink Current =0.1A, VCC =12V - 2.4 4 Sink Current =0.1A, VCC =5V - 3.9 7 PWMs rising to PGATEs rising, VCC=5~12V - 50 100 PWMs falling to NGATEs falling, VCC=5~12V - 50 100 250 350 450 225 375 525 250 350 450 225 375 525 - 150 - °C - 40 - °C Ω TIMING tp Propagation Delay td1_12V Delay Time1 td1_5V td2_12V Delay Time2 td2_5V PGATEs rising to NGATEs rising, VCC=12V, TA= -40°C ~85°C PGATEs rising to NGATEs rising, VCC=5V, TA= -40°C ~85°C NGATEs falling to PGATEs falling, VCC=12V, TA=-40°C ~85°C NGATEs falling to PGATEs falling, VCC=5V, TA=-40°C ~85°C ns ns ns THERMAL SHUTDOWN Thermal Shutdown Threshold TJ rising Thermal Shutdown Hysteresis Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 3 www.anpec.com.tw APW7181 Typical Operating Characteristics Delay Time vs. Junction Temperature Delay Time vs. VCC Supply Voltage 500 400 TA=25oC Vcc=12V 450 Delay Time (ns) Delay Time (ns) Delay Time2 (td2) 380 360 Delay Time1 (td1) 340 400 Delay Time1 (td1) 350 Delay Time2 (td2) 300 320 250 200 -50 300 4 6 10 8 12 14 500 VCC Quiescent current, IQ (µA) Delay Time (ns) 450 400 Delay Time2 (td2) Delay Time1 (td1) 300 250 50 75 100 125 150 TA=25oC VPWM＝0V 450 400 350 300 250 200 -25 0 25 50 75 100 125 4 150 6 10 8 12 (oC) VCC Supply Voltage, VCC (V) VCC Supply Current vs. Junction Temperature VCC Supply Current vs. PWM Frequency Junction Temperature, TJ 700 100000 PWM1=PWM2 Frequency=60kHz VCC Supply Current (µA) VCC=12V VCC Supply Current (µA) 25 500 Vcc=5V 200 -50 0 VCC Quiescent Current vs. VCC Supply Voltage Delay Time vs. Junction Temperature 350 -25 Junction Temperature, TJ (oC) VCC Supply Voltage, VCC (V) 650 600 550 500 14 VCC=12V CL = 4700pF TA=25oC Both Inputs Enable CL = 2200pF 10000 1000 CL = 0F 100 -50 -25 0 25 50 75 100 125 150 10 Junction Temperature, TJ (oC) Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 100 1000 PWM Frequency (kHz) 4 www.anpec.com.tw APW7181 Typical Operating Characteristics (Cont.) NGATE Source/Sink Resistance vs. Junction Temperature PGATE Source/Sink Resistance vs. Junction Temperature 8 Source/Sink Resistance (Ω) 7 6 Source/Sink Resistance (Ω) 8 IPGATE source current=0.1A IPGATE sink current=0.1A VCC=12V Sink 5 4 Source 3 2 1 INGATE source current=0.1A INGATE sink current=0.1A 7 Source VCC=12V 6 5 4 3 Sink 2 1 0 0 -50 -25 0 25 50 75 100 125 -50 150 -25 Junction Temperature, TJ (oC) 0 25 50 75 100 125 150 Junction Temperature, TJ (oC) Pin Description PIN FUNCTION NO. NAME 1 PGATE2 2 PWM1 3 GND 4 PWM2 5 NGATE2 6 VCC 7 NGATE1 Low-Side Gate Driver Output for N-channel MOSFET of Channel 1. 8 PGATE1 High-Side Gate Driver Output for P-channel MOSFET of Channel 1. High-Side Gate Driver Output for P-channel MOSFET of Channel 2. Input PWM Signal for Channel 1. Ground. Input PWM Signal for Channel 2. Low-Side Gate Driver Output for N-channel MOSFET of Channel 2. Power Supply Input. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 5 www.anpec.com.tw APW7181 Block Diagram VCC PGATE1 Driver NGATE1 Driver PGATE2 Driver Hysteresis Driver PWM1 POR NGATE2 Delay Time Control Thermal Shutdown PWM2 Hysteresis Delay Time Control GND Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 6 www.anpec.com.tw APW7181 Typical Application Circuit F1 VIN 10µFx4 R1 10k Fuse R2 10k D2 D1 5V or 12V C5 6 PGATE1 VCC C7 PGATE2 C4 Q3 8 2.2µF 2 Q1 C1 C2 C3 1 T1 0.047µF C6 CCFL 0.047µF PWM1 7 Q2 Q4 NGATE1 4 PWM2 NGATE2 5 GND Q1, Q3 : APM4015P 3 Q2, Q4 : APM4010N Timing Diagram PWM PGATE NGATE tp Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 td1 tp 7 td2 www.anpec.com.tw APW7181 Function Description Application Information Thermal Shutdown Layout Consideration ο If the junction temperature exceeds 150 C, the thermal shutdown circuit will pull PGATE outputs high and NGATE In any high switching frequency application, a correct layout is important to ensure proper operation of the device. outputs low thus turning high-side and low-side MOSFET off. When the driver cools down below 110οC after a ther- With power devices switching at high frequency, the resulting current transient will cause voltage spike across mal shutdown, it resumes normal operation and follows the PWM input signals. the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition Power-On-Reset (POR) of the PWM MOSFET. Before turn-off, the MOSFET is carrying the full load current. During turn-off, current stops The APW7181 provides the power-on-reset function that keeps the driver disable when the VCC voltage is insuffi- flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of cient to driver external MOSFETs reliably. The PGATE outputs remain high and the NGATE outputs remain low the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed until the VCC voltage exceeds POR threshold. Once the POR threshold is reached, the condition of gate driver circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. Below is a outputs is defined by the PWM signals. checklist for your layout : - Keep the switching nodes (PGATE, NGATE and the State PGATE NGATE PWM L L L Signal H H H H L Thermal Shutdown drain of the MOSFETs) away from sensitive small signal nodes (PWM1, PWM2, MS, and DTC ) since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - Place the drain of the P-MOSFET and the drain of the NMOSFET as close as possible to minimize the imped ance with wide layout plane between the two pads and Table 1. Truth Table reduce the voltage bounce of the node. - The traces from the gate drivers to the MOSFETs (PGATE and NGATE) should be short and wide. - The VCC decoupling capacitor (C7), C5, C6, and RDTC should be close to their pins. - The input capacitor should be near the source of the P-MOSFET. - The drain of the MOSFETs should be a large plane for heat sinking. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 8 www.anpec.com.tw APW7181 Package Information SOP-8 D E E1 SEE VIEW A h X 45 ° c A 0.25 b GAUGE PLANE SEATING PLANE A1 A2 e L VIEW A S Y M B O L SOP-8 MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 1.75 0.069 0.004 0.25 0.010 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0 0° 8° 0° 8° Note: 1. Follow JEDEC MS-012 AA. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension “E” does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 9 www.anpec.com.tw APW7181 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-8 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.40±0.20 5.20±0.20 2.10±0.20 (mm) Devices Per Unit Package Type SOP-8 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 Quantity 2500 10 www.anpec.com.tw APW7181 Taping Direction Information SOP-8 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 11 www.anpec.com.tw APW7181 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak (Tp)* package body Temperature Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Volume mm Thickness <350 <2.5 mm 235 °C ≥2.5 mm 220 °C Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 3 Volume mm 350-2000 260 °C 250 °C 245 °C Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item Method Description SOLDERABILITY JESD-22, B102 5 Sec, 245°C HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C TCT JESD-22, A104 500 Cycles, -65°C~150°C ESD JESD-22, A114; A115 VHBM≧2KV, VMM≧200V Latch-Up JESD 78 10ms, 1tr≧100mA Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 12 www.anpec.com.tw APW7181 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.2 - Jan., 2009 13 www.anpec.com.tw