ANPEC APW8805A

APW8805A
3A 5V 1MHz Synchronous Buck Converter
Features
General Description
•
High Efficiency up to 95%
APW8805A is a 3A synchronous buck converter with inte-
•
Adjustable Output Voltage from 0.6V to VVIN
•
Integrated 75mΩ High Side / 55mΩ Low Side
grated 75mΩ high side and 55mΩ low side power
MOSFETs. The APW8805A, design with a current-mode
control scheme, can convert wide input voltage of 2.6V to
6V to the output voltage adjustable from 0.6V to 6V to
MOSFETs
•
Low Dropout Operation: 100% Duty Cycle
•
Mode Selection
provide excellent output voltage regulation.
The APW8805A is equipped with force PWM mode
- APW8805A : Force PWM
opeation.
The APW8805A is also equipped with Power-on-reset,
•
Stable with Low ESR Ceramic Capacitors
•
Power-On-Reset Detection on VCC and VIN
•
Integrated Soft-Start and Soft-Stop
•
Over-Temperature Protection
•
Over-Voltage Protection
single package.
This device, available TDFN3x3-10, provides a very com-
•
Under-Voltage Protection
pact system solution external components and PCB area.
•
High/ Low Side Current Limit
•
Power Good Indication
•
Enable/Shutdown Function
•
Current-Mode Operation with Internal
soft-start, soft-stop, and whole protections (under-voltage,
over-voltage, over-temperature and current-limit) into a
Compensation
•
Small TDFN3x3-10 Packages
•
Lead Free and Green Devices Available
Simplified Application Circuit
(RoHS Compliant)
Applications
•
•
VIN
VOUT
Notebook Computer & UMPC
VIN
SW
VCC
FB
APW8805A
LCD Monitor/TV
•
Set-Top Box
•
DSL, Switch HUB
•
Portable Instrument
(option)
POK
ON
OFF
GND
EN
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
1
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APW8805A
Ordering and Marking Information
APW8805A
Assembly Material
Handling Code
Temperature Range
Package Code
APW8805A QB :
APW
8805A
XXXXX
Package Code
QB : TDFN3x3-10
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
APW8805A
FB 1
VCC 2
VIN 3
GND 4
GND 5
11
GND
10 EN
9 POK
8 NC
7 SW
6 SW
TDFN 3X3-10
(Top View)
11
GND Exposed pad
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Rating
Unit
VVIN, VVCC
Input Supply Voltage
-0.3 ~ 6.5
V
VSW
SW to GND Voltage
-1 ~VVCC+0.3
V
-0.3 ~ 6.5
V
POK, FB, EN to GND Voltage
PD
Power Dissipation
Internally Limited
W
TJ
Junction Temperature
150
o
TSTG
Storage Temperature
-65 ~ 150
o
C
C
o
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
260
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
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APW8805A
Thermal Characteristics
Symbol
θJA
θJC
Parameter
Junction-to-Ambient Resistance in Free Air
Typical Value
Unit
(Note 2)
o
TDFN3x3-10
50
TDFN3x3-10
10
C/W
Junction-to-Case Resistance in Free Air (Note 3)
o
C/W
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of SOP-8P or TDFN3x3-10 is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P or TDFN3x3-10 package.
Recommended Operating Conditions (Note 4)
Parameter
Symbol
VVCC
Control and Driver Supply Voltage
VVIN
Input Supply Voltage
VOUT
L
IOUT
Range
Unit
2.6~ 6
V
2~6
V
Converter Output Voltage
0.6~6
V
Inductance
1~2.2
µH
Converter Output Current
0~3
A
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
C
C
Note 4: Refer to the typical application circuit.
Electrical Characteristics
Unless otherwise specified, these specifications apply over VVCC=VVIN=5V, VOUT=3.3V, TA=25oC.
Symbo
Parameter
APW8805A
Test Conditions
Min.
Typ.
Unit
Max.
SUPPLY CURRENT
VCC Supply Current
VFB=0.7V
-
460
-
µA
IVCC_SDH VCC Shutdown Supply Current
EN=GND
-
-
1
µA
2.3
2.4
2.5
V
-
0.2
-
V
1.5
1.7
1.9
V
-
0.2
-
V
-
0.8
-
V
-1
-
+1
%
-1.5
-
+1.5
%
IVCC
POWER-ON-RESET (POR)
VCC POR Voltage Threshold
VVCC Rising
VCC POR Hysteresis
VIN POR Voltage Threshold
VIN POR Hysteresis
REFERENCE VOLTAGE
VREF
Reference Voltage
All temperature
Output Accuracy
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
IOUT=10mA~3A, VVCC=2.6~5V
3
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APW8805A
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VVCC=VVIN=5V, VOUT=3.3V, TA=25oC.
Symbo
Parameter
APW8805A
Test Conditions
Unit
Min.
Typ.
Max.
0.85
1
1.15
MHz
-
100
-
%
-
100
-
ns
-
75
90
mΩ
-
55
75
mΩ
-
-
10
µA
-
550
-
µA/V
-
80
-
dB
Current Sense Transresistance
-
400
-
mΩ
Dead Time
-
20
-
ns
4
5
6
A
Over-Temperature Trip Point
-
160
-
°C
Over-Temperature Hysteresis
-
50
-
°C
Over-Voltage Protection Threshold
120
-
135
%VREF
Under-Voltage Protection Threshold
45
50
55
%VREF
Soft-Start Time
-
1
-
ms
EN Enable Threshold
-
-
1.4
V
0.5
-
-
V
87
90
93
%VOUT
POK Low Hysteresis
(POK Goes Low)
-
5
-
%VOUT
POK in from Higher
(POK Goes High)
122
125
128
%VOUT
-
5
-
%VOUT
-
100
-
Ω
OSCILLATOR AND DUTY CYCLE
FOSC
Oscillator Frequency
Maximum Converter’s Duty
VFB=0.7V
Minimum on Time
POWER MOSFET
High Side P-MOSFET Resistance
Low Side N-MOSFET Resistance
VVCC=5V, ISW =0.5A, TA=25oC
o
VVCC=5V, ISW =0.5A, TA=25 C
High/Low Side MOSFET Leakage
Current
CURRENT-MODE PWM CONVERTER
Gm
Error Amplifier Transconductance
Error Amplifier DC Gain
TD
COMP=NC
PROTECTIONS
ILIM
TOTP
High Side MOSFET Current-Limit
Peak Current
SOFT-START, ENABLE, AND INPUT CURRENTS
EN Shutdown Threshold
POK in from Lower
(POK Goes High)
POK Threshold
POK High Hysteresis
(POK Goes Low)
Power Good Pull Low Resistance
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APW8805A
Typical Operating Characteristics
Refer to the “Typical Application Circuit”. The test condition is VVCC=VVIN=5V, TA= 25oC unless otherwise specified.
Efficiency vs. Load Current
100
90
90
Efficiency (%)
Efficiency (%)
Efficiency vs. Load Current
100
80
VVCC=5V
70
80
70
VVIN=5V
V VIN=3.3V
60
60
V OUT=1.8V
VOUT=3.3V
50
50
0
1
2
Load Current, IOUT(A)
0
3
1
2
Load Current, IOUT(A)
3
Output Voltage vs. Load Current
Efficiency vs. Load Current
1.9
100
1.88
Output Voltage, VOUT(V)
Efficiency (%)
90
80
70
VVIN=5V
VVIN=3.3V
60
VOUT=1.05V
1.86
1.84
1.82
1.8
1.78
1.76
1.74
1.72
50
0
1
2
Load Current, IOUT(A)
1.7
3
0
1
1.5
2
Load Current, IOUT(A)
2.5
3
Supply Voltage vs. MOSFET On
Supply Voltage vs. P-FET Current
Limit
Resistance
100
MOSFET On Resistance, RON(mΩ)
6
P-FET Current Limit, ILIM(A)
0.5
5
4
3
2
1
90
80
70
60
50
40
P-FET
30
N-FET
20
10
0
0
2
3
4
5
Supply Voltage, VVIN(V)
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
2
6
5
3
4
5
Supply Voltage, VVIN(V)
6
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APW8805A
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified.
Shutdown
Enable without Loading
1
VEN
VEN
1
2
2
VPOK , 5V/Div
VPOK , 5V/Div
VOUT , 1V/Div, DC
3
3
4
VOUT , 1V/Div, DC
4
IL , 1A/Div
IL , 1A/Div
TIME: 200µs/Div
TIME: 200µs/Div
Enable with 1.8A Loading
1
Shutdown
VEN
VEN
VPOK , 5V/Div
1
2
2
VPOK , 5V/Div
VOUT , 1V/Div, DC
VOUT , 1V/Div, DC
3
3
4
4
IL , 1A/Div
IL , 1A/Div
TIME: 200µs/Div
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
TIME: 200µs/Div
6
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APW8805A
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=5V, TA= 25oC unless otherwise specified.
Load Transient Response
Load Transient Response
1.5A
2.5A
1A
IOUT , 1A/Div
10mA
IOUT , 1A/Div
1
1
2
2
VOUT , 100mV/Div, AC
VOUT , 100mV/Div, AC
TIME: 20µs/Div
TIME: 50µs/Div
Over Voltage Protection
Normal Operating Waveform
V SW , 5V/Div
1
VPOK , 5V/Div
1
V OUT , 20mV/Div, DC
VOUT , 1V/Div, DC
2
2
3
IL , 1A/Div
IL , 1A/Div
3
TIME: 1µs/Div
TIME: 20µs/Div
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APW8805A
Pin Description
NO.
NAME
FUNCTION
1
FB
Output Feedback Input. The APW8805A senses the feedback voltage via FB and regulates
the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’s output sets the
output voltage.
2
VCC
Signal Input. VCC supplies the control circuitry, gate drivers. Connecting a ceramic bypass
capacitor from VCC to GND to eliminate switching noise and voltage ripple on the input to the
IC.
3
VIN
Power Input. VIN supplies the step-down converter switches. Connecting a ceramic bypass
capacitor from VIN to GND to eliminate switching noise and voltage ripple on the input to the
IC.
4,5
GND
Ground. Power and signal ground.
6,7
SW
Power Switching Output. SW is the Junction of the high-side and low-side Power MOSFETs
to supply power to the output LC filter.
8
NC
No connection.
9
POK
Power Good Output. This pin is open-drain logic output that is pulled to the ground when the
output voltage is out of regulation point.
10
EN
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on
the regulator, drive it low to turn it off.
11
Ground and Exposed pad. Connect the exposed pad to the system ground plan with large
GND
(Exposed Pad) copper area for dissipating heat into the ambient air.
Copyright  ANPEC Electronics Corp.
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APW8805A
Block Diagram
VIN
VCC
Current
Sense
Amplifier
LOC
Over
Temperature
Protection
PowerOnReset
Current
Limit
Zero Crossing
Comparator
POR
125%V REF
OTP
OVP
Fault
Logics
50%VREF
UVP
Inhibit
125%V REF
Gate
Control
SW
POK
90%VREF
Current
Compartor
Error
Amplifier
FB
Gate
Driver
Gat
e
Gm
Soft-start
V REF
0.8V
Slope
Compensation
Oscillator
Shutdown
EN
LOC
Current
Sense
Amplifier
GND
POK
Copyright  ANPEC Electronics Corp.
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APW8805A
Typical Application Circuit
L1
1.5µH
VIN
VIN
R3
100k
CIN
22µF
SW
C1
(option)
VCC
APW8805A
ON
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
R1
4.7k
FB
POK
OFF
VOUT
1.05V/3A
COUT
22µFx2
R2
15k
GND
EN
10
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APW8805A
Function Description
VCC and VIN Power-On-Reset (POR)
with a 50oC hysteresis to lower the average TJ during
The APW8805A keeps monitoring the voltage on VCC
and VIN pins to prevent wrong logic operations which
continuous thermal overload conditions, increasing lifetime of the APW8805A.
may occur when VCC or VIN voltage is not high enough
for internal control circuitry to operate. The VCC POR ris-
Current-Limit Protection
The APW8805A monitors the output current, flows through
the high-side and low-side power MOSFETs, and limits
ing threshold is 2.4V (typical) with 0.2V hysteresis and
VIN POR rising threshold is 1.7V with 0.2V hysteresis.
the current peak at current-limit level to prevent the IC
from damaging during overload, short-circuit and over-
During start-up, the VCC and VIN voltage must exceed
the enable voltage threshold. Then, the IC starts a start-
voltage conditions. Typical high side power MOSFET current limit is 5A.
up process and ramps up the output voltage to the voltage target.
Output Under-Voltage Protection (UVP)
Soft-Start
In the operational process, if a short-circuit occurs, the
output voltage will drop quickly. Before the current-limit
circuit responds, the output voltage will fall out of the re-
The APW8805A has a built-in soft-start to control the rise
rate of the output voltage and limit the input current surge
quired regulation range. The under-voltage continually
monitors the FB voltage after soft-start is completed. If a
during start-up. During soft-start, an internal voltage ramp
connected to one of the positive inputs of the error
load step is strong enough to pull the output voltage lower
than the under-voltage threshold, the IC starts soft-stop
amplifier, rises up to replace the reference voltage (0.8V)
until the voltage ramp reaches the reference voltage. Dur-
function and shuts down converter’s output.
ing soft-start without output over-voltage, the APW8805A
converter’s sinking capability is disabled until the output
The under-voltage threshold is 50% of the nominal output voltage. The under-voltage comparator has a built-in
voltage reaches the voltage target.
3µs noise filter to prevent the chips from wrong UVP shutdown being caused by noise. APW8805A will be latched
Soft-Stop
after under-voltage protection.
At the moment of shutdown controlled by EN signal, under-voltage event or over-voltage event, the APW8805A
Over-Voltage Protection (OVP)
initiates a soft-stop process to discharge the output voltage in the output capacitors. Certainly, the load current
The over-voltage function monitors the output voltage by
also discharges the output voltage. During soft-stop, the
internal voltage ramp (VRAMP) falls down to replace the
FB pin. When the FB voltage increases over 125% of the
reference voltage due to the high-side MOSFET failure or
reference voltage. Therefore, the output voltage falls down
slowly at the light load. After the soft-stop interval elapses,
for other reasons, the over-voltage protection comparator
will trigger soft-stop function and shutdown the converter
the soft-stop process ends and the IC turns.
output.
Over-Temperature Protection (OTP)
The over-temperature circuit limits the junction temperature of the APW8805A. When the junction temperature
Enable and Shutdown
Driving EN to ground places the APW8805A in shutdown.
exceeds TJ=+160oC, a thermal sensor turns off the both
power MOSFETs, allowing the devices to cool. The ther-
In shutdown mode, the internal N-Channel power
MOSFET turns off, all internal circuitry shuts down and
mal sensor allows the converters to start a start-up process and to regulate the output voltage again after the
the quiescent supply current reduces to less than 1µA.
junction temperature cools by 50oC. The OTP is designed
Copyright  ANPEC Electronics Corp.
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APW8805A
Function Description (Cont.)
Powr Good Indicator
POK is actively held low in shutdown and soft-start status.
In the soft-start process, the POK is an open-drain. When
the soft-start is finished, the POK is released. In normal
operation, the POK window is from 90% to 125% of the
converter reference voltage. When the output voltage has
to stay within this window, POK signal will become high.
When the output voltage outruns 90% or 125% of the
target voltage, POK signal will be pulled low immediately.
In order to prevent false POK drop, capacitors need to
parallel at the output to confine the voltage deviation with
severe load step transient.
Copyright  ANPEC Electronics Corp.
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APW8805A
Application Information
shown in “Typical Application Circuits”. A suggestion of
maximum value of R2 is 20kΩ to keep the minimum cur-
Input Capacitor Selection
Because buck converters have a pulsating input current,
a low ESR input capacitor is required. This results in the
rent that provides enough noise rejection ability through
the resistor divider. The output voltage can be calculated
best input voltage filtering, minimizing the interference
with other circuits caused by high input voltage spikes.
as below:
 R1 
 R1 
VOUT = VREF ⋅ 1+
 = 0.8 ⋅ 1 +

 R2 
 R2 
Also, the input capacitor must be sufficiently large to stabilize the input voltage during heavy load transients. For
good input voltage filtering, usually a 22µF input capacitor
is sufficient. It can be increased without any limit for better
VOUT
input-voltage filtering. Ceramic capacitors show better
performance because of the low ESR value, and they are
R1≤80Ω
less sensitive against voltage transients and spikes compared to tantalum capacitors. Place the input capacitor as
FB
R2 ≤ 20kΩ
APW8805A
close as possible to the input and GND pin of the device
for better performance.
GND
Inductor Selection
Output Capacitor Selection
For high efficiencies, the inductor should have a low DC
The current-mode control scheme of the APW8805A allows the use of tiny ceramic capacitors. The higher ca-
resistance to minimize conduction losses. Especially at
high-switching frequencies, the core material has a
pacitor value provides the good load transients response.
Ceramic capacitors with low ESR values have the lowest
higher impact on efficiency. When using small chip
inductors, the efficiency is reduced mainly due to higher
output voltage ripple and are recommended. If required,
tantalum capacitors may be used as well. The output
inductor core losses. This needs to be considered when
selecting the appropriate inductor. The inductor value de-
ripple is the sum of the voltages across the ESR and the
ideal output capacitor.
termines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the
lower the conduction losses of the converter. Conversely,
larger inductor values cause a slower load transient
∆VOUT
response. A reasonable starting point for setting ripple
current, ∆IL, is 40% of maximum output current. The rec-

V
VOUT ⋅ 1 − OUT
VIN

≅
FSW ⋅ L


 
1
 ⋅  ESR +

⋅
8
F
SW ⋅ COUT





When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
ommended inductor value can be calculated as below:
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.


V
VOUT 1 − OUT 
VIN 

L≥
FSW ⋅ ∆IL
IL(MAX) = IOUT(MAX) + 1/2 x ∆IL
VIN
IIN
To avoid the saturation of the inductor, the inductor should
be rated at least for the maximum output current of the
IP-FET
IL
converter plus the inductor ripple current.
CIN
IOUT
P-FET
VOUT
SW
Output Voltage Setting
N-FET
In the adjustable version, the output voltage is set by a
resistive divider. The external resistive divider is con-
ESR
COUT
nected to the output, allowing remote voltage sensing as
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APW8805A
Application Information (Cont.)
Output Capacitor Selection (Cont.)
Via To VOUT
IL
R2
R1
ILIM
IPEAK
CIN
IP-FET
SW
IOUT
VCC GND
∆IL
COUT
L1
VOUT
APW8805A Layout Consideration
ThermalVia diameter
12mil X 5
Layout Consideration
For all switching power supplies, the layout is an important step in the design; especially at high peak currents
0.75
Ground plane for
ThermalPAD
0.275
0.3
and switching frequencies. If the layout is not carefully
done, the regulator might show noise problems and duty
2.70
cycle jitter.
1. The input capacitor should be placed close to the VIN
and GND. Connecting the capacitor and VIN/GND with
short and wide trace without any via holes for good
input voltage filtering. The distance between VIN/GND
0.5
to capacitor less than 2mm respectively is
recommended.
1.75
TDFN3x3-10
2. To minimize copper trace connections that can inject
noise into the system, the inductor should be placed
as close as possible to the SW pin to minimize the
noise coupling into other circuits.
Unit: mm
APW8805A Recommended Footprint
3. The output capacitor should be place closed to SW
and GND.
4. Since the feedback pin and network is a high impedance circuit the feedback network should be routed
away from the inductor. The feedback pin and feedback network should be shielded with a ground plane
or trace to minimize noise coupling into this circuit.
5. A star ground connection or ground plane minimizes
ground shifts and noise is recommended.
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APW8805A
Package Information
TDFN3x3-10
A
b
E
D
Pin 1
A1
D2
A3
L
E2
Pin 1
Corner
e
S
Y
M
B
O
L
TDFN3x3-10
MILLIMETERS
MAX.
0.80
0.028
0.031
0.05
0.000
0.002
0.007
MAX.
A
0.70
A1
0.00
A3
INCHES
MIN.
MIN.
0.20 REF
0.008 REF
0.012
b
0.18
0.30
D
2.90
3.10
0.114
0.122
0.087
0.106
D2
2.20
2.70
E
2.90
3.10
0.114
0.122
1.75
0.055
0.069
E2
1.40
e
0.50 BSC
L
0.30
K
0.20
0.020 BSC
0.012
0.50
0.020
0.008
Note : 1. Followed from JEDEC MO-229 VEED-5.
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APW8805A
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TDFN3x3-10
A
H
T1
C
d
D
W
E1
F
330.0±
2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±0.20
3.30±
0.20
1.30±
0.20
4.0±
0.10
8.0±0.10
(mm)
Devices Per Unit
Package Type
TDFN3x3-10
Unit
Tape & Reel
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
Quantity
3000
16
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APW8805A
Taping Direction Information
TDFN3x3-10
USER DIRECTION OF FEED
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
17
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APW8805A
Classification Profile
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
18
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APW8805A
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Aug., 2013
19
www.anpec.com.tw