DM54L74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Connection Diagram Dual-In-Line Package TL/F/6631 – 1 Order Number DM54L74J or DM54L74W See NS Package Number J14A or W14B Function Table Inputs Outputs PR CLR CLK D Q Q L H L H H H H L L H H H X X X X X X H L X H L H* H L QO L H H* L H QO u u L H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level u e Positive-going transition. QO e The output logic level of Q before the indicated input conditions were established. * e This configuration is nonstable; that is, it will not persist when either the preset and/or clear inputs returned to their inactive (high) level. C1995 National Semiconductor Corporation TL/F/6631 RRD-B30M105/Printed in U. S. A. DM54L74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 8V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54L b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol DM54L74 Parameter VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 2) tW Pulse Width (Note 2) Nom Max 4.5 5 5.5 2 0 Clock High 75 Clock Low 75 Preset Low 75 Clear Low V V 0.7 V b 0.2 mA 2 mA 6 MHz ns 75 tSU Input Setup Time (Notes 1 & 2) 50u tH Input Hold Time (Notes 1 & 2) 15u TA Free Air Operating Temperature b 55 Note 1: The symbol ( Units Min u) indicates the rising edge of the clock pulse is used for reference. Note 2: TA e 25§ C and VCC e 5V. 2 ns ns 125 §C Electrical Characteristics Symbol over recommended operating free air temperature (unless otherwise noted) Parameter Conditions VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIL e Max, VIH e Min II Input Current @ Max Input Voltage VCC e Max VI e 5.5V IIH IIL High Level Input Current Low Level Input Current Min Typ (Note 1) 2.4 3.3 Max V 0.15 0.3 D VCC e Max VI e 2.4V VCC e Max VI e 0.3V 300 Preset 200 Clock 200 D 10 Clear 30 Preset 20 Clock 20 D b 0.18 Clear b 0.36 Preset b 0.18 Clock b 0.36 IOS Short Circuit Output Current ICC Supply Current VCC e Max (Note 2) V 100 Clear VCC e Max Units b3 1.6 mA mA mA b 15 mA 3 mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the time of measurement, the clock input is grounded. Switching Characteristics Symbol at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Parameter From (Input) To (Output) RL e 4 kX, CL e 50 pF Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Preset to Q 6 60 ns tPHL Propagation Delay Time High to Low Level Output Preset to Q 120 ns tPLH Propagation Delay Time Low to High Level Output Clear to Q 60 ns tPHL Propagation Delay Time High to Low Level Output Clear to Q 120 ns tPLH Propagation Delay Time Low to High Level Output Clock to Q or Q 10 90 ns tPHL Propagation Delay Time High to Low Level Output Clock to Q or Q 10 120 ns 3 MHz DM54L74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs Physical Dimensions inches (millimeters) 14-Lead Ceramic Dual-In-Line Package (J) Order Number DM54L74J NS Package Number J14A 14-Lead Ceramic Flat Package (W) Order Number DM54L74W NS Package Number W14B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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