AOSMD AOZ1214

AOZ1214
EZBuck 3A™ Simple Buck Regulator
with Linear Controller
General Description
Features
The AOZ1214 is a high efficiency, simple to use, buck
regulator plus one linear regulator controller optimized for
a variety of applications.
z 4.5V to 28V operating input voltage range
The AOZ1214 works from a 4.5V to 28V wide input
voltage range. The buck regulator provides up to 3A of
continuous output current. Each output voltage is
adjustable down to 0.8V. The buck regulator and LDO
can be enabled independently.
z Internal soft start
The AOZ1214 is available in a 4x3 DFN-12 package and
can operate over a -40°C to +85°C ambient temperature
range.
z Short-circuit protection
z Integrated linear regulator controller
z 40 mΩ internal NFET, efficiency: up to 95%
z Each output voltage adjustable down to 0.8V
z 3A continuous output current
z Fixed 370 kHz PWM operation
z Cycle-by-cycle current limit
z Thermal shutdown
z Small size 4x3 DFN-12 package
z Independent enable input for Buck and LDO
Applications
z Point of load DC/DC conversion
z Set top boxes
z LCD Monitors & TVs
z Cable modems
z Telecom/Networking/Datacom equipment
Typical Application
VIN
C5
0.1µF
C1
22µF
VOUT1
EN2
VIN
C6
1µF
EN1
BS
C7
4.7µF
VBIAS
R4
8.06k
R1
31.6k
C2, C3
22µF x 2
FB1
FB2
R3
10k
VOUT1
LX
LDRV
AOZ1214
VOUT2
L1
6.8µH
C4
1µF
COMP
GND
R2
10k
RC
30k
CC
2.2nF
Figure 1. Typical Application Circuit
Rev. 1.0 December 2010
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Page 1 of 16
AOZ1214
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1214DI
-40°C to +85°C
4x3 DFN-12L
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
Pin Configuration
LX
1
12
IN
IN
BST
2
11
BIAS
PGND
3
10
AGND
EN1
4
9
LDRV
AGND
EN2
5
8
FB2
FB1
6
7
COMP
DFN-12
(Top View)
Pin Description
Pin
Number
Pin
Name
1
LX
2
BST
3
PGND
4
EN1
Enable1 input for buck regulator. EN1 is active high. Connect EN1 to IN if not used. Do not leave
EN1 floating.
5
EN2
Enable2 input for linear regulator. EN2 is active high.
6
FB1
Buck Regulator Feedback Input. FB1 is regulated to 0.8V. Set the buck regulator output voltage
using a resistive voltage divider.
7
COMP
8
FB2
Pin Function
Buck Regulator Switching Node.
Buck Regulator Bootstrap Pin. BST is the high side driver supply. Connect a 0.1μF capacitor
between BST and LX to form a bootstrap circuit.
Power Ground.
Buck Regulator Compensation Pin. COMP is the output of the internal transconductance error
amplifier. Connect a RC network between COMP and GND to compensate the control loop.
Linear Regulator Feedback Input. FB2 is regulated to 0.8V. Set the linear regulator output voltage
using a resistive voltage divider.
9
LDRV
Linear Regulator Drive Output. LDRV controls the gate of an external pass transistor.
10
AGND
Analog Ground.
11
BIAS
12
IN
Rev. 1.0 December 2010
Internal Bias Regulator Output. Connect a 1μF between BIAS and GND.
Input Supply Pin. The input range is between 4.5V and 28V.
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Page 2 of 16
AOZ1214
Block Diagram
VIN
+5V
VBIAS
UVLO
& POR
EN2
5V LDO
Regulator
OTP
+
ISen
EN1
–
Reference
& Bias
Softstart 1
BST
ILimit
Q1
GM = 200µA/V
+
+
EAmp
0.8V
FB
–
PWM
Control
Logic
PWM
Comp
–
LX
+
COMP
0.3V
Q2
370kHz Oscillator
Short Detect
Comparator
+
–
Softstart 2
GM = 2A/V
+
EAmp2
COMP
–
UVP
< 0.6V
LDRV
AGND
PGND
Absolute Maximum Ratings
Recommended Operating Conditions
Exceeding the Absolute Maximum Ratings may damage the
device.
The device is not guaranteed to operate beyond the
Maximum Recommended Operating Conditions.
Parameter
Supply Voltage (VIN)
Rating
Parameter
30V
Supply Voltage (VIN)
LX to GND
-0.7V to VIN + 0.3V
Output Voltage Range
EN1, EN2 to GND
-0.3V to VIN + 0.3V
FB1, FB2 to GND
-0.3V to 6V
Ambient Temperature (TA)
COMP to GND
-0.3V to 6V
BST to GND
LDRV to GND
PG to GND
VLX + 6V
-0.3V to 6V
-0.3V to 30V
Junction Temperature (TJ)
+150°C
Storage Temperature (TS)
-65°C to +150°C
Rev. 1.0 December 2010
Package Thermal Resistance
4 x 3 DFN-12 (ΘJA)(1)
4 x 3 DFN-12 (ΘJC)
Rating
4.5V to 28V
0.8V to VIN
-40°C to +85°C
64.6°C/W
7.1°C/W
Note:
1. The value of ΘJA is measured with the device mounted on 1-in2
FR-4 board with 2oz. Copper, in a still air environment with
TA = 25°C. The value in any given application depends on the
user's specific board design.
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Page 3 of 16
AOZ1214
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, unless otherwise specified(2).
Symbol
VIN
VUVLO
IIN
IOFF
VFB1, 2
IFB1
Parameter
Conditions
Supply Voltage
Min.
Typ.
4.5
Input Under-Voltage Lockout
Threshold
VIN Rising
4.0
VIN Falling
3.7
Supply Current (Quiescent)
IOUT = 0, VFB = 1.2V,
VEN > 2V
Shutdown Supply Current
VEN1 = VEN2 = 0V
Feedback Voltage
Units
28
V
V
V
3
mA
3
20
μA
0.8
0.812
V
2
0.788
Max.
Load Regulation
0.5
%
Line Regulation
0.1
%
Feedback Voltage Input Current
200
nA
0.6
V
V
ENABLE
VEN1,2
EN1,2 Input Threshold
VHYS
EN1,2 Input Hysteresis
IEN1,2
EN1,2 Sink/Source Current
Off Threshold
On Threshold
2.5
mV
200
50
nA
425
kHz
MODULATOR
fO
Frequency
315
370
DMAX
Maximum Duty Cycle
85
%
DMIN
Minimum Duty Cycle
5
%
GVEA
Error Amplifier Voltage Gain
500
V/V
GEA
Error Amplifier Transconductance
200
μA / V
PROTECTION
ILIM
Current Limit
Over-Temperature Shutdown Limit
4
5
6
A
TJ Rising
145
TJ Falling
100
°C
°C
tSS1
Soft Start Interval 1
6
ms
tSS2
Soft Start Interval 2
6
ms
PWM OUTPUT STAGE
RDS(ON)
High-Side Switch On-Resistance
High-Side Switch Leakage
40
VEN = 0V, VLX = 0V
50
mΩ
10
μA
LINEAR CONTROLLER
LDRV Vout
Drive Output High Voltage
Vfb2 = 0.7V,
LDRV Iout = 20mA,
Iout1 = 0
4
V
LDRV Iout
Drive Output Current
Vfb2 = 0.7V, Iout1 = 0
10
mA
IFB2
Under Voltage Threshold
0.6
V
Line Regulation
0.5
%
Load Regulation
1
%
FB2 Leakage
150
nA
Note:
2. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Rev. 1.0 December 2010
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Page 4 of 16
AOZ1214
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Efficiency
Efficiency
(Vin = 24V, L = 6.8µH)
100%
95%
85%
3.3V OUTPUT
80%
75%
90%
Efficiency (%)
5.0V OUTPUT
Efficiency (%)
Efficiency (%)
90%
3.3V OUTPUT
85%
80%
75%
0
0.5
1.0
1.5
2.0
2.5
70%
3.0
0
0.5
80%
1.0
1.5
2.0
2.5
70%
3.0
380
360
340
320
25
Soft Start Time vs. Temp
5.5
5.0
4.5
-45 -30 -15
0
15
30
45
60
75
90
4
3
75
90
0
5
10
15
Vin (V)
20
25
UVLO vs. Temp
12V INPUT
4.1
Vin_rise
4.0
3.9
3.8
Vin_fall
3.7
5V INPUT
3.6
3.3V INPUT
0
0.5
1.0
1.5
2.0
2.5
3.5
-45 -30 -15
3.0
0
15
30
45
60
Icc vs. Temp
VFB1 vs. Vin
Current Limit vs. Vin
(Vout = 3.3V, L = 6.8µH, 25°C)
(Vout = 3.3V, L = 6.8µH, 25°C)
0.83
1.7
0.82
1.6
1.5
1.4
0.81
0.80
0.79
1.3
0.78
1.2
0.77
1.1
0.76
1.0
-45 -30 -15
0
15 30 45
Temperature (°C)
Rev. 1.0 December 2010
60
75
90
6.0
Current Limit (A)
1.8
0.75
90
6.5
0.85
0.84
75
Temperature (°C)
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
1.9
30
(Vin = 12V, Vout = 3.3V, L = 6.8µH, 25°C)
4.2
Load (A)
VFB1 (V)
Icc (mA)
60
(25°C)
Temperature (°C)
2.0
5
1
0
15 30 45
Temperature (°C)
UVLO (V)
6.0
15
14
13
12
11
10
9
8
7
6
5
4
3
3.0
6
Minimum Vin
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
Vin (V)
Soft Start Time (ms)
6.5
2.5
2
300
-45 -30 -15
30
2.0
7
360
20
1.5
(Vout = 3.3V, L = 6.8µH, 25°C)
8
Soft Start Time (ms)
Frequency (Hz)
370
15
Vin (V)
1.0
Soft Start Time
400
10
0.5
Load Current (A)
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
420
380
5
0
Frequency vs. Temperature
(Vout = 3.3V, L = 6.8µH, 25°C)
0
1.8V OUTPUT
85%
Load Current (A)
Frequency vs. Vin
Frequency (kHz)
90%
75%
Load Current (A)
390
3.3V OUTPUT
95%
5.0V OUTPUT
8.0V OUTPUT
350
(Vin = 5V, L = 6.8µH)
100%
8.0V OUTPUT
95%
70%
Efficiency
(Vin = 12V, L = 6.8µH)
100%
5.5
5.0
4.5
4.0
4
6
8
10 12 14 16 18 20 22 24 26 28
Vin (V)
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3.5
4
6
8
10 12 14 16 18 20 22 24 26 28
Vin (V)
Page 5 of 16
AOZ1214
Typical Performance Characteristics (Continued)
Circuit of Figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Current Limit vs. Temp
VFB2 vs. Temp
VFB1 vs. Temp
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
(Vin = 12V, Vout = 3.3V, L = 6.8µH)
5.0
4.5
4.0
-45 -30 -15
0
15 30 45
Temperature (°C)
60
75
90
0.85
0.85
0.84
0.84
0.83
0.83
0.82
0.82
0.81
VFB1 (V)
5.5
VFB2 (V)
Current Limit (A)
6.0
0.80
0.79
0.81
0.80
0.79
0.78
0.78
0.77
0.77
0.76
0.76
0.75
-45 -30 -15
0
15 30 45
Temperature (°C)
EN1,2 vs. Vin
EN1,2 On vs. Temp
(oVout = 3.3V, L = 6.8µH, no load, 25°C)
(Vout = 3.3V, L = 6.8µH)
3.0
2.5
60
75
90
0.75
-45 -30 -15
0
15 30 45
Temperature (°C)
60
75
90
75
90
EN1,2 Off vs. Temp
(Vout = 3.3V, L = 6.8µH)
3.0
2.4
2.3
En1,2 on
2.0
1.9
1.8
En1,2 off
1.7
24V INPUT
2.0
EN1,2 Off (V)
2.1
EN1,2 On (V)
EN1,2 (V)
2.5
2.5
2.2
12V INPUT
5V INPUT
1.5
2.0
24V INPUT
12V INPUT
1.5
1.6
5V INPUT
1.5
1.0
-45 -30 -15
1.4
4
6
8
10 12 14 16 18 20 22 24 26 28
75
90
0.5
0.4
12V INPUT
0.3
0.2
5V INPUT
0.1
45
60
75
90
30
45
60
LDRV Output Voltage vs. Source Current
(FB2 = 0.7V, 25°C)
35
30
25
20
15
10
4
3
2
1
5
0
-45 -30 -15
0
0
15
30
45
60
75
90
0
Temperature (°C)
Vo Ripple
200mV/Div
10
20
30
40
50
60
LDRV Source Current (mA)
1.5A–3A
Vo Ripple
200mV/Div
Io
1A/div
Io
1A/div
200µs/div
200µs/div
Rev. 1.0 December 2010
15
5
Temperature (°C)
0–1.5A
0
Temperature (°C)
LDRV Output Voltage (V)
LDRV Source Current (mA)
EN1,2 Hysteresis (V)
24V INPUT
0.6
30
60
40
0.7
15
45
(VFB2 = 0.7V, LDRV = 4V)
(Vout = 3.3V, L = 6.8µH)
0
30
LDRV Source Current vs. Temp
EN1,2 Hysteresis vs Temp
0
-45 -30 -15
15
Temperature (°C)
Vin (V)
0.8
0
1.0
-45 -30 -15
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Page 6 of 16
AOZ1214
Detailed Description
The AOZ1214 is a current-mode step down regulator
with integrated high side NMOS switch. It operates from
a 4.5V to 28V input voltage range and supplies up to 3A
of load current. The duty cycle can be adjusted from 5%
to 85% allowing a wide range of output voltage. Features
include independent enable control for buck and linear
regulator, Power-On Reset, input under voltage lockout,
fixed internal soft-start and thermal shut down. The linear
regulator controller is designed to drive an external NPN
power transistor or an N channel power MOSFET to
provide up to 1A of current to an auxiliary load.
The AOZ1214 is available in 4x3 DFN-12 package.
divider at the FB pin. The difference of the FB pin voltage
and reference is amplified by the internal transconductance error amplifier. The error voltage, which
shows on the COMP pin, is compared against the current
signal, which is sum of inductor current signal and ramp
compensation signal, at PWM comparator input. If the
current signal is less than the error voltage, the internal
high-side switch is on. The inductor current flows from
the input through the inductor to the output. When the
current signal exceeds the error voltage, the high-side
switch is off. The inductor current is freewheeling through
the Schottky diode to output.
Switching Frequency
Enable and Soft Start
The AOZ1214 has independent internal soft start feature
to limit buck and LDO in-rush current and ensure the
output voltage ramps up smoothly to regulation voltage.
When the input voltage rises to 4.0V and voltage on EN1,
EN2 pin is HIGH, the soft start processes of buck and
linear regulator independently begin. In each soft start
process, the buck or linear regulator output voltage is
ramped to regulation voltage in typically 6ms. The 6ms
soft start time is set internally.
Connect the EN1, EN2 pin to VIN if enable function is not
used. Pull EN1 and EN2 to ground will disable the buck
and linear regulator independently. Do not leave them
open. The voltage on EN1, EN2 pin must be above 2.5V
to active. When voltage on EN1, EN2 pin falls below
0.6V, the buck and linear regulator is disabled
independently. If an application circuit requires the
AOZ1214 buck or linear regulator to be disabled, an
open drain or open collector circuit should be used to
interface to EN1 or EN2 pin.
The AOZ1214 switching frequency is fixed and set by
an internal oscillator. The switching frequency is set
370 kHz.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin with a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below.
R 1⎞
⎛
V OUT1 = 0.8 × ⎜ 1 + -------⎟
R 2⎠
⎝
Some standard value of R1, R2 for most commonly used
output voltage values are listed in Table 1.
Table 1.
Vo (V)
R1 (kΩ)
R2 (kΩ)
Steady-State Operation
0.8
1.0
Open
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
1.2
4.99
10
1.5
10
11.5
1.8
12.7
10.2
The AOZ1214 integrates an internal N-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Since the N-MOSFET requires a
gate voltage higher than the input voltage, a boost
capacitor connected between LX pin and BST pin drives
the gate. The boost capacitor is charged while LX is low.
An internal 10 ohm switch from LX to PGND is used to
insure that LX is pulled to PGND even in the light load.
Output voltage is divided down by the external voltage
2.5
21.5
10
3.3
31.6
10
5.0
52.3
10
12.0
140
10
Rev. 1.0 December 2010
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
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Page 7 of 16
AOZ1214
Protection Features
The AOZ1214 has multiple protection features to prevent
system circuit damage under abnormal conditions.
Thermal Protection
Over Current Protection (OCP)
The sensed inductor current signal is also used for over
current protection. Since the AOZ1214 employs peak
current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited cycle
by cycle.
The cycle by cycle current limit threshold is internally set.
When the load current reaches the current limit
threshold, the cycle by cycle current limit circuit turns off
the high side switch immediately to terminate the current
duty cycle. The inductor current stop rising. The cycle by
cycle current limit protection directly limits inductor peak
current. The average inductor current is also limited due
to the limitation on peak inductor current. When cycle by
cycle current limit circuit is triggered, the output voltage
drops as the duty cycle decreasing.
The AOZ1214 has internal short circuit protection to
protect itself from catastrophic failure under output short
circuit conditions. The FB pin voltage is proportional to
the output voltage. Whenever FB pin voltage is below
0.3V, the short circuit protection circuit is triggered.
To prevent current limit running away, when comp pin
voltage is higher than 2.1V, the short circuit protection is
also triggered. Before short protection is triggered, there
is about 1 ms blank time to prevent false trigger caused
by glitch or noise. The converter will start up via a soft
start once the short circuit condition disappears.
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.0V, the converter
starts operation. When input voltage falls below 3.7V,
the converter will stop switching.
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side NMOS if the junction temperature exceeds
145ºC. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100ºC.
Application Information
The basic AOZ1214 application circuit is shown in
Figure 1. Component selection is explained below.
Buck Regulator Design
Input Capacitor
The input capacitor (C1 in Figure 1) must be connected to
the VIN pin and GND pin of the AOZ1214 to maintain
steady input voltage and filter out the pulsing input
current. The voltage rating of input capacitor must be
greater than maximum input voltage plus ripple voltage.
The input ripple voltage can be approximated by
equation below:
VO ⎞ VO
IO
⎛
ΔV IN = ----------------- × ⎜ 1 – ---------⎟ × --------V IN⎠ V IN
f × C IN ⎝
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
VO ⎛
VO ⎞
I CIN_RMS = I O × --------- ⎜ 1 – ---------⎟
V IN ⎝
V IN⎠
if let m equal the conversion ratio:
Linear Regulator
The AOZ1214 contains an error amplifier which can be
configured as a linear regulator controller. By adding an
external follower (NPN or NMOS) and divider resistors as
shown in Figure 1, the FB2 and LDRV pins can be
configured as a controller for a Low Dropout Regulator.
The LDRV pin source capability come from LDO inside
which is capable more than 10mA of base current to the
external NPN transistor.
Rev. 1.0 December 2010
The FB2 voltage is monitored by an Under Voltage
Protection circuit, which shutdown LDRV output when
FB2 voltage is under 0.6V.
VO
-------- = m
V IN
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2 below. It can be seen that when VO is
half of VIN, CIN is under the worst current stress. The
worst current stress on CIN is 0.5 x IO.
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Page 8 of 16
AOZ1214
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked for
thermal and efficiency requirements.
0.5
0.4
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
ICIN_RMS(m) 0.3
IO
0.2
0.1
0
Output Capacitor
0
0.5
m
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
1
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high ripple current rating. Depending on the
application circuits, other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used. When
selecting ceramic capacitors, X5R or X7R type dielectric
ceramic capacitors are preferred for their better
temperature and voltage characteristics. Note that the
ripple current rating from capacitor manufactures is
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
ΔV O = ΔI L × ⎛ ESR CO + -------------------------⎞
⎝
8×f×C ⎠
O
Inductor
where;
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is,
CO is output capacitor value and
VO ⎞
VO ⎛
ΔI L = ----------- × ⎜ 1 – ---------⎟
V IN⎠
f×L ⎝
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
1
ΔV O = ΔI L × ⎛ -------------------------⎞
⎝8 × f × C ⎠
The peak inductor current is:
ΔI L
I Lpeak = I O + -------2
O
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
Rev. 1.0 December 2010
ESRCO is the Equivalent Series Resistor of output capacitor.
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
ΔV O = ΔI L × ESR CO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum capacitor or
aluminum electrolytic capacitor may also be used as
output capacitors.
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Page 9 of 16
AOZ1214
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current.
It can be calculated by:
ΔI L
I CO_RMS = ---------12
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
network can be used for AOZ1214. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
In the AOZ1214, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
Schottky Diode Selection
The external freewheeling diode supplies the current to
the inductor when the high side NMOS switch is off.
To reduce the losses due to the forward voltage drop and
recovery of diode, Schottky diode is recommended to
use. The maximum reverse voltage rating of the chosen
Schottky diode should be greater than the maximum
input voltage and size for average forward current in
normal condition. Average forward current can be
calculated from:
IO
I D_AVE = --------- ( V IN – V OUT )
V IN
G EA
f P2 = ------------------------------------------2π × C C × G VEA
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage gain, which is 500 V/V, and
CC is the compensation capacitor.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
1
f Z2 = ----------------------------------2π × C C × R C
Loop Compensation
The AOZ1214 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
1
f p1 = ----------------------------------2π × C O × R L
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover frequency is also called the converter
bandwidth. Generally a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high due to system stability concern.
When designing the compensation loop, converter
stability under all line and load condition must be
considered.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. It is recommended
to choose a crossover frequency less than 30 kHz.
f C = 30kHz
1
f Z1 = -----------------------------------------------2π × C O × ESR CO
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
Rev. 1.0 December 2010
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Page 10 of 16
AOZ1214
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
VO
2π × C O
R C = f C × ---------- × -----------------------------V
G ×G
FB
EA
CS
where;o
Linear Regulator Design
Adjustable Output Voltage
The output voltage can be set by feeding back the output
to FB2 pin with a resistor divider network. In the
application circuit shown in Figure 1. The linear regulator
output voltage can be obtained using the following
equation:
R3
V OUT2 = 0.8 × ⎛ 1 + --------⎞
⎝
R4⎠
fC is desired crossover frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200x10-6
A/V, and
GCS is the current sense circuit transconductance, which is
5.64 A/V.
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. CC can is selected by:
1.5
C C = ----------------------------------2π × R C × f p1
CO × RL
C C = --------------------RC
1. The transistor and MOSFET should be able to supply
maximum operating current for the linear regulator
supply.
L = 1.5μH–3.3μH
L = 4.7μH–10μH
L = 6.8μH–15μH
4. Comparing with transistor, MOSFET has lower
dropout voltage which is RDS(ON) times the output
current. But the minimum input voltage will increase
to VO plus VGS while transistor is VO plus VBE.
RC = 10KΩ
RC = 30KΩ
RC = 30KΩ
CC = 6.8nF
CC = 2.2nF
CC = 3.3nF
Linear Regulator Output Capacitor
L = 1.5μH
L = 4.7μH–10μH
L = 6.8uH–15μH
RC = 10KΩ
RC = 30KΩ
RC = 30KΩ
CC = 6.8nF
CC = 2.2nF
CC = 3.3nF
VO
20V
Both Transistor and MOSFET can be used as an external
follower. Some cautions must be noticed:
3. The total power dissipation should not be higher than
the rated value.
Table 2. Recommended Parameters
12V
External NPN Pass Transistor or MOSFET
2. DC current gain hFE must be large enough so that
the pass transistor and supply the maximum load
current with 30 mA with base current. However, too
big hFE may cause the LDO sensitive to current
noise, and a compromised DC current gain transistor
should be selected.
Equation above can also be simplified to:
Vin
R4 should be less than 10 kohm to avoid bias current
errors.
1.2V
3.3V
5V
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
The linear regulator requires using an output capacitor as
part of the frequency compensation network, which
affects the stability and high frequency response. The
regulator has a finite band width. For high frequency
transient loads, recovery from transient is determined by
both output capacitor and the bandwidth of the regulator.
A minimum output capacitor of 4.7 μF is recommended to
prevent oscillations and provide good transient response.
The ESR value should be maintained in the range that
determines the loop stability. When small signal ringing
Rev. 1.0 December 2010
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Page 11 of 16
AOZ1214
occurs with ceramics due to insufficient ESR in low
output voltage condition, adding ESR or increasing the
capacitor value improves the stability and reduces the
ringing. But too high ESR is also not suggested, which
will cause the zero too big and the phase margin is not
satisfied. High ESR also brings in high voltage ripple. The
lower the output voltage is, the higher value ESR is
needed. Basically, ESR between 0.02 ohm and 3 ohm
can make sure the circuit stable.
Solid tantalum electrolytic, aluminum electrolytic, and
multilayer ceramic capacitors are all suitable, only if their
capacitance and ESR meet the requirements.
Output Voltage Ripple
The LDO is designed to provide low output voltage noise
while operating at any load. Because of the existence of
stray inductance and capacitance, sometimes there
could be a big ripple voltage in the output which is
unexpected. The following tips could decrease the ripple
voltage to a lower value:
1. Improve the PCB layout.
Signal grounds should connect to AGND to insure
the noise is small.
Low side divider resistor connects to AGND directly.
Keep sensitive signal trace such as FB2 pin, LDRV
pin as short as possible, and far away from noise
trace;
2. Adding a bypass capacitor from FB2 pin to AGND,
which will lower the bandwidth of the loop. The
impedance of the FB2 pin capacitor at the ripple
frequency should be less than the value of R3.
3. Adding a resistor RG between LDRV and base of
transistor (gate of MOSFET), which can structure a
RC filter with the capacitor of Base-Emitter to reduce
the noise. As the increasing of RG value, the noise
getting smaller. Considering the power dispassion of
the RG, its value is often between 10 ohm and
100 ohm.
4. Increasing the capacitance of output capacitor or add
the ESR of the output capacitor.
5. Change the pass transistor to a lower hFE type
(MOSFET to a lower gFS type), thus the loop gain
can be smaller as a source follower. But the hFE
and gFS should be large enough to meet the output
current requirement.
Rev. 1.0 December 2010
Thermal Management and Layout
Consideration
In the AOZ1214 buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the
LX pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the GND pin of the
AOZ1214, to the LX pins of the AZO1214. Current flows
in the second loop when the low side diode is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is recommended to connect input capacitor, output
capacitor, and GND pin of the AOZ1214.
In the AOZ1214 buck regulator circuit, the three major
power dissipating components are the AOZ1214,
external diode and output inductor. The total power
dissipation of converter circuit can be measured by input
power minus output power.
P total_loss = V IN × I IN – V O × I O
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor.
P inductor_loss = IO2 × R inductor × 1.1
The power dissipation of diode is:
VO ⎞
⎛
P diode_loss = I O × V F × ⎜ 1 – ---------⎟
V IN⎠
⎝
The actual AOZ1214 junction temperature can be
calculated with power dissipation in the AOZ1214 and
thermal impedance from junction to ambient.
T junction = ( P total_loss – P inductor_loss ) × Θ JA
+ + T ambient
The maximum junction temperature of AOZ1214 is
145ºC, which limits the maximum load current capability.
The thermal performance of the AOZ1214 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
operate under the recommended environmental
conditions.
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Page 12 of 16
AOZ1214
Several layout tips are listed below for the best electric
and thermal performance. Figure 3 is the layout example.
1. Do not use thermal relief connection to the VIN and
the GND pin. Pour a maximized copper area to the
GND pin and the VIN pin to help thermal dissipation.
2. Input capacitor should be connected to the VIN pin
and the GND pin as close as possible.
3. Make the current trace from LX pins to L to Co to the
GND as short as possible.
4. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
5. Keep sensitive signal trace such as trace connected
with FB pin and COMP pin far away form the LX pins.
Top Side
Bottom Side
Figure 3. Layout Example for the AOZ1214
Rev. 1.0 December 2010
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Page 13 of 16
AOZ1214
Package Dimensions, DFN 4x3, 12L
A
Pin #1 IDA
Chamfer 0.15
D/2
e
L1
1
L
Index Area
(D/2 x E/2)
L3
E/2
E1/2
E
E1
L3
L2
D1
TOP VIEW
D2
BOTTOM VIEW
A3
A
Seating
Plane
A1
b
SIDE VIEW
Dimensions in millimeters
RECOMMENDED LAND PATTERN
0.50
0.25
0.23
0.50
0.30
1.35
1.60
0.80
0.715
2.70
0.30
0.20 x 45
1.035
E
E1
e
L
L1
L2
L3
0.315
2.065
Symbols
A
A1
A3
b
D
D1
D2
Unit: mm
Min.
0.80
0.00
Nom.
0.90
0.02
0.20 REF.
0.20
0.23
4.00 BSC
0.83
0.985
1.86
2.015
Max.
1.00
0.05
0.35
1.09
2.12
Dimensions in inches
Symbols
A
A1
A3
b
D
D1
D2
Min. Nom. Max.
0.031 0.035 0.039
0.000 0.001 0.002
0.008 REF.
0.008 0.009 0.014
0.157 BSC
0.033 0.039 0.043
0.073 0.079 0.083
3.00 BSC
1.60
1.70
0.50 BSC
0.30
0.40
0.50
0.61
0.715
0.82
E
E1
e
L
L1
0.21
L2
L3
0.008 0.012 0.017
0.012 REF.
1.45
0.315
0.42
0.30 REF.
0.118 BSC
0.063 0.067
0.020 BSC
0.012 0.016 0.020
0.024 0.028 0.032
0.057
aaa
bbb
ccc
0.15
0.10
0.10
aaa
bbb
ccc
0.006
0.004
0.004
ddd
0.08
ddd
0.003
Notes:
1. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
2. The location of the terminal #1 identifier and terminal numbering conforms to JEDEC publication 95 SPP-002.
3. Dimension b applied to metallized terminal and is measured between 0.20mm and 0.35mm from the terminal tip. If the terminal
has the optional radius on the other end of the terminal, dimension b should not be measured in that radius area.
4. Coplanarity ddd applies to the terminals and all other bottom surface metallization.
Rev. 1.0 December 2010
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Page 14 of 16
AOZ1214
Tape and Reel Dimensions, DFN 4x3
Carrier Tape
P1
P2
D1
T
E1
E2
E
C
L
B0
K0
D0
P0
A0
Feeding Direction
UNIT: mm
Package
DFN 4 x 3
(12 mm)
A0
3.40
±0.10
B0
4.40
±0.10
K0
1.10
±0.10
D0
1.50
Min.
D1
1.50
+0.10/-0.0
E
12.0
±0.3
Reel
E1
1.75
±0.10
E2
5.50
±0.05
P0
8.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.10
T
0.30
±0.05
W1
S
G
N
M
K
V
R
H
W
UNIT: mm
Tape Size Reel Size
12mm
ø330
M
N
ø330.0
±2.0
ø79.0
±1.0
W
W1
12.4
17.0
+2.0/-0 +2.6/-0
H
K
S
G
R
V
ø13.0
±0.5
10.5
±0.2
2.0
±0.5
—
—
—
Leader / Trailer & Orientation
Trailer Tape
300mm Min. or
75 Empty Pockets
Rev. 1.0 December 2010
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm Min. or
125 Empty Pockets
Page 15 of 16
AOZ1214
Part Marking
AOZ1214DI
(4 x 3 DFN-12)
Z1214DI
Part Number Code
FAYWLT
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.0 December 2010
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Page 16 of 16