AVAGO ACPL-38JT-000E

ACPL-38JT
Automotive Gate Drive Optocoupler with R2Coupler™ Isolation,
2.5 Amp Output Current, Integrated Desaturation (VCE) Detection
and Fault Status Feedback
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
Avago’s automotive 2.5 Amp Gate Drive Optocoupler with
Integrated Desaturation (VCE) Detection and Fault Status
Feedback makes automotive IGBT VCE fault protection
compact, affordable, and easy-to-implement while satisfying automotive AEC-Q100 Grade 1 semiconductor requirement.
 2.5 A maximum peak output current
R2Coupler
Avago
isolation products provide the reinforced insulation and reliability needed for critical in automotive and high temperature industrial applications
Functional Diagram
VLED1+ VLED1–
7
8
D
R
I
V
E
R
LED1
VIN+
VIN–
VCC1
RESET
FAULT
GND1
13
2
3
UVLO
10
DESAT
SHIELD
4
11
14
16
6 FAULT
1
15
SHIELD
Figure 1. ACPL-38JT Functional Diagram
VOUT
DESAT
9, 12
VEE
LED2
5
VCC2
VC
VE
VLED2+
 Drive IGBTs up to IC = 150 A, VCE = 1200 V
 Optically isolated, FAULT status feedback
 SO-16 package
 CMOS/TTL compatible
 500 ns max. switching speeds
 “Soft” IGBT turn-off
 Integrated fail-safe IGBT protection
– Desat (VCE) detection
– Under Voltage Lock-Out protection (UVLO) with
hysteresis
 User configurable: inverting, noninverting, auto-reset,
auto-shutdown
 Wide operating VCC range: 15 to 30 Volts
 -40°C to +125°C operating temperature range
 15 kV/s min. Common Mode Rejection (CMR) at VCM =
1500 V
 Qualified to AEC-Q100 Grade 1 Test Guidelines
 Regulatory approvals:
– UL1577, CSA
– IEC/EN/DIN EN 60747-5-5
Applications
 Automotive Isolated IGBT/MOSFET Inverter gate drive
 Automotive DC-DC Converter
 AC and brushless dc motor drives
 Industrial inverters for power supplies and motor
controls
 Un-interruptible Power Supplies
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-38JT is UL Recognized with 5000 Vrms for 1 minute per UL1577.
Part Number
RoHS Compliant
-000E
ACPL-38JT
-500E
Package
Surface Mount
Tape & Reel
Quantity
X
SO-16
X
45 per tube
X
850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-38JT-500E to order product of SO-16 Surface Mount RoHS compliant package in Tape and Reel packaging.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Typical Fault Protected IGBT Gate Drive Circuit
The ACPL-38JT is an easy-to-use, intelligent gate driver which makes IGBT VCE fault protection compact, affordable, and
easy-to-implement. Features such as user configurable inputs, integrated VCE detection, under voltage lockout (UVLO),
“soft” IGBT turn-off and isolated fault feedback provide maximum design flexibility and circuit protection.
Boundary
Isolation
Battery
Battery
Boundary
Isolation
M
DC-DC
Converter
Boundary
Isolation
Boundary
Isolation
FAULT
Typical Application Block Diagram of a motor control system.
2
Boundary
Isolation
Micro-Controller
Boundary
Isolation
Boundary
Isolation
0.1μF
1
GND1
2
VE
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
0.1μF 0.1μF
*
CBLANK
100 Ω
DDESAT
+ VF 
_+
μCC
RF
0.1μF
*
RG
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
+

Q1
RPULL-DOWN
+
VCE

+ *

Q2
Typical de-saturation protected gate drive circuit, non-inverting.
Description of Operation during Fault Condition
Output Control
1. DESAT terminal monitors the IGBT VCE voltage through
DDESAT.
The outputs (VOUT and FAULT) of the ACPL-38JT are controlled by the combination of VIN, UVLO and a detected
IGBT Desat condition. As indicated in the below table, the
ACPL-38JT can be configured as inverting or non-inverting using the VIN+ or VIN- inputs respectively. When an
inverting configuration is desired, VIN+ must be held high
and VIN- toggled. When a non-inverting configuration
is desired, VIN- must be held low and VIN+ toggled. Once
UVLO is not active (VCC2 - VE > VUVLO), VOUT is allowed
to go high, and the DESAT (pin 14) detection feature of
the ACPL-38JT will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once
VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO< 12.4 V. Thus, the DESAT detection and UVLO features of
the ACPL-38JT work in conjunction to ensure constant
IGBT protection.
2. When the voltage on the DESAT terminal exceeds 7
volts, the IGBT gate voltage (VOUT ) is slowly lowered.
3. FAULT output goes low, notifying the microcontroller
of the fault condition.
4. Microcontroller takes appropriate action.
VIN+
VIN-
UVLO
(VCC2 - VE)
Desat
Condition
Detected
on Pin 14
X
X
Low
X
X
X
Active
X
X
X
Yes
X
X
Low
X
Low
Low
Low
X
High
X
X
X
Low
High
Low
Not Active
No
High
High
3
Pin 6
(FAULT)
Output
VOUT
Product Overview Description
The ACPL-38JT (shown in Figure 1) is a highly integrated
power control device that incorporates all the necessary
components for a complete, isolated IGBT gate drive
circuit with fault protection and feedback into one SO-16
package. TTL input logic levels allow direct interface with
a microcontroller, and an optically isolated power output
stage drives IGBTs with power ratings of up to 150 A and
1200 V. A high speed internal optical link minimizes the
propagation delays between the microcontroller and
the IGBT while allowing the two systems to operate at
very large common mode voltage differences that are
common in industrial motor drives and other power
switching applications. An output IC provides local protection for the IGBT to prevent damage during overcurrents, and a second optical link provides a fully isolated
fault status feedback signal for the microcontroller. A built
in “watchdog” circuit monitors the power stage supply
voltage to prevent IGBT caused by insufficient gate drive
voltages. This integrated IGBT gate driver is designed to
increase the performance and reliability of a motor drive
without the cost, size, and complexity of a discrete design.
Two light emitting diodes and two integrated circuits
housed in the same SO-16 package provide the input
control circuitry, the output power stage, and two
optical channels. The input Buffer IC is designed on a
bipolar process, while the output Detector IC is designed
4
manufactured on a high voltage BiCMOS/Power DMOS
process. The forward optical signal path, as indicated by
LED1, transmits the gate control signal. The return optical
signal path, as indicated by LED2, transmits the fault
status feedback signal. Both optical channels are completely controlled by the input and output ICs respectively, making the internal isolation boundary transparent to
the microcontroller.
Under normal operation, the input gate control signal
directly controls the IGBT gate through the isolated output
detector IC. LED2 remains off and a fault latch in the input
buffer IC is disabled. When an IGBT fault is detected, the
output detector IC immediately begins a “soft” shutdown
sequence, reducing the IGBT current to zero in a controlled
manner to avoid potential IGBT damage from inductive
over-voltages. Simultaneously, this fault status is transmitted back to the input buffer IC via LED2, where the fault
latch disables the gate control input and the active low
fault output alerts the microcontroller.
During power-up, the Under Voltage Lockout (UVLO)
feature prevents the application of insufficient gate
voltage to the IGBT, by forcing the ACPL-38JT’s output
low. Once the output is in the high state, the DESAT (VCE)
detection feature of the ACPL-38JT provides IGBT protection. Thus, UVLO and DESAT work in conjunction to
provide constant IGBT protection.
Package Pin Out
1
GND1
VE
16
2
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED1+
VOUT
10
8
VLED1
VEE
9
Pin Descriptions
Symbol
Description
Symbol
Description
VIN+
Noninverting gate drive voltage output (VOUT )
control input.
VE
Common (IGBT emitter) output supply voltage.
VIN-
Inverting gate drive voltage output (VOUT )
control input.
VLED2+
LED 2 anode. This pin must be left unconnected
for guaranteed data sheet performance.
(For optical coupling testing only.)
VCC1
Positive input supply voltage. (4.5 V to 5.5 V)
DESAT
Desaturation voltage input. When the voltage
on DESAT exceeds an internal reference voltage
of 7 V while the IGBT is on, FAULT output is changed
from a high impedance state to a logic low state
within 5 s. See Note 25.
GND1
Input Ground.
VCC2
Positive output supply voltage.
RESET
FAULT reset input. A logic low input for at least
0.1 s, asynchronously resets FAULT output high
and enables VIN. Synchronous control of RESET
relative to VIN is required. RESET is not affected
by UVLO. Asserting RESET while VOUT is high does
not affect VOUT.
VC
Collector of output pull-up triple-darlington
transistor. It is connected to VCC2 directly or through
a resistor to limit output turn-on current.
FAULT
Fault output. FAULT changes from a high impedance
state to a logic low output within 5 s of the voltage
on the DESAT pin exceeding an internal reference
voltage of 7 V. FAULT output remains low until RESET
is brought low. FAULT output is an open collector
which allows the FAULT outputs from all HCPL-316Js
in a circuit to be connected together in a “wired OR”
forming a single fault bus for interfacing directly to
the micro-controller.
VOUT
Gate drive voltage output.
VLED1+
LED 1 anode. This pin must be left unconnected
for guaranteed data sheet performance.
(For optical coupling testing only.)
VEE
Output supply voltage.
VLED1-
LED 1 cathode. This pin must be connected to
ground.
5
Package Outline Drawings
16-Lead Surface Mount
0.018
(0.457)
16 15 14 13 12 11 10 9
0.050
(1.270)
LAND PATTERN RECOMMENDATION
TYPE NUMBER
DATE CODE
A 38JT
YYWW
EE
0.458 (11.63)
0.295 ± 0.010
(7.493 ± 0.254)
0.085 (2.16)
1 2 3 4 5 6 7 8
0.406 ± 0.10
(10.312 ± 0.254)
EXTENDED
DATECODE FOR
LOT TRACKING
0.025 (0.64)
0.345 ± 0.010
(8.763 ± 0.254)
9°
0.018
(0.457)
0.138 ± 0.005
(3.505 ± 0.127)
0–8°
0.025 MIN.
0.408 ± 0.010
(10.363 ± 0.254)
ALL LEADS
TO BE
COPLANAR
± 0.002
0.008 ± 0.003
(0.203 ± 0.076)
STANDOFF
Package Characteristics
All specifications and figures are at the nominal (typical) operating conditions of VCC1 = 5 V, VCC2 - VEE = 30 V, VE - VEE = 0 V,
and TA = +25°C.
Parameter
Symbol
Min.
Input-Output Momentary Withstand
Voltage
VISO
5000
Resistance (Input-Output)
RI-O
Capacitance (Input-Output)
Typ.
Max.
Units
Test Conditions
Note
VRMS
RH < 50%, t = 1 min.
TA = 25°C
1, 2, 3
1014

VI-O = 500 Vdc
3
CI-O
1.3
pF
f = 1 MHz
Output IC-to-Pins 9 & 12
Thermal Resistance
O9-12
30
°C/W
TA = 100°C
Input IC-to-Pin 1 Thermal Resistance
I1
60
°C/W
TA = 100°C
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
The ACPL-38JT is approved by the following organizations:
UL
IEC/EN/DIN EN 60747-5-5
Approved under UL 1577, component recognition
program up to VISO = 5000 VRMS expected prior to product
release.
Approved under:
IEC 60747-5-5
EN 60747-5-5
DIN EN 60747-5-5
CSA
Approved under CSA Component Acceptance Notice #5,
File CA 88324.
6
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Description
Symbol
Characteristic
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
for rated mains voltage ≤ 600 Vrms
I - IV
I - III
I - II
Climatic Classification
55/125/21
Pollution Degree (DIN VDE 0110/1.89)
2
Unit
Maximum Working Insulation Voltage
VIORM
1230
VPEAK
Input to Output Test Voltage, Method b[2] VIORM x 1.875 = VPR,
100% Production Test with tm = 10 sec, Partial discharge < 5 pC
VPR
2306
VPEAK
Input to Output Test Voltage, Method a[2] VIORM x 1.6 = VPR,
Type and Sample Test, tm = 60 sec, Partial discharge < 5 pC
VPR
1968
VPEAK
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
VIOTM
8000
VPEAK
Safety-limiting values – maximum values allowed in the event of a failure
Case Temperature
Input Current[3]
Output Power[3]
TS
IS, INPUT
PS, OUTPUT
175
400
1200
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V
RS
>109

Notes:
1. Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface Mount Classification is Class A in accordance with CECCOO802.
2. Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
3. Refer to the following figure for dependence of PS and IS on ambient temperature.
1400
PS, OUTPUT
PS, INPUT
PS – POWER – mW
1200
1000
800
600
400
200
0
0
25
50
75
100 125 150
TS – CASE TEMPERATURE – °C
175
Figure 2. Dependence of safety limiting values on temperature.
7
200
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Minimum External Air Gap (Clearance)
L(101)
8.3
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking (Creepage)
L(102)
8.3
mm
Measured from input terminals to output terminals,
shortest distance path along body.
0.5
mm
Through insulation distance conductor to conductor,
usually the straight line distance thickness between
the emitter and detector.
>175
Volts
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
IIIa
Material Group (DIN VDE 0110)
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
150
°C
Operating Temperature
TA
-40
125
°C
Output IC Junction Temperature
TJ
150
°C
4
Peak Output Current
|IO(peak)|
2.5
A
5
Fault Output Current
IFAULT
8
mA
Positive Input Supply Voltage
VCC1
-0.5
5.5
Volts
Input Pin Voltages
VIN+, VIN- and
VRESET
-0.5
VCC1
Volts
Total Output Supply Voltage
(VCC2 - VEE)
-0.5
35
Volts
Negative Output Supply Voltage
(VE - VEE)
-0.5
15
Volts
Positive Output Supply Voltage
(VCC2 - VE)
-0.5
35 - (VE - VEE)
Volts
Gate Drive Output Voltage
Vo(peak)
-0.5
VCC2
Volts
Collector Voltage
VC
VEE + 5
VCC2
Volts
DESAT Voltage
VDESAT
VE
VE + 10
Volts
Output IC Power Dissipation
PO
600
mW
Input IC Power Dissipation
PI
150
mW
Solder Reflow Temperature Profile
See Package Outline Drawings section
Note
6
4
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Notes
Input Supply Voltage
VCC1
4.5
5.5
Volts
28
Total Output Supply Voltage
(VCC2 - VEE)
15
30
Volts
9
Negative Output Supply Voltage
(VE - VEE)
0
15
Volts
6
Positive Output Supply Voltage
(VCC2 - VE)
15
30 – (VE - VEE)
Volts
Collector Voltage
VC
VEE + 6
VCC2
Volts
Operating Temperature
TA
-40
125
°C
8
Electrical Specifications
Recommended operating conditions unless otherwise specified: TA = -40°C to +125°C, all typical values at TA = 25°C,
VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating
Conditions.
Parameter
Symbol
Min.
Typ.*
Max.
Units
0.8
V
Test Conditions
Fig.
Note
Logic Low Input Voltages
VIN+L, VIN-L,
VRESETL
Logic High Input Voltages
VIN+H, VIN-H,
VRESETH
2.0
Logic Low Input Currents
IIN+L, IIN-L,
IRESETL
-0.5
-0.4
mA
VIN = 0.4 V
FAULT Logic Low Output
Current
IFAULTL
5.0
12
mA
VFAULT = 0.4 V
29
FAULT Logic High Output
Current
IFAULTH
-40
A
VFAULT = VCC1
30
High Level Output Current
IOH
-0.5
-2.0
-1.5
A
VOUT = VCC2 - 4 V
VOUT = VCC2 - 15 V
3, 8,
31
7
5
Low Level Output Current
IOL
0.5
2.0
2.3
A
VOUT = VEE + 2.5 V
VOUT = VEE + 15 V
4, 9,
32
7
5
Low Level Output Current
IOLF
90
160
230
mA
VOUT - VEE = 14 V
5, 33
8
High Level Output Voltage
VOH
VC - 3.5
VC - 2.5
VC - 1.5
V
IOUT = -100 mA
6, 8,
9, 10, 11
VC -2.9
VC - 2.0
VC - 1.2
V
IOUT = -650 A
34
VC
V
IOUT = 0
V
Low Level Output Voltage
VOL
0.17
0.5
V
IOUT = 100 mA
7, 9, 35
26
High Level Input Supply
Current
ICC1H
17
22
mA
VIN+ = VCC1 = 5.5 V,
VIN- = 0 V
10, 36
Low Level Input Supply
Current
ICCIL
6
11
mA
VIN+ = VIN- = 0 V,
VCC1 = 5.5 V,
10, 37
Output Supply Current
ICC2
2.5
5
mA
VOUT open
11, 12,
38, 39
11
Low Level Collector Current
ICL
0.3
1.0
mA
IOUT = 0
15, 58
27
High Level Collector Current
ICH
0.3
1.3
mA
IOUT = 0
15, 57
27
1.8
3.0
mA
IOUT = -650 A
15, 56
27
VE Low Level Supply Current
IEL
-0.7
-0.4
0
mA
14, 60
VE High Level Supply Current
IEH
-0.5
-0.14
0
mA
14, 59
25
Blanking Capacitor Charging
Current
ICHG
-0.13
-0.18
-0.25
-0.25
-0.33
-0.33
mA
mA
VDESAT = 0 - 6 V
VDESAT = 0 - 6 V,
TA = 25°C - 125°C
13, 40
11, 12
Blanking Capacitor Discharge
Current
IDSCHG
10
50
mA
VDESAT = 7 V
41
UVLO Threshold
VUVLO+
VUVLO-
11.6
12.3
11.1
V
V
VOUT > 5 V
VOUT < 5 V
42
UVLO Hysteresis
(VUVLO+
VUVLO-)
0.4
1.2
DESAT Threshold
VDESAT
6.5
7.0
9
13.5
12.4
V
7.5
V
9, 11, 13
9, 11, 14
42
VCC2 - VE > VUVLO-
16, 43
11
Switching Specifications
Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/
Maximum specifications are at Recommended Operating Conditions.
Parameter
Symbol
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
VIN to High Level Output
Propagation Delay Time
tPLH
0.10
0.30
0.50
s
tPHL
0.10
0.32
0.5
s
17,18,19,
20,21,22,
44, 53, 54
15
VIN to Low Level Output
Propagation Delay Time
Rg = 10 
Cg = 10 nF
f = 10 kHz
Duty Cycle = 50%
Pulse Width Distortion
PWD
-0.30
0.02
0.30
s
16,17
0.35
s
17,18
Propagation Delay Difference (tPHL-tPLH) PDD -0.35
Between Any 2 Parts
10% to 90% Rise Time
tr
0.1
s
44
90% to 10% Fall Time
tf
0.1
s
44
DESAT Sense to 90% VOUT
Delay
tDESAT(90%)
0.3
0.5
s
Rg = 10 
Cg = 10 nF
23, 55
DESAT Sense to 10% VOUT
Delay
tDESAT(10%)
2.0
3.0
s
VCC2 - VEE = 30 V
24, 26, 27
45, 55
DESAT Sense to Low Level
FAULT Signal Delay
tDESAT(FAULT)
1.8
5
s
25, 46, 55
20
DESAT Sense to DESAT Low
Propagation Delay
tDESAT(LOW)
0.25
s
55
21
RESET to High Level FAULT
Signal Delay
tRESET(FAULT)
3
s
28, 47, 55
22
RESET Signal Pulse Width
PWRESET
0.1
UVLO to VOUT High Delay
tUVLO ON
4.0
s
48
13
UVLO to VOUT Low Delay
tUVLO OFF
6.0
s
Output High Level Common
Mode Transient Immunity
|CMH|
15
30
kV/s TA = 25°C,
VCM = 1500 V,
VCC2 = 30 V
Output Low Level Common
Mode Transient Immunity
|CML|
15
30
kV/s TA = 25°C,
VCM = 1500 V,
VCC2 = 30 V
10
7
20
19
s
VCC2 = 1.0 ms ramp
14
49, 50, 51,
52
23
24
Notes:
1.
In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 Vrms for 1 second.
2.
The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 Insulation
Characteristics Table.
3.
Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 12 shorted together.
4.
In order to achieve the absolute maximum power dissipation specified, pins 1, 9, and 12 require ground plane connections and may require
airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature
and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation
achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section
in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power
dissipation does not require de-rating.
5.
Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO
peak minimum = 2.0 A. See Applications section for additional details on IOH peak. De-rate linearly from 3.0 A at +25°C to 2.5 A at +125°C. This
compensates for increased IOPEAK due to changes in VOL over temperature.
6.
This supply is optional. Required only when negative gate drive is implemented.
7.
Maximum pulse width = 50 s, maximum duty cycle = 0.5%.
8.
See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
9.
15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+
threshold of 13.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will
approach VCC as IOH approaches zero units.
10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
11. Once VOUT of the ACPL-38JT is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the ACPL-38JT will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- < 12.4 V. Thus, the
DESAT detection and UVLO features of the ACPL-38JT work in conjunction to ensure constant IGBT protection.
12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details.
13. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE.
14. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE.
15. This load condition approximates the gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit.
17. As measured from VIN+, VIN- to VOUT.
18. The difference between tPHL and tPLH between any two ACPL-38JT parts under the same test conditions.
19. Supply Voltage Dependent.
20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
21. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low.
22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 μs is the guaranteed
minimum FAULT signal pulse width when the ACPL-38JT is configured for Auto-Reset. See the Auto-Reset section in the applications notes at the
end of this data sheet for further details.
23. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 3K pull-up resistor is needed in fault detection mode.
24. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
25. Does not include LED2 current during fault or blanking capacitor discharge current.
26. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 A
while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down
resistor is not used.
27. The recommended output pull-down resistor between VOUT and VEE does not contribute any output current when VOUT = VEE.
28. In most applications VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the
IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that Vin+ remains low until VCC1 reaches the proper operating
voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down.
11
7
1.8
IOL - OUTPUT LOW CURRENT
IOH - OUTPUT HIGH CURRENT - A
2.0
1.6
1.4
1.2
1.0
-40
-20
0
20
40
60
80
TA - TEMPERATURE - °C
100
120
3
2
175
150
125
100
75
-40°C
25°C
100°C
50
25
0
20
10
15
VOUT – OUTPUT VOLTAGE – V
5
25
30
Figure 5. IOLF vs. VOUT.
-20
0
20
40
60
80
TA - TEMPERATURE - °C
100
120
140
100
120
140
0
Iout = -100mA
-1
-2
-3
-4
-40
-20
0
20
40
60
80
TA - TEMPERATURE - °C
Figure 6. VOH vs. Temperature.
29.0
VOH - OUTPUT HIGH VOLTAGE - V
0.25
0.20
0.15
0.10
0.05
0.00
-40
Figure 4. IOL vs. temperature.
(VOH-VCC) HIGH OUTPUT VOLTAGE DROP - V
IOLF – LOW LEVEL OUTPUT CURRENT
DURING FAULT CONDITION – mA
4
0
140
200
OUTPUT LOW VOLTAGE - V
5
1
Figure 3. IOH vs. temperature.
-40
10
Figure 7. VOL vs. Temperature.
12
VOUT=VEE + 2.5V
VOUT=VEE + 15V
6
60
110
TA - TEMPERATURE - °C
160
-40°C
+25°C
+125°C
28.5
28.0
27.5
27.0
26.5
0
Figure 8. VOH vs. IOH.
0.2
0.4
0.6
IOH - OUTPUT HIGH CURRENT - A
0.8
20
-40°C
+25°C
+125°C
5
ICC1 - SUPPLY CURRENT - mA
VOL - OUPUT LOW VOLTAGE - V
6
4
3
2
1
0
0
0.5
1
1.5
IOL - OUTPUT LOW CURRENT - A
2
Icc1H
Icc1L
-40
-20
0
20
40
60
80
TA - TEMPERATURE - °C
100
120
140
2.60
ICC2 – OUTPUT SUPPLY CURRENT – mA
ICC2 - OUTPUT SUPPLY CURRENT - mA
5
Figure 10. ICC1 vs. temperature.
3.0
2.9
2.8
Icc2H
2.7
-40
-20
0
20
40
60
80
TA - TEMPERATURE - °C
100
120
2.55
2.50
2.45
2.40
2.35
140
Figure 11. ICC2 vs. temperature.
ICC2H
ICC2L
15
20
25
VCC2 – OUTPUT SUPPLY VOLTAGE – V
30
Figure 12. ICC2 vs. VCC2.
-0.15
-0.10
IE - VE SUPPLY CURRENT - mA
ICGH - BLANKING CAPACITOR
CHARGING CURRENT -mA
10
0
2.5
Figure 9. VOL vs. IOL.
15
-0.2
-0.25
-0.15
-0.20
-0.25
IEH
IEL
-0.30
-0.35
-0.40
-0.45
-0.3
-40
-20
0
Figure 13. ICHG vs. temperature.
13
20 40 60 80
TA - TEMPERATURE - °C
100 120 140
-0.50
-40
-20
0
Figure 14. IE vs. temperature.
20 40 60 80
TEMPERATURE - °C
100
120
140
4
IC (mA)
3
2
1
0
-40°C
+25°C
+100°C
0
0.5
1.0
VDESAT -DESAT THRESHOLD - V
7.5
6.5
6.0
2.0
1.5
7.0
-40
-20
0
20 40
60 80
TEMPERATURE - °C
IOUT (mA)
Figure 15. IC vs. IOUT.
140
0.40
TpLH
TpHL
TP – PROPAGATION DELAY – μs
TP - PROPAGATION DELAY - μs
120
Figure 16. DESAT threshold vs. temperature.
0.50
0.40
0.30
0.20
-40
-20
0
20
40
60
80
TEMPERATURE - °C
100
120
tPHL
tPLH
0.35
0.30
0.25
0.20
140
Figure 17. Propagation delay vs. temperature.
20
25
VCC – SUPPLY VOLTAGE – V
15
30
Figure 18. Propagation delay vs. supply voltage.
0.50
0.40
VCC1=4.5V
VCC1=5.0V
VCC1=5.5V
0.35
PROPAGATION DELAY - μs
PROPAGATION DELAY - μs
100
0.30
0.25
0.45
VCC1=4.5V
VCC1=5.0V
VCC1=5.5V
0.40
0.35
0.30
0.25
0.20
-50
0
50
TEMPERATURE - °C
100
Figure 19. VIN to high propagation delay vs. temperature.
14
150
0.20
-50
0
50
TEMPERATURE - °C
100
Figure 20. VIN to low propagation delay vs. temperature.
150
0.40
0.40
tPLH
tPHL
tPLH
tPHL
0.35
DELAY – s
DELAY – s
0.35
0.30
0.25
0.25
0.20
0
20
40
60
LOAD CAPACITANCE – nF
80
0.45
3.0
0.40
2.5
0.35
-50
0
50
TEMPERATURE - °C
100
40
50
0
50
TEMPERATURE - °C
100
150
Figure 24. DESAT sense to 10% Vout delay vs. temperature.
0.008
3.6
VCC2 = 15 V
VCC2 = 30 V
3.2
0.006
DELAY – ms
DELAY – s
20
30
LOAD RESISTANCE – 
2.0
1.0
-50
150
Figure 23. DESAT sense to 90% Vout delay vs. temperature.
2.8
2.4
0.004
0.002
2.0
1.6
10
1.5
0.30
0.25
0
Figure 22. Propagation delay vs. load resistance.
DELAY – s
DELAY – s
0.20
100
Figure 21. Propagation delay vs. load capacitance.
0
-50
0
50
TEMPERATURE - °C
100
Figure 25. DESAT sense to low level fault signal delay vs. temperature.
15
0.30
150
0
10
20
30
LOAD CAPACITANCE – nF
40
Figure 26. DESAT sense to 10% Vout delay vs. load capacitance.
50
0.0030
12
Vcc1 = 4.5V
Vcc1 = 5.0V
Vcc1 = 5.5V
VCC2 = 15 V
VCC2 = 30 V
10
DELAY - μs
DELAY – μs
0.0025
0.0020
6
0.0015
0.0010
8
10
20
40
30
LOAD RESISTANCE – Ω
4
50
Figure 27. DESAT sense to 10% Vout delay vs. load resistance.
-50
0
50
TEMPERATURE – °C
100
150
Figure 28. RESET to high level fault signal delay vs. temperature.
Test Circuit Diagrams
0.1μF
VIN+
16
VLED2+
15
10mA
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
10
7
VLED+
VOUT
10
8
VLED
VEE
9
8
VLED
VEE
9
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
GND1
2
0.4V
IFAULT
Figure 30. IFAULTH test circuit.
VE
1
5
RESET
VEE
6
FAULT
VC
7
VLED+
VOUT
10
8
VLED
VEE
9
+
_
Figure 31. IOH pulsed test circuit.
16
2
VE
VIN
12
11
VE
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
12
1
GND1
2
0.1μF
+
_
5V
GND1
3
Figure 29. IFAULTL test circuit.
0.1
4.5V
1
30V
+
_
15V
Pulsed
IOUT
0.1μF
30V
+
_
0.1μF
5
RESET
VEE
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
Figure 32. IOL pulsed test circuit.
0.1μF
30V
+
_
+
_
IFAULT
2
0.1μF
0.1μF
VE
+
_
+
_
0.4V
GND1
+
_
4.5V
1
15V
0.1μF
Pulsed
30V
IOUT
+
_
+
_
0.1μF
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
0.1μF
30V
6
FAULT
VC
11
IOUT
14V
7
VLED+
VOUT
10
+
_
8
VLED
VEE
9
30V
0.1μF
+
_
0.1μF
VLED2+
15
VIN
DESAT
14
VCC1
+
_
4
5
RESET
VCC2
13
VEE
12
6
FAULT
VC
7
VLED+
VOUT
8
VLED
11
0.1μF
10
V OUT
+
_
VIN+
VLED2+
15
5.5V 0.1μF
3
VIN
DESAT
14
4
VCC1
VCC2
13
17
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
30V
VOUT 2V
Pulsed
30V
0.1μF
+
_
0.1μF
0.1μF
+
_
0.1μF
VE
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
12
1
GND1
2
5
RESET
VEE
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
VE
16
5V 0.1μF
1
GND1
2
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
12
5
RESET
VEE
11
6
FAULT
VC
11
VOUT
10
7
VLED+
VOUT
10
VEE
9
8
VLED
VEE
9
RESET
VEE
12
6
FAULT
VC
7
VLED+
8
VLED
Figure 37. ICC1L test circuit.
3
0.1μF
Figure 36. ICC1H test circuit.
2
5
15
VEE 9
16
ICC1
VLED2+
5.5V
30V
100mA
VE
GND1
VIN+
ICC1
Figure 35. VOL test circuit.
1
30V
+
_
VIN+
3
16
+
_
5V 0.1μF
16
2
2
VE
0.1μF
VE
GND1
GND1
Figure 34. VOH pulsed test circuit.
+
_
+
_
Figure 33. IOLF test circuit.
1
5V
1
Figure 38. ICC2H test circuit.
0.1μF
30V
+
_
2
0.1μF
VE
+
_
GND1
+
_
5V
1
+
_
0.1μF
0.1μF
30V
+
_
0.1μF
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
30V
+
_
VIN+
5V 0.1μF
ICC2
0.1μF
+
_
0.1μF
VLED2+
15
3
VIN
DESAT
14
4
VCC1
5
VCC2
VEE
13
RESET
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
7V
IDSCHG
0.1μF 30V
5V 0.1μF
0.1μF
12
30V
0.1μF
+
_
Figure 41. IDSCHG test circuit.
VE
GND1
2
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
0.1μF
Figure 43. DESAT threshold test circuit.
18
16
7V
+
_
10mA
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
VE
16
1
GND1
2
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
0.1μF 15V
VIN
+
_
1
VLED2+
30V
0.1μF
ICHG
0.1μF
0.1μF
30V
+
_
ICHG
VOUT
0.1μF Sweep
+
_
Figure 42. UVLO threshold test circuit.
SWEEP
5V
0.1μF
12
0.1μF
+
_
16
+
_
VIN+
VE
+
_
2
VIN+
2
Figure 40. ICHG pulsed test circuit.
+
_
GND1
16
GND1
30V
Figure 39. ICC2L test circuit.
1
VE
1
0.1μF
1
GND1
VE
16
2
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
15V
+
_
3k
Figure 44. tPLH, tPHL, tr, tf test circuit.
0.1μF 30V
+
_
2
0.1μF
+
_
16
GND1
+
_
VE
1
VOUT
10Ω
10nF
0.1μF
0.1μF 30V
+
_
VIN
VCC1
5
RESET
DESAT
VCC2
VEE
14
4
6
FAULT
VLED+
VC
11
VOUT
100
VLED
VEE
9
7
8
5V
0.1μF
133
VOUT
12
0.1μF
0.1μF 30V
+
_
10Ω
16
5
RESET
DESAT
VCC2
VEE
14
4
VIN
VCC1
6
FAULT
VLED+
VC
11
VOUT
10
+
_
3k
VIN HIGH TO LOW
VFAULT
7
8
VLED
VEE
15
0.1μF 30V
1
2
SCOPE
0.1μF
0.1μF
RESET
6
FAULT
VLED+
VC
11
7
VOUT
10
8
VLED
VEE
9
VOUT
12
9
10Ω
3k
0.1μF 30V
+
_
0.1μF
10nF
VOUT
12
16
5
RESET
DESAT
VCC2
VEE
14
4
VIN
VCC1
6
VC
11
7
FAULT
VLED+
VOUT
10
8
VLED
VEE
9
VE
16
VLED2+
15
14
4
5
RESET
6
FAULT
VLED+
VC
11
7
VOUT
10
8
VLED
VEE
9
1
5V
10Ω
10nF
0.1μF 30V
+
_
0.1μF
15
13
VOUT
12
0.1μF
10Ω
10nF
VOUT
0.1μF
3 kΩ
0.1μF
SCOPE
0.1μF
10Ω
10nF
VE
16
VLED2+
15
14
4
5
RESET
DESAT
VCC2
VEE
6
FAULT
VLED+
VC
11
7
VOUT
10
8
VLED
VEE
9
+
_
9V
GND1
VIN+
VIN
VCC1
3
13
12
2
25V
750Ω
19
0.1μF 30V
Figure 48. UVLO delay test circuit.
DESAT
VCC2
VEE
Figure 49. CMR test circuit, LED2 off.
VIN
13
VE
VLED2+
3
13
VIN
VCC1
3
3 kΩ
GND1
VIN+
5
DESAT
VCC2
VEE
GND1
VIN+
2
5V
0.1μF
Figure 47. tRESET(FAULT) test circuit.
5V
VFAULT
1
STROBE 8V
+
_
VE
VLED2+
3
5V
0.1μF
VIN
VCC1
14
4
15
Figure 46. tDESAT(FAULT) test circuit.
GND1
VIN+
2
16
3
3k
10nF
Figure 45. tDESAT(10%) test circuit.
1
VE
VLED2+
2
_
_
3k
VIN
+
+
3
5V
0.1μFF
155
_
2
GND1
VIN+
1
0.1μF 30V
+
_
166
+
VE
VLED2+
+
_
GND1
VIN+
1
Figure 50. CMR test circuit, LED2 on.
25V
13
0.1μF
12
10Ω
10nF
1
5V
2
0.1μF
100pF
VLED2+
15
DESAT
VCC2
VEE
14
4
5
RESET
6
FAULT
VLED+
VC
11
VOUT
10
VLED
VEE
9
7
8
1
16
VIN
VCC1
3
3 kΩ
VE
GND1
VIN+
13
5V
2
25V
0.1μF
3 kΩ
SCOPE
10Ω
0.1μF
100pF
16
VLED2+
15
14
4
5
RESET
DESAT
VCC2
VEE
6
FAULT
VLED+
VC
11
VOUT
10
VLED
VEE
9
7
10nF
VE
VIN
VCC1
3
12
GND1
VIN+
8
25V
13
0.1μF
12
10Ω
SCOPE
10nF
VCM
VCM
Figure 51. CMR test circuit, LED1 off.
Figure 52. CMR test circuit, LED1 on.
VIN-
VIN-
0V
2.5 V
VIN+
2.5 V
2.5 V
tr
VIN+
2.5 V
5.0 V
tf
tr
90%
tf
90%
50%
10%
VOUT
tPLH
50%
10%
VOUT
tPLH
tPHL
Figure 53. VOUT propagation delay waveforms, noninverting configuration.
tPHL
Figure 54. VOUT propagation delay waveforms, inverting configuration.
tDESAT (FAULT)
tDESAT (10%)
tDESAT (LOW)
7V
VDESAT
VOUT
50%
tDESAT (90%)
90%
10%
FAULT
50% (2.5 V)
tRESET (FAULT)
RESET
Figure 55. Desat, VOUT, fault, reset delay waveforms.
20
50%
16
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
12
30V
+
_
VIN+
0.1μF
5V 0.1μF
0.1μF
5
RESET
VEE
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
+
_
+
_
5V 0.1μF
VE
GND1
2
0.1μF
IC
30V
+
_
650μF
Figure 56. ICH test circuit.
VE
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
VE
16
1
GND1
2
0.1μF
30V
+
_
1
0.1μF
0.1μF
IC
30V
+
_
Figure 57. ICH test circuit.
IE
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
30V
0.1μF
+
_
VIN+
2
5V 0.1μF
0.1μF
5
RESET
VEE
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
12
+
_
16
GND1
0.1μF
IC
30V
+
_
Figure 58. ICL test circuit.
IE
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
2
+
_
Figure 60. IEL test circuit.
21
0.1μF
30V
+
_
5V 0.1μF
16
GND1
GND1
2
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
12
0.1μF
0.1μF
30V
+
_
0.1μF
30V
0.1μF
5
RESET
VEE
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
Figure 59. IEH test circuit.
VE
1
1
+
_
VE
1
0.1μF
30V
+
_
Typical Application/Operation
Introduction to Fault Detection and Protection
The power stage of a typical three phase inverter is susceptible to several types of failures, most of which are
potentially destructive to the power IGBTs. These failure
modes can be grouped into four basic categories: phase
and/or rail supply short circuits due to user misconnect or
bad wiring, control signal failures due to noise or computational errors, overload conditions induced by the load,
and component failures in the gate drive circuitry. Under
any of these fault conditions, the current through the
IGBTs can increase rapidly, causing excessive power dissipation and heating. The IGBTs become damaged when
the current load approaches the saturation current of the
device, and the collector to emitter voltage rises above the
saturation voltage level. The drastically increased power
dissipation very quickly overheats the power device and
destroys it. To prevent damage to the drive, fault protection must be implemented to reduce or turn--off the overcurrents during a fault condition.
The alternative protection scheme of measuring IGBT
current to prevent desaturation is effective if the short
circuit capability of the power device is known, but this
method will fail if the gate drive voltage decreases enough
to only partially turn on the IGBT. By directly measuring
the collector voltage, the ACPL-38JT limits the power
dissipation in the IGBT even with insufficient gate drive
voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in the
IGBT is monitored, while the current sense method relies
on a preset current threshold to predict the safe limit of
operation. Therefore, an overly- conservative overcurrent
threshold is not needed to protect the IGBT.
A circuit providing fast local fault detection and shutdown
is an ideal solution, but the number of required components, board space consumed, cost, and complexity have
until now limited its use to high performance drives. The
features which this circuit must have are high speed, low
cost, low resolution, low power dissipation, and small size.
The recommended application circuit shown in Figure 61
illustrates a typical gate drive implementation using the
ACPL-38JT.
Applications Information
The ACPL-38JT satisfies these criteria by combining a high
speed, high output current driver, high voltage optical
isolation between the input and output, local IGBT desaturation detection and shut down, and an optically
isolated fault status feedback signal into a single 16-pin
surface mount package.
The fault detection method, which is adopted in the
ACPL-38JT, is to monitor the saturation (collector) voltage
of the IGBT and to trigger a local fault shutdown sequence
if the collector voltage exceeds a predetermined
threshold. A small gate discharge device slowly reduces
the high short circuit IGBT current to prevent damaging
voltage spikes. Before the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state
of the IGBT, the fault detect circuitry is simply disabled to
prevent false ‘fault’ signals.
22
Recommended Application Circuit
The ACPL-38JT has both inverting and non-inverting gate
control inputs, an active low reset input, and an open
collector fault output suitable for wired ‘OR’ applications.
The four supply bypass capacitors (0.1 F) provide the
large transient currents necessary during a switching
transition. Because of the transient nature of the charging
currents, a low current (5 mA) power supply suffices.
The desat diode and 100pF capacitor are the necessary
external components for the fault detection circuitry. The
gate resistor (10 ) serves to limit gate charge current and
indirectly control the IGBT collector voltage rise and fall
times. The open collector fault output has a passive 3.3 k
pull-up resistor and a 330 pF filtering capacitor.
A clamping diode between VCC1 and RESET will prevent
positive going voltage noises affecting the FAULT status.
A 47 k pulldown resistor on VOUT provides a more
predictable high level output voltage (VOH). In this application, the IGBT gate driver will shut down when a fault is
detected and will not resume switching until the microcontroller applies a reset signal.
0.1μF
μC
−
+
5V
3.3kΩ
330pF
VE
16
V IN+
V LED2+
15
3
V IN-
DESAT
14
4
V CC1
V CC2
13
5
RESET
V EE
12
6
FAULT
VC
11
7
V LED+
V OUT
10
8
V LED--
V EE
9
1
GND1
2
100pF
0.1μF
100Ω D DESAT
0.1μF
+V F −
V CC2 =18V
0.1μF
+
−
RG
47kΩ
Q1
+
V CE
−
+
−
V EE = -5V Q2
+
V CE
−
3-Phase
Output
Figure 61. Recommended application circuit.
Description of Operation/Timing
Fault Condition
Figure 62 illustrates input and output waveforms under
the conditions of normal operation, a desat fault condition,
and normal reset behavior.
When the voltage on the DESAT pin exceeds 7 V while
the IGBT is on, VOUT is slowly brought low in order to
“softly” turn-off the IGBT and prevent large di/dt induced
voltages. Also activated is an internal feedback channel
which brings the FAULT output low for the purpose of
notifying the micro-controller of the fault condition. See
Figure 62.
Normal Operation
During normal operation, VOUT of the ACPL-38JT is controlled by either VIN+ or VIN-, with the IGBT collector-toemitter voltage being monitored through DDESAT. The
FAULT output is high and the RESET input should be held
high. See Figure 62.
NORMAL
OPERATION
VINNON-INVERTING
CONFIGURED
INPUTS
INVERTING
CONFIGURED
INPUTS
0V
5V
VIN+
VIN-
5V
VIN+
5V
VDESAT
VOUT
FAULT
RESET
Figure 62. Timing diagram.
23
FAULT
CONDITION
7V
Reset
The FAULT output remains low until RESET is brought
low. See Figure 62. While asserting the RESET pin (LOW),
the input pins must be asserted for an output low state
(VIN+ is LOW or VIN- is HIGH). This may be accomplished
either by software control (i.e. of the microcontroller) or
hardware control (see Figures 71 and 72).
RESET
Slow IGBT Gate Discharge During Fault Condition
When a desaturation fault is detected, a weak pull-down
device in the ACPL-38JT output drive stage will turn on
to ‘softly’ turn off the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current that
could cause damaging voltage spikes due to lead and
wire inductance. During the slow turn off, the large output
pull-down device remains off until the output voltage falls
below VEE + 2 Volts, at which time the large pull down
device clamps the IGBT gate to VEE.
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
theshold. This time period, called the DESAT blanking
time, is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT
capacitor. The nominal blanking time is calculated in terms
of external capacitance (CBLANK), FAULT threshold voltage
(VDESAT ), and DESAT charge current (ICHG) as tBLANK =
CBLANK x VDESAT / ICHG. The nominal blanking time with the
recommended 100 pF capacitor is 100 pF * 7 V / 250 A =
2.8 sec. The capacitance value can be scaled slightly to
adjust the blanking time, though a value smaller than 100
pF is not recommended.
This nominal blanking time also represents the longest
time it will take for the ACPL-38JT to respond to a DESAT
fault condition. If the IGBT is turned on while the collector
and emitter are shorted to the supply rails (switching into
a short), the soft shut-down sequence will begin after approximately 3 sec. If the IGBT collector and emitter are
shorted to the supply rails after the IGBT is already on, the
response time will be much quicker due to the parasitic
parallel capacitance of the DESAT diode. The recommended 100 pF capacitor should provide adequate blanking as
well as fault response times for most applications.
Under Voltage Lockout
The ACPL-38JT Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insufficient gate
voltage to the IGBT by forcing the ACPL-38JT output low
during power-up. IGBTs typically require gate voltages of
15 V to achieve their rated VCE(ON) voltage. At gate voltages
below 13 V typically, their on-voltage increases dramatically, especially at higher currents. At very low gate voltages
(below 10 V), the IGBT may operate in the linear region and
quickly overheat. The UVLO function causes the output to
be clamped whenever insufficient operating supply (VCC2)
24
is applied. Once VCC2 exceeds VUVLO+ (the positive-going
UVLO threshold), the UVLO clamp is released to allow the
device output to turn on in response to input signals. As
VCC2 is increased from 0 V (at some level below VUVLO+),
first the DESAT protection circuitry becomes active.
As VCC2 is further increased (above VUVLO+), the UVLO
clamp is released. Before the time the UVLO clamp is
released, the DESAT protection is already active. Therefore,
the UVLO and DESAT FAULT DETECTION features work
together to provide seamless protection regardless of
supply voltage (VCC2).
Behavioral Circuit Schematic
The functional behavior of the ACPL-38JT is represented
by the logic diagram in Figure 63 which fully describes the
interaction and sequence of internal and external signals
in the ACPL-38JT.
Input IC
In the normal switching mode, no output fault has been
detected, and the low state of the fault latch allows the
input signals to control the signal LED. The fault output is
in the open-collector state, and the state of the Reset pin
does not affect the control of the IGBT gate. When a fault
is detected, the FAULT output and signal input are both
latched. The fault output changes to an active low state,
and the signal LED is forced off (output LOW). The latched
condition will persist until the Reset pin is pulled low.
Output IC
Three internal signals control the state of the driver
output: the state of the signal LED, as well as the UVLO and
Fault signals. If no fault on the IGBT collector is detected,
and the supply voltage is above the UVLO threshold, the
LED signal will control the driver output state. The driver
stage logic includes an interlock to ensure that the pull-up
and pull-down devices in the output stage are never on at
the same time. If an undervoltage condition is detected,
the output will be actively pulled low by the 50x DMOS
device, regardless of the LED state. If an IGBT desaturation
fault is detected while the signal LED is on, the Fault signal
will latch in the high state. The triple darlington AND the
50x DMOS device are disabled, and a smaller 1x DMOS
pull-down device is activated to slowly discharge the
IGBT gate. When the output drops below two volts, the
50x DMOS device again turns on, clamping the IGBT gate
firmly to Vee. The Fault signal remains latched in the high
state until the signal LED turns off.
250 μA
VIN+ (2)
VIN– (3)
+
–
LED
VCC1 (4)
GND (1)
–
+
UVLO
DELAY
DESAT (14)
7V
VCC2 (13)
12 V
VC (11)
FAULT
FAULT (6)
VE (16)
Q
R S
VOUT (10)
50 x
FAULT
RESET (5)
VEE (9,12)
1x
Figure 63. Behavioral circuit schematic
VE
16
VIN+
VLED2+
3
VIN
4
VCC1
1
GND1
2
VE
16
VIN+
VLED2+
15
3
DESAT
14
MJD44H11 or
D44VH10
4.5Ω
VIN
4
VCC1
VCC2
13
5
RESET
VEE
12
2.5Ω
6
FAULT
VC
11
MJD45H11 or
D45VH10
7
VLED+
VOUT
10
8
VLED
VEE
9
1
GND1
15
2
DESAT
14
VCC2
13
12
100pF
5
RESET
VEE
6
FAULT
VC
11
10Ω
7
VLED+
VOUT
10
10nF
8
VLED
VEE
9
15V
16
VIN+
VLED2+
15
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
GND1
0.1μF
2
5V
3
+
_
μC
3.3kΩ
330pF
Figure 66. FAULT Pin CMR protection.
25
Figure 65. DESAT pin protection.
VE
1
100Ω
-5V
Figure 64. Output pull-down resistor.
100pF
Rg
DDESAT
Other Recommended Components
Driving with Standard CMOS/TTL for High CMR
The application circuit in Figure 61 includes an output pulldown resistor, a DESAT pin protection resistor, a FAULT pin
capacitor (330 pF), and a FAULT pin pull-up resistor.
Capacitive coupling from the isolated high voltage
circuitry to the input referred circuitry is the primary CMR
limitation. This coupling must be accounted for to achieve
high CMR performance. The input pins VIN+ and VIN- must
have active drive signals to prevent unwanted switching
of the output under extreme common mode transient
conditions. Input drive circuits that use pull-up or pulldown resistors, such as open collector configurations,
should be avoided. Standard CMOS or TTL drive circuits
are recommended.
Output Pull-Down Resistor
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of VCC2. If the output
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly VCC2-3(VBE)
to VCC2 within a period of several microseconds. To limit
the output voltage to VCC2-3(VBE), a pull-down resistor
between the output and VEE is recommended to sink a
static current of several 650 A while the output is high.
Pull-down resistor values are dependent on the amount
of positive supply and can be adjusted according to the
formula, Rpull-down = [VCC2-3 * (VBE)] / 650 A.
DESAT Pin Protection
User-Configuration of the ACPL-38JT Input Side
The VIN+, VIN-, FAULT and RESET input pins make a wide
variety of gate control and fault configurations possible,
depending on the motor drive requirements. The
ACPL-38JT has both inverting and nonninverting gate
control inputs, an open collector fault output suitable for
wired ‘OR’ applications and an active low reset input.
The freewheeling of flyback diodes connected across the
IGBTs can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage
of the diode. This may result in a large negative voltage
spike on the DESAT pin which will draw substantial current
out of the IC if protection is not used. To limit this current
to levels that will not damage the IC, a 100 ohm resistor
should be inserted in series with the DESAT diode. The
added resistance will not alter the DESAT threshold or the
DESAT blanking time.
The Gate Drive Voltage Output of the ACPL-38JT can be
configured as inverting or non-inverting using the VIN–
and VIN+ inputs. As shown in Figure 67, when a non-inverting configuration is desired, VIN– is held low by connecting it to GND1 and VIN+ is toggled. As shown in Figure
68, when an inverting configuration is desired, VIN+ is held
high by connecting it to VCC1 and VIN– is toggled.
Pull-up Resistor on FAULT Pin
Local Shutdown, Local Reset
The FAULT pin is an open-collector output and therefore
requires a pull-up resistor to provide a high-level signal.
As shown in Figure 69, the fault output of each ACPL-38JT
gate driver is polled separately, and the individual reset
lines are asserted low independently to reset the motor
controller after a fault condition.
Capacitor on FAULT Pin for High CMR
Rapid common mode transients can affect the fault pin
voltage while the fault output is in the high state. A 330 pF
capacitor (Fig. 66) should be connected between the fault
pin and ground to achieve adequate CMOS noise margins
at the specified CMR value of 15 kV/s. The added capacitance does not increase the fault output delay when a desaturation condition is detected.
Protection on RESET Pin for High CMR
Large voltage spike on RESET due to excessive switching
noise coupling could trigger false FAULT output signal. In
such cases connecting a 330pF filtering capacitor between
RESET and GROUND or a clamping diode between RESET
to VCC1 will eliminate the false FAULT signal.
26
Driving Input of ACPL-38JT in Non-Inverting/
Inverting Mode
Global-Shutdown, Global Reset
As shown in Figure 70, when configured for inverting
operation, the ACPL-38JT can be configured to shutdown
automatically in the event of a fault condition by tying the
FAULT output to VIN+. For high reliability drives, the open
collector FAULT outputs of each ACPL-38JT can be wire
‘OR’ed together on a common fault bus, forming a single
fault bus for interfacing directly to the micro-controller.
When any of the six gate drivers detects a fault, the fault
output signal will disable all six ACPL-38JT gate drivers
simultaneously and thereby provide protection against
further catastrophic failures.
GND1
VE
16
1
GND1
2
VIN+
VLED2+
15
2
3
VIN
DESAT
14
3
4
VCC1
VCC2
13
VEE
VE
16
VIN+
VLED2+
15
VIN
DESAT
14
4
VCC1
VCC2
13
12
5
RESET
VEE
12
5
RESET
6
FAULT
VC
11
6
FAULT
VC
11
7
VLED+
VOUT
10
7
VLED+
VOUT
10
8
VLED
VEE
9
8
VLED
VEE
9
Figure 67. Typical input configuration, noninverting.
+
_
μC
μC
+
_
+
_
μC
1
Figure 68. Typical Input Configuration, Inverting.
VE
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
10
8
VLED
VEE
9
1
GND1
2
Figure 69. Local shutdown, local reset configuration.
Auto-Reset
Resetting Following a Fault Condition
As shown in Figure 71, when the inverting VIN- input is
connected to ground (non-inverting configuration), the
ACPL-38JT can be configured to reset automatically by
connecting RESET to VIN+. In this case, the gate control
signal is applied to the non-inverting input as well as the
reset input to reset the fault latch every switching cycle.
During normal operation of the IGBT, asserting the reset
input low has no effect. Following a fault condition, the
gate driver remains in the latched fault state until the gate
control signal changes to the ‘gate low’ state and resets
the fault latch. If the gate control signal is a continuous
PWM signal, the fault latch will always be reset by the
next time the input signal goes high. This configuration
protects the IGBT on a cycle-by-cycle basis and automatically resets before the next ‘on’ cycle. The fault outputs can
be wire ‘OR’ed together to alert the microcontroller, but
this signal would not be used for control purposes in this
(Auto-Reset) configuration. When the ACPL-38JT is configured for Auto-Reset, the guaranteed minimum FAULT
signal pulse width is 3 s.
To resume normal switching operation following a fault
condition (FAULT output low), the RESET pin must first be
asserted low in order to release the internal fault latch and
reset the FAULT output (high). Prior to asserting the RESET
pin low, the input (VIN) switching signals must be configured for an output (VOL) low state. This can be handled
directly by the microcontroller or by hardwiring to synchronize the RESET signal with the appropriate input
signal. Figure 72a shows how to connect the RESET to the
VIN+ signal for safe automatic reset in the non-inverting
input configuration. Figure 72b shows how to configure
the VIN+/RESET signals so that a RESET signal from the
microcontroller causes the input to be in the “outputoff ” state. Similarly, Figures 72c and 72d show automatic
RESET and microcontroller RESET safe configurations for
the inverting input configuration.
27
16
1
GND1
VIN+
VLED2+
15
2
VIN
DESAT
14
3
4
VCC1
VCC2
13
5
RESET
VEE
6
FAULT
VC
7
VLED+
VOUT
GND1
2
3
8
CONNECT TO
OTHER
RESETS
VLED
VE
16
VIN+
VLED2+
15
VIN
DESAT
14
4
VCC1
VCC2
13
12
5
RESET
VEE
12
11
6
FAULT
VC
11
10
7
VLED+
VOUT
10
VEE 9
8
VLED
VEE
9
C
CONNECT TO
OTHER
FAULTS
Figure 70. Global-shutdown, global reset configuration.
C
VIN+/
RESET
+
_
+
_
C
VE
1
VCC
FAULT
Figure 71. Auto-reset configuration.
VE
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
7
VLED+
VOUT
8
VLED
VEE
1
GND1
2
VE
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
10
7
VLED+
VOUT
10
9
8
VLED
VEE
9
VIN+
VCC
C
RESET
FAULT
Figure 72a. Safe hardware reset for non-inverting input configuration
(automatically resets for every VIN+ input).
C
RESET
FAULT
2
VCC
VE
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
1
GND1
2
VIN
C
RESET
FAULT
VE
16
VIN+
VLED2+
15
3
VIN
DESAT
14
4
VCC1
VCC2
13
5
RESET
VEE
12
6
FAULT
VC
11
1
GND1
2
6
FAULT
VC
11
7
VLED+
VOUT
10
7
VLED+
VOUT
10
8
VLED
VEE
9
8
VLED
VEE
9
Figure 72c. Safe hardware reset for inverting input configuration.
28
GND1
Figure 72b. Safe hardware reset for non-inverting input configuration.
VCC
VIN
1
Figure 72d. Safe hardware reset for inverting input configuration
(automatically resets for every VIN- input).
VE
16
VIN+
VLED2+
3
VIN
4
VCC1
5
1
GND1
2
VE
16
15
VLED2+
15
DESAT
14
DESAT
14
VCC2
13
VCC2
13
RESET
VEE
12
VEE
12
6
FAULT
VC
11
10Ω
VC
11
10Ω
2.5Ω
7
VLED+
VOUT
10
10nF
VOUT
10
10nF
8
VLED
VEE
9
VEE
9
MJD45H11 or
D45VH10
100pF
RC8Ω
15V
100pF
MJD44H11 or
D44VH10
4.5Ω
15V
-5V
-5V
Figure 73. Use of RC to further limit ION,PEAK.
Figure 74. Current buffer for increased drive current
Higher Output Current Using an External Current Buffer:
DESAT Diode and DESAT Threshold
To increase the IGBT gate drive current, a non-inverting
current buffer (such as the npn/pnp buffer shown in Figure
74) may be used. Inverting types are not compatible with
the de-saturation fault protection circuitry and should be
avoided. To preserve the slow IGBT turn-off feature during
a fault condition, a 10 nF capacitor should be connected
from the buffer input to VEE and a 10 W resistor inserted
between the output and the common npn/pnp base. The
MJD44H11/MJD45H11 pair is appropriate for currents up
to 8A maximum. The D44VH10/ D45VH10 pair is appropriate for currents up to 15 A maximum.
The DESAT diode’s function is to conduct forward current,
allowing sensing of the IGBT’s saturated collector-toemitter voltage, VCESAT, (when the IGBT is “on”) and to
block high voltages (when the IGBT is “off ”). During the
short period of time when the IGBT is switching, there is
commonly a very high dVCE/dt voltage ramp rate across
the IGBT’s collector-to-emitter. This results in ICHARGE (=
CD-DESAT x dVCE/dt) charging current which will charge
the blanking capacitor, CBLANK. In order to minimize this
charging current and avoid false DESAT triggering, it
is best to use fast response diodes. Listed in the below
table are fast-recovery diodes that are suitable for use as
a DESAT diode (DDESAT ). In the recommended application
circuit shown in Figure 61, the voltage on pin 14 (DESAT)
is VDESAT = VF + VCE, (where VF is the forward ON voltage
of DDESAT and VCE is the IGBT collector-to-emitter voltage).
The value of VCE which triggers DESAT to signal a FAULT
condition, is nominally 7V – VF. If desired, this DESAT
threshold voltage can be decreased by using multiple
DESAT diodes in series. If n is the number of DESAT diodes
then the nominal threshold value becomes VCE,FAULT(TH) =
7 V – n x VF. In the case of using two diodes instead of one,
diodes with half of the total required maximum reversevoltage rating may be chosen.
Part Number
Manufacturers
trr (ns)
Max. Reverse Voltage Rating
VRRM (Volts)
Package Type
MUR1100E
ON Semiconductor
75
1000
59-04 (axial leaded)
MURS160T3G
ON Semiconductor
75
600
Case 403A (surface mount)
UF4007
Vishay General Semi.
75
1000
DO-204AL (axial leaded)
BYV26E
Vishay General Semi.
75
1000
SOD57 (axial leaded)
29
Power Considerations
Operating Within the Maximum Allowable Power Ratings (Adjusting
Value of RG):
When choosing the value of RG, it is important to confirm
that the power dissipation of the ACPL-38JT is within the
maximum allowable power rating.
The steps for doing this are:
1. Calculate the minimum desired RG;
2. Calculate total power dissipation in the part referring
to Figure 76. (Average switching energy supplied to
ACPL-38JT per cycle vs. RG plot);
3. Compare the input and output power dissipation
calculated in step #2 to the maximum recommended
dissipation for the ACPL-38JT. (If the maximum recommended level has been exceeded, it may be necessary to raise the value of RG to lower the switching
power and repeat step #2.)
As an example, the total input and output power dissipation
can be calculated given the following conditions:
 ION, MAX ~ 2.0 A
 VCC2 = 18 V
 VEE = -5 V
 fCARRIER = 10 kHz
Step 2: Calculate total power dissipation in the ACPL-38JT:
The ACPL-38JT total power dissipation (PT ) is equal to the
sum of the input-side power (PI) and output-side power
(PO):
PT = PI + PO
PI = ICC1 * VCC1
PO = PO(BIAS) + PO(SWTICH)
= ICC2 * (VCC2–VEE ) + ESWITCH * fSWITCH
where,
PO (BIAS) = steady-state power dissipation in the ACPL-38JT
due to biasing the device.
PO (SWITCH) = transient power dissipation in the ACPL-38JT
due to charging and discharging power device gate.
ESWITCH = Average Energy dissipated in ACPL-38JT due to
switching of the power device over one switching cycle
(J/cycle).
fSWITCH = average carrier signal frequency.
3
Step 1: Calculate RG minimum from IOL peak specification:
RG =
=
=
2
ION, IOFF (A)
To find the peak charging lOL assume that the gate is
initially charged the steady-state value of VEE. Therefore
apply the following relationship:
1
-1
IOL, PEAK
-2
[VCC2 – 1 – (VOL + VEE )]
-3
18 V – 1 V – (1.5 V + (-5 V))
2.0 A
=
10.25 
≈
10.5  (for a 1% resistor)
(Note from Figure 75 that the real value of IOL may vary
from the value calculated from the simple model shown.)
IOFF (MAX.)
0
[[email protected] A – (VOL+VEE)]
IOL, PEAK
MAX. ION, IOFF vs. GATE RESISTANCE (VCC2 / VEE2 = 25 V / 5 V)
4
ION (MAX.)
0
20
40
60
80
100 120 140
Rg (Ω)
160
180 200
Figure 75. Typical peak ION and IOFF currents vs. Rg (for ACPL-38JT output
driving an IGBT rated at 600 V/100 A).
For RG = 10.5, the value read from Figure 76 is ESWITCH =
6.05 J. Assume a worst-case average ICC1 = 16.5 mA
(which is given by the average of ICC1H and ICC1L). Similarly
the average ICC2 = 5.5 mA.
PI = 16.5 mA * 5.5 V = 90.8 mW
PO = PO(BIAS) + PO(SWITCH)
= 5.5 mA * (18 V – (–5 V)) + 6.051 J * 10 kHz
= 126.5 mW + 60.51 mW
= 187.01 mW
30
Step 3: Compare the calculated power dissipation with the absolute
maximum values for the ACPL-38JT:
For the example,
PI = 90.8 mW < 150 mW (abs. max.) OK
PO = 187.01 mW < 600 mW (abs. max.) OK
Therefore, the power dissipation absolute maximum
rating has not been exceeded for the example.
Ess (μJ)
Please refer to the following Thermal Model section for an
explanation on how to calculate the maximum junction
temperature of the ACPL-38JT for a given PC board layout
configuration.
9
8
7
6
5
4
3
2
1
0
SWITCHING ENERGY vs. GATE RESISTANCE
(VCC2 / VEE2 = 25 V / 5 V)
As long as the maximum power specification is not
exceeded, the only other limitation to the amount of
power one can dissipate is the absolute maximum junction
temperature specification of 140°C. The junction temperatures can be calculated with the following equations:
Tji = Pi (i1 + 1A) + TA
Tjo = Po (o9,12 + 9,12A) + TA
where Pi = power into input IC and Po = power into output
IC.
Since 1A and θ9,12A are dependent on PCB layout
and airflow, their exact number may not be available.
Therefore, a more accurate method of calculating the
junction temperature is with the following equations:
Tji = Pii1 + TP1
Tjo = Poo9,12 + TP9,12
These equations, however, require that the pin 1 and pins
9, 12 temperatures be measured with a thermal couple on
the pin at the ACPL-38JT package edge.
Ess (Qg = 650 nC)
Pi = 90.8 mW, Po = 314 mW, TA = 125°C, and assuming the
thermal model shown in Figure 77 below.
0
50
100
Rg (Ω)
150
200
Tji = (90.8 mW)(60°C/W + 50°C/W) + 125°C = 135°C
Tjo = (187.01 mW)(30°C/W + 50°C/W) + 125°C = 140°C
Figure 76. Switching energy plot for calculating average Pswitch
(for ACPL-38JT output driving an IGBT rated at 600 V/100 A).
If we, however, assume a worst case PCB layout and no
air flow where the estimated q1A and q9,12A are 100°C/W.
Then the junction temperatures become
Thermal Model
Tji = (90.8 mW)(60°C/W + 100°C/W) + 125°C = 140°C
Tjo = (187.01 mW)(30°C/W + 100°C/W) + 125°C = 149°C
The ACPL-38JT is designed to dissipate the majority of the
heat through pins 1 for the input IC and pins 9 and 12 for
the output IC. (There are two VEE pins on the output side,
pins 9 and 12, for this purpose.) Heat flow through other
pins or through the package directly into ambient are
considered negligible and not modeled here.
In order to achieve the power dissipation specified in the
absolute maximum specification, it is imperative that
pins 1, 9, and 12 have ground planes connected to them.
both of which are within the absolute maximum specification of 150°C.
If the calculated junction temperatures for the thermal
model in Figure 77 is higher than 150°C, the pin temperature for pins 9 and 12 should be measured (at the package
edge) under worst case operating environment for a more
accurate estimate of the junction temperatures.
From the earlier power dissipation calculation example:
Tji = junction temperature of input side IC
Tjo
Tji
Tjo = junction temperature of output side IC
l9, 12 = 30°C/W
I1 = 60°C/W
TP1 = pin 1 temperature at package edge
TP9,12 = pin 9 and 12 temperature at package edge
I1 = input side IC to pin 1 thermal resistance
TP9, 12
TP1
1A = 50°C/W*
9, 12A = 50°C/W*
TA
Figure 77. Thermal Model for ACPL-38JT
31
I9,12 = output side IC to pin 9 and 12 thermal resistance
1A = pin 1 to ambient thermal resistance
9,12A = pin 9 and 12 to ambient thermal resistance
* The 1A and 9,12A values shown here are for PCB layouts shown in Figure 77
with reasonable air flow. This value may increase or decrease by a factor of
2 depending on PCB layout and/or airflow.
Printed Circuit Board Layout Considerations
Adequate spacing should always be maintained between
the high voltage isolated circuitry and any input referenced circuitry. Care must be taken to provide the same
minimum spacing between two adjacent high-side
isolated regions of the printed circuit board. Insufficient
spacing will reduce the effective isolation and increase
parasitic coupling that will degrade CMR performance.
The placement and routing of supply bypass capacitors
requires special attention. During switching transients,
the majority of the gate charge is supplied by the bypass
capacitors. Maintaining short bypass capacitor trace
lengths will ensure low supply ripple and clean switching
waveforms. See Figure 77A.
Bypass Cap
C1, C2, C4
Bypass Capacitors should be placed in between these
pins: VCC2 to VE, VE to VEE, VCC1 to GND1 and VCC2 to VEE.
Ground plane connections are necessary for PIN1 (GND1)
and PIN 9 (VEE) in order to achieve maximum power as the
ACPL-38JT is designed to dissipate the majority of heat
generated through these pins. Actual power dissipation
will depend on the application environment (PCB layout,
airflow, part placement, etc. (See Figure 77B and 77C).
VE should have direct connection (Kelvin connection) to
IGBT Emitter to avoid switching noise on the ground line
affecting accurate DESAT voltage sensing. See Figure77C.
Ground Plane for GND1
(Pin 1)
Bypass Cap
C13
ACPL-36JV/38JT
Top Gate
Driver (U1)
Board Isolation
Figure 77a. Bypass Capacitors
Ground Plane for VEE (Pin 9)
Figure 77b. Ground Plane
Kelvin Connection between VEE and IGBT Emitter
IGBT
Emitter
Figure 77c. Kelvin Connection between VEE and IGBT Emitter
32
System Considerations
Propagation Delay Difference (PDD)
The ACPL-38JT includes a Propagation Delay Difference
(PDD) specification intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 62) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between
the high and low voltage motor rails, a potentially catastrophic condition that must be prevented.
To minimize dead time in a given design, the turn-on of
the ACPL-38JT driving Q2 should be delayed (relative to
the turn-off of the ACPL-38JT driving Q1) so that under
worst-case conditions, transistor Q1 has just turned off
when transistor Q2 turns on, as shown in Figure 80. The
amount of delay necessary to achieve this condition is
equal to the maximum value of the propagation delay
difference specification, PDDMAX, which is specified to be
400 ns over the operating temperature range of -40°C to
125°C.
Delaying the ACPL-38JT turn-on signals by the maximum
propagation delay difference ensures that the minimum
dead time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead time is
equivalent to the difference between the maximum and
minimum propagation delay difference specifications
as shown in Figure 79. The maximum dead time for the
ACPL-38JT is 800 ns (= 400 ns - (-400 ns)) over an operating
temperature range of -40°C to 125°C.
ILED1
VOUT1
Q1 ON
Q1 OFF
Q2 ON
VOUT2
ILED2
Q2 OFF
tPHL MAX
tPLH MIN
PDD* MAX = (tPHL - tPLH) MAX = tPHL MAX - tPLH MIN
*PDD = Propagation Delay Difference
Note: for PDD calculations the propagation delays
Are taken at the same temperature and test conditions.
Figure 78. Minimum LED Skew for Zero Dead Time.
ILED1
VOUT1
VOUT2
Q1 ON
Q1 OFF
Q2 ON
Q2 OFF
ILED2
tPLH MIN
tPHL MAX
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the components under consideration are
typically mounted in close proximity to each other and are
switching identical IGBTs.
tPLH MIN
tPLH MAX
(tPHL - tPLH) MAX
PDD* MAX
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN)
= (tPHL MAX - tPLH MIN) + (tPHL MIN - tPLH MAX)
= PDD* MAX - PDD* MIN
*PDD = Propagation Delay Difference
Note: For Dead Time and PDD calculations all propagation
delays are taken at the same temperature and test conditions.
Figure 79. Waveforms for Dead Time Calculation.
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www.avagotech.com
Avago, Avago Technologies, the A logo and R2Coupler™ are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved.
AV02-2546EN - February 17, 2012