AVAGO ACPL-P340-560E

ACPL-P340 and ACPL-W340
1.0 Amp Output Current IGBT Gate Drive Optocoupler
with Rail-to-Rail Output Voltage in Stretched SO6
Data Sheet
Description
Features
The ACPL-P340/W340 contains an AlGaAs LED, which is
optically coupled to an integrated circuit with a power
output stage. This optocoupler is ideally suited for driving
power IGBTs and MOSFETs used in motor control inverter
applications. The high operating voltage range of the
output stage provides the drive voltages required by gate
controlled devices. The voltage and high peak output
current supplied by this optocoupler make it ideally suited
for direct driving IGBT with ratings up to 1200 V / 50 A. For
IGBTs with higher ratings, this optocoupler can be used to
drive a discrete power stage which drives the IGBT gate.
The ACPL-P340 and ACPL-W340 have the highest insulation voltage of VIORM = 891 Vpeak and VIORM = 1140 Vpeak
respectively in the IEC/ EN/DIN EN 60747-5-2.
 1.0 A maximum peak output current
 0.8 A minimum peak output current
 Rail-to-rail output voltage
 200 ns maximum propagation delay
 100 ns maximum propagation delay difference
 LED current input with hysteresis
 35 kV/s minimum Common Mode Rejection (CMR) at
VCM = 1500 V
 ICC = 3.0 mA maximum supply current
 Under Voltage Lock-Out protection (UVLO) with
hysteresis
 Wide operating VCC Range: 15 to 30 V
Functional Diagram
 Industrial temperature range: -40° C to 105° C
 Safety Approval:
ANODE
1
6
– UL Recognized 3750/5000 VRMS for 1 min.
VCC
– CSA
NC
2
5
– IEC/EN/DIN EN 60747-5-2 VIORM = 891/1140 Vpeak
VOUT
Applications
CATHODE
3
4
 IGBT/MOSFET gate drive
VEE
 AC and Brushless DC motor drives
Note: A 1 F bypass capacitor must be connected between pins VCC and
VEE.
 Renewable energy inverters
 Industrial inverters
 Switching power supplies
Truth Table
LED
VCC – VEE
“POSITIVE GOING”
(i.e., TURN-ON)
VCC – VEE
“NEGATIVE GOING”
(i.e., TURN-OFF)
VO
OFF
ON
ON
ON
0 – 30 V
0 – 12.1 V
12.1 – 13.5 V
13.5 – 30 V
0 – 30 V
0 – 11.1 V
11.1 – 12.4 V
12.4 – 30 V
LOW
LOW
TRANSITION
HIGH
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-P340 is UL Recognized with 3750 VRMS for 1 minute per UL1577.
ACPL-W340 is UL Recognized with 5000 VRMS for 1 minute per UL1577.
Option
Part number
RoHS Compliant
Package
Surface Mount
ACPL-P340
ACPL-W340
-000E
Stretched
SO-6
X
-500E
Tape & Reel
IEC/EN/DIN
EN 60747-5-2
X
-060E
X
-560E
X
Quantity
100 per tube
X
X
1000 per reel
X
100 per tube
X
1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-P340-560E to order product of Stretched SO-6 Surface Mount package in Tape and Reel packaging with IEC/EN/
DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
ACPL-W340-000E to order product of Stretched SO-6 Surface Mount package in Tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Outline Drawings
ACPL-P340 Stretched SO-6 Package (7 mm clearance)
4.580 +– 0.254
0
1.27 (0.050) BSG
0.381 ±0.127
(0.015 ±0.005)
Land Pattern Recommendation
(0.180 +– 0.010
0.000 )
0.76 (0.03)
1.27 (0.05)
10.7
(0.421)
2.16
(0.085)
7.62 (0.300)
1.590 ±0.127
(0.063 ±0.005)
6.81 (0.268)
0.45 (0.018)
45°
3.180 ±0.127
(0.125 ±0.005)
7°
7°
7°
0.20 ±0.10
(0.008 ±0.004)
7°
1 ±0.250
(0.040 ±0.010)
5° NOM.
0.254 ±0.050
(0.010 ±0.002)
Floating Lead Protusions max. 0.25 (0.01)
Dimensions in Millimeters (Inches)
9.7 ±0.250
(0.382 ±0.010)
Lead Coplanarity = 0.1 mm (0.004 Inches)
ACPL-W340 Stretched SO-6 Package (8 mm clearance)
4.580 +– 0.254
0
(0.180 +– 0.010
0.000 )
1.27 (0.050) BSG
0.381 ±0.127
(0.015 ±0.005)
Land Pattern Recommendation
0.76 (0.03)
1
6
2
5
3
4
1.27 (0.05)
(
6.807 +– 0.127
0
0.268 +– 0.005
0.000
7.62 (0.300)
)
1.590 ±0.127
(0.063 ±0.005)
7°
45°
0.45 (0.018)
1.905
(0.075)
12.65
(0.5)
3.180 ±0.127
(0.125 ±0.005)
7°
0.20 ±0.10
(0.008 ±0.004)
0.750 ±0.250
(0.0295 ±0.010)
7°
35° NOM.
11.500 ±0.25
(0.453 ±0.010)
3
7°
0.254 ±0.050
(0.010 ±0.002)
Floating Lead Protusions max. 0.25 (0.01)
Dimensions in Millimeters (Inches)
Lead Coplanarity = 0.1 mm (0.004 Inches)
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non- Halide Flux should be used.
Regulatory Information
The ACPL-P340/W340 is approved by the following organizations:
UL
Recognized under UL 1577, component recognition program up to VISO = 3750 VRMS (ACPL-P340) and VISO = 5000 VRMS
(ACPL-W340) expected prior to product release.
CSA
CSA Component Acceptance Notice #5, File CA 88324
IEC/EN/DIN EN 60747-5-2 (Option 060 Only)
Maximum Working Insulation Voltage VIORM = 891 Vpeak (ACPL-P340) and VIORM = 1140 Vpeak (ACPL-W340)
Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics* (Option 060 – Under Evaluation)
ACPL-P340
Option 060
ACPL-W340
Option 060
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000 Vrms
I – IV
I – IV
I – III
I – III
I – IV
I – IV
I – IV
I – IV
I – III
Climatic Classification
55/100/21
55/100/21
Description
Symbol
Pollution Degree (DIN VDE 0110/1.89)
Unit
2
2
Maximum Working Insulation Voltage
VIORM
891
1140
Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial discharge < 5 pC
VPR
1671
2137
Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial discharge < 5 pC
VPR
1426
1824
Vpeak
Highest Allowable Overvoltage
(Transient Overvoltage tini = 60 sec)
VIOTM
6000
8000
Vpeak
Safety-limiting values – maximum values allowed in the event
of a failure.
Case Temperature
Input Current
Output Power
TS
IS, INPUT
PS, OUTPUT
175
230
600
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V
RS
>109
>109

*
Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/
DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles.
Note:
These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by
means of protective circuits. Surface mount classification is Class A in accordance with CECC 00802.
4
Table 2. Insulation and Safety Related Specifications
Parameter
Symbol
ACPL-P340
ACPL-W340
Units
Conditions
Minimum External Air Gap
(External Clearance)
L(101)
7.0
8.0
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
(External Creepage)
L(102)
8.0
8.0
mm
Measured from input terminals to output
terminals, shortest distance path along body.
0.08
0.08
mm
Through insulation distance conductor to
conductor, usually the straight line distance
thickness between the emitter and detector.
>175
>175
V
DIN IEC 112/VDE 0303 Part 1
IIIa
IIIa
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
Notes:
1. All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting
point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board,
minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance
path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered (the recommended
Land Pattern does not necessarily meet the minimum creepage of the device). There are recommended techniques such as grooves and ribs which
may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending
on factors such as pollution degree and insulation level.
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Note
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
105
°C
Output IC Junction Temperature
TJ
125
°C
Average Input Current
IF(AVG)
25
mA
Peak Transient Input Current
(<1 s pulse width, 300 pps)
IF(TRAN)
1
A
Reverse Input Voltage
VR
5
V
“High” Peak Output Current
IOH(PEAK)
1.0
A
2
1.0
A
2
35
V
500
ns
1
“Low” Peak Output Current
IOL(PEAK)
Total Output Supply Voltage
(VCC - VEE)
Input Current (Rise/Fall Time)
tr(IN) / tf(IN)
Output Voltage
VO(PEAK)
VCC
V
Output IC Power Dissipation
PO
700
mW
3
Total Power Dissipation
PT
745
mW
4
Lead Solder Temperature
260° C for 10 sec., 1.6 mm below seating plane
0
-0.5
Table 4. Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Operating Temperature
TA
-40
105
°C
Output Supply Voltage
(VCC - VEE)
15
30
V
Input Current (ON)
IF(ON)
7
16
mA
Input Voltage (OFF)
VF(OFF)
-3.6
0.8
V
5
Note
Table 5. Electrical Specifications (DC)
Unless otherwise noted, all typical values are at TA = 25° C, VCC - VEE = 30 V, VEE = Ground; all minimum and maximum
specifications are at recommended operating conditions (TA = -40 to 105° C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V,
VEE = Ground, VCC = 15 to 30 V).
Parameter
Symbol
Min.
High Level Peak Output
Current
IOH
Low Level Peak Output
Current
IOL
High Level Output Voltage
VOH
Units
Test Conditions
Fig.
Note
-0.3
A
VO = VCC – 4 V
14
5
-0.8
A
VCC - VO ≤ 15 V
0.3
A
VO = VEE + 2.5 V
0.8
A
VO - VEE ≤ 15 V
V
IO = -100 mA
2, 16
Vcc – 0.3
Typ.
Max.
Vcc – 0.2
6
15
High Level Output Voltage
VOH
Vcc
V
IO = 0 mA, IF = 10 mA
1
Low Level Output Voltage
VOL
0.1
0.2
V
IO = 100 mA
5, 17
High Level Supply Current
ICCH
1.9
3.0
mA
Rg = 10 ,
Cg = 25 nF, IF = 10 mA
4, 5
Low Level Supply Current
ICCL
1.9
3.0
mA
Rg = 10 ,
Cg = 25 nF, VF = 0 V
Threshold Input Current
Low to High
IFLH
1.5
4.0
mA
Rg = 10 ,
Cg = 25 nF, VO > 5 V
6, 7, 8
Threshold Input Voltage
High to Low
VFHL
0.8
Input Forward Voltage
VF
1.2
V
IF = 10 mA
13
Temperature Coefficient
of Input Forward Voltage
VF/TA
mV/°C
IF = 10 mA
Input Reverse Breakdown
Voltage
BVR
V
IR = 100 A
Input Capacitance
CIN
pF
f = 1 MHz, VF = 0 V
V
VO > 5 V, IF = 10 mA
UVLO Threshold
UVLO Hysteresis
6
V
1.55
1.95
-1.7
5
70
VUVLO+
12.1
12.8
13.5
VUVLO-
11.1
11.8
12.4
UVLOHYS
1.0
V
5
7
19
8,9
Table 6. Switching Specifications (AC)
Unless otherwise noted, all typical values are at TA = 25° C, VCC - VEE = 30 V, VEE = Ground; all minimum and maximum
specifications are at recommended operating conditions (TA = -40 to 105° C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V,
VEE = Ground, VCC = 15 to 30 V).
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Propagation Delay Time to
High Output Level
tPLH
50
98
200
ns
Propagation Delay Time to
Low Output Level
tPHL
50
95
200
ns
8, 9,
10, 11,
12, 20
Pulse Width Distortion
PWD
22
70
ns
Rg = 10 , Cg = 25 nF,
f = 20 kHz,
Duty Cycle = 50%,
IF = 7 mA to 16 mA,
VCC = 15 V to 30 V
Propagation Delay Difference
Between Any Two Parts
PDD
(tPHL - tPLH)
100
ns
Rise Time
tR
Fall Time
tF
40
ns
Output High Level Common
Mode Transient Immunity
|CMH|
35
50
kV/s
TA = 25° C, IF = 10 mA,
21
VCC = 30 V, VCM = 1500 V
with split resistors
12, 13
Output Low Level Common
Mode Transient Immunity
|CML|
35
50
kV/s
TA = 25° C, VF = 0 V,
VCC = 30 V, VCM = 1500 V
with split resistors
12, 14
-100
43
10
27, 28
ns
Vcc = 30 V
Note
11
20
Table 7. Package Characteristics
Unless otherwise noted, all typical values are at TA = 25° C; all minimum/maximum specifications are at recommended
operating conditions.
Parameter
Symbol
Device
Min.
Input-Output Momentary
Withstand Voltage*
VISO
ACPL-P340
ACPL-W340
Typ.
Max.
Units
Test Conditions
3750
VRMS
RH < 50%, t = 1 min.,
TA = 25° C
15,17
5000
VRMS
RH < 50%, t = 1 min.,
TA = 25° C
16,17
17
Input-Output Resistance
RI-O
>5012

VI-O = 500 VDC
Input-Output Capacitance
CI-O
0.6
pF
f =1 MHz
LED-to-Ambient Thermal
Resistance
R11
135
°C/W
LED-to-Detector Thermal
Resistance
R12
27
Detector-to-LED Thermal
Resistance
R21
39
Detector-to-Ambient
Thermal Resistance
R22
47
*
7
Fig.
Note
18
The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Avago Technologies Application Note 1074
entitled “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70° C free-air temperature at a rate of 0.3 mA/°C.
2. Maximum pulse width = 10 s. This value is intended to allow for component tolerances for designs with IO peak minimum = 0.8 A. See applications
section for additional details on limiting IOH peak.
3. Derate linearly above 85° C free-air temperature at a rate of 16.9 mW/°C.
4. Derate linearly above 85° C free-air temperature at a rate of 15.3 mW/°C. The maximum LED junction temperature should not exceed 125° C.
5. Maximum pulse width = 50 s.
6. Output is sourced at -0.8 A with a maximum pulse width = 10 s. VCC-VO is measured to ensure 15 V or below.
7. Output is sourced at 0.8 A with a maximum pulse width = 10 s. VO-VEE is measured to ensure 15 V or below.
8. In this test VOH is measured with a DC load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero amps.
9. Maximum pulse width = 1 ms.
10. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device.
11. The difference between tPHL and tPLH between any two ACPL-P340 parts under the same test condition.
12. Pin 2 needs to be connected to LED common.
13. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in the high state (i.e., VO > 15.0 V).
14. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e., VO < 1.0 V).
15. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≤ 4500 VRMS for 1 second (leakage detection
current limit, II-O < 5 A).
16. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≤ 6000 VRMS for 1 second (leakage detection
current limit, II-O < 5 A).
17. Device considered a two-terminal device: pins 1, 2, and 3 shorted together and pins 4, 5 and 6 shorted together.
18. The device was mounted on a high conductivity test board as per JEDEC 51-7.
8
(VOH-VCC) - HIGH OUTPUT VOLTAGE DROP - V
VOH - HIGH OUTPUT RAIL VOLTAGE - V
29.84
IF = 10 mA
IOUT = 0 mA
VCC = 30 V
VEE = 0 V
29.83
29.82
29.81
29.8
29.79
29.78
29.77
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 1. High output rail voltage vs. temperature
-0.05
-0.1
-0.15
-0.2
-0.25
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
2.5
ICC - SUPPLY CURRENT - mA
0.12
0.1
0.08
0.06
VF (OFF) = 0 V
IOUT = 100 mA
VCC = 15 to 30 V
VEE = 0 V
0.04
0.02
2
1.5
1
ICCH
ICCL
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
Figure 3. VOL vs. temperature
Figure 4. ICC vs. temperature
2.5
34
TA = 25° C
VCC = 30 V
VEE = 0 V
29
2
VO - OUTPUT VOLTAGE - V
ICC - SUPPLY CURRENT - mA
IF = 10 mA for ICCH
VF = 0 V for ICCL
VCC = 30 V
VEE = 0 V
0.5
0
0
1.5
1
IF = 10 mA for ICCH
VF = 0 V for ICCL
TA = 25° C
VEE = 0 V
0.5
ICCL
ICCH
24
19
14
9
IFLH ON
IFLH OFF
4
0
-1
15
Figure 5. ICC vs. VCC
9
IF = 7 to 16 mA
IOUT = -100 mA
VCC = 15 to 30 V
VEE = 0 V
Figure 2. VOH vs. temperature
0.14
VOL - OUTPUT LOW VOLTAGE - V
0
20
25
VCC - SUPPLY VOLTAGE - V
30
0
0.5
1
1.5
2
2.5
IFLH - LOW TO HIGH CURRENT THRESHOLD - mA
Figure 6. IFLH hysteresis
3
VCC = 15 to 30 V
VEE = 0 V
TP - PROPAGATION DELAY - ns
IFLH - LOW TO HIGH CURRENT THRESHOLD -mA
120
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
IFLH ON
IFLH OFF
110
100
90
70
15
120
120
110
110
100
90
VCC = 30 V, VEE = 0 V
TA = 25° C
Rg = 10 7, Cg = 25 nF
DUTY CYCLE = 50%
f = 20 kHz
80
70
TPLH
TPHL
8
10
12
14
IF - FORWARD LED CURRENT - mA
16
Figure 9. Propagation delays vs. IF
TP - PROPAGATION DELAY - ns
100
95
90
85
80
IF = 7 mA, TA = 25° C
VCC = 30 V, VEE = 0 V
Cg = 25 nF
DUTY CYCLE = 50%
f = 20 kHz
70
65
TPLH
TPHL
60
10
15
20
25
30
35
40
Rg - SERIES LOAD RESISTANCE - 7
Figure 11. Propagation delay vs. Rg
100
90
IF = 7 mA
VCC = 30 V, VEE = 0 V
Rg = 10 7, Cg = 25 nF
DUTY CYCLE = 50%
f = 20 kHz
80
70
TPLH
TPHL
Figure 10. Propagation delays vs. temperature
105
75
30
60
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
60
6
20
25
VCC - SUPPLY VOLTAGE - V
Figure 8. Propagation delays vs. VCC
TP - PROPAGATION DELAY - ns
TP - PROPAGATION DELAY - ns
Figure 7. IFLH vs. temperature
TP - PROPAGATION DELAY - ns
TPLH
TPHL
60
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
TA - TEMPERATURE - °C
10
IF = 7 mA
TA = 25° C
Rg = 10 7, Cg = 25 nF
DUTY CYCLE = 50%
f = 20 kHz
80
45
50
110
105
100
95
90
85
80
75
70
65
60
IF = 7 mA, TA = 25° C
VCC = 30 V, VEE = 0 V
Rg = 10 7
DUTY CYCLE = 50%
f = 20 kHz
10
15
20
25
30
35
40
Cg - SERIES LOAD CAPACITANCE - nF
Figure 12. Propagation delay vs. Cg
TPLH
TPHL
45
50
IF - FORWARD CURRENT - mA
100
10
1
0.1
1.4
1.45
1.5
1.55
VF - FORWARD VOLTAGE - V
1.6
1.65
Figure 13. Input current vs. forward voltage
4 V Pulsed
1
6
IF = 7 to 16 mA
+
_
1 MF
2
IOH
3
4
Figure 14. IOH test circuit
1
6
1 MF
2
VCC = 15 to 30 V
IOL
3
+
_
5
+
_
4
2.5 V Pulsed
Figure 15. IOL test circuit
11
VCC = 15 to 30 V
+
_
5
1
6
IF = 7 to 16 mA
1 MF
2
5
3
4
VCC = 15 to 30 V
VOH
+
_
100 mA
Figure 16. VOH test circuit
1
6
100 mA
1 MF
2
5
3
4
VCC = 15 to 30 V
VOL
+
_
Figure 17. VOL test circuit
1
6
1 MF
IF
2
5
VO > 5 V
10 7
3
Figure 18. IFLH test circuit
12
4
25 nF
VCC = 15 to 30 V
+
_
1
6
IF = 7 to 16 mA
1 MF
2
5
3
4
VO > 5 V
+
_
VCC
Figure 19. UVLO test circuit
IF = 7 to 16 mA,
20 kHz, 50% Duty Cycle
1
6
2
5
1 MF
VCC = 15 to 30 V
VO
+
_
10 7
3
25 nF
4
Figure 20. tPHL, tPHL, tr and tf test circuit and waveforms
205 7
1
5V
6
1 MF
+
_
2
5
3
4
VO
VCC = 30 V
+
_
+
_
137 7
VCM = 1500 V
Figure 21. CMR test circuit with split resistors network and waveforms
13
10
10mA
mA
Application Information
Product Overview Description
Recommended Application Circuit
The ACPL-P340/W340 is an optically isolated power output
stage capable of driving IGBTs of up to 50 A and 1200 V.
Based on BCDMOS technology, this gate drive optocoupler delivers higher peak output current, better rail-to-rail
output voltage performance and two times faster speed
than the previous generation products.
The recommended application circuit shown in Figure 22
illustrates a typical gate drive implementation using the
ACPL-P340. The following describes about driving IGBT.
However, it is also applicable to MOSFET. Designers will
need to adjust the VCC supply voltage, depending on the
MOSFET or IGBT gate threshold requirements (Recommended VCC = 15 V for IGBT and 12 V for MOSFET).
The high peak output current and short propagation delay
are needed for fast IGBT switching to reduce dead time
and improve system overall efficiency. Rail-to-rail output
voltage ensures that the IGBT’s gate voltage is driven to
the optimum intended level with no power loss across
IGBT. This helps the designer lower the system power
which is suitable for bootstrap power supply operation.
It has very high CMR(common mode rejection) rating
which allows the microcontroller and the IGBT to operate
at very large common mode noise found in industrial
motor drives and other power switching applications. The
input is driven by direct LED current and has a hysteresis
that prevents output oscillation if insufficient LED driving
current is applied. This will eliminates the need of additional Schmitt trigger circuit at the input LED.
The supply bypass capacitors (1 F) provide the large
transient currents necessary during a switching transition.
Because of the transient nature of the charging currents, a
low current (3.0 mA) power supply will be enough to power
the device. The split resistors (in the ratio of 1.5:1) across
the LED will provide a high CMR response by providing a
balanced resistance network across the LED.
The gate resistor RG serves to limit gate charge current
and controls the IGBT collector voltage rise and fall times.
In PC board design, care should be taken to avoid routing
the IGBT collector or emitter traces close to the ACPL-P340
input as this can result in unwanted coupling of transient
signals into ACPL-P340 and degrade performance.
The stretched SO6 package which is up to 50% smaller
than conventional DIP package facilitates smaller more
compact design. These stretched packages are compliant
to many industrial safety standards such as IEC/EN/DIN EN
60747-5-2, UL 1577 and CSA.
R
ANODE
1
NC
2
+
_
R
CATHODE
3
VCC
6
VOUT
1 MF
Rg
VCC = 15 V
+
_
+ HVDC
Q1
+
VCE
_
Q2
+
VCE
_
5
VEE
VEE = 5 V
3-HVDC
AC
+
_
4
-HVDC
Figure 22. Recommended application circuit with split resistors LED drive
14
Rail-to-Rail Output
ACPL-P340 uses a power PMOS to deliver the large current
and pull it to VCC to achieve rail-to-rail output voltage
as shown in Figure 24. This ensures that the IGBT’s gate
voltage is driven to the optimum intended level with no
power loss across IGBT even when an unstable power
supply is used.
Figure 23 shows a typical gate driver’s high current output
stage with 3 bipolar transistors in darlington configuration.
During the output high transition, the output voltage rises
rapidly to within 3 diode drops of VCC. To ensure the VOUT
is at VCC in order to achieve IGBT rated VCE(ON) voltage. The
level of VCC will be need to be raised to beyond VCC+3(VBE)
to account for the diode drops. And to limit the output
voltage to VCC, a pull-down resistor, RPULL-DOWN between
the output and VEE is recommended to sink a static current
while the output is high.
ANODE
1
8
NC
2
7
CATHODE
3
6
NC
4
5
VCC
VOUT
RG
RPULL-DOWN
VEE
Figure 23. Typical gate driver with output stage in darlington configuration
ANODE
1
6
VCC
NC
2
5
VOUT
CATHODE
3
4
VEE
Figure 24. ACPL-P340/W340 with PMOS and NMOS output stage for rail-to-rail output voltage
15
Selecting the Gate Resistor (Rg)
Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT and Rg in Figure 22 can be analyzed as a simple
RC circuit with a voltage supplied by ACPL-P340/W340.
Rg ≥
=
VCC – VEE – VOL
IOLPEAK
15 V + 5 V – 0.6 V
1A
= 19.4   20 
Step 1: Check the ACPL-P340/W340 power dissipation and increase Rg if necessary. The ACPL-P340/W340 total power
dissipation (PT ) is equal to the sum of the emitter power (PE) and the output power (PO).
PT = PE + PO
PE = IF • VF • Duty Cycle
PO = PO(BIAS) + PO(SWITCHING)
= ICC • (VCC-VEE) + ESW(Rg;Cg) • f
Using IF(worst case) = 16 mA, Rg = 20 , Max Duty Cycle = 80%, Cg = 25 nF, f = 25 kHz and TA max = 85° C:
PE = 16 mA • 1.95 V • 0.8 = 25 mW
PO = 3 mA • 20 V + 3.5 J • 25 kHz
= 60 mW + 87.5 mW
= 147.5 mW < 700 mW (PO(MAX) @ 85° C)
The value of 3 mA for ICC in the previous equation is the maximum ICC over the entire operating temperature range.
Since PO is less than PO(MAX), Rg = 20  is alright for the power dissipation.
ESW - ENERGY PER SWITCHING CYCLE - J
3.0E-05
VCC = 30 V
VCC = 20 V
VCC = 15 V
2.5E-05
2.0E-05
1.5E-05
1.0E-05
5.0E-06
0.0E+00
0
5
10
15
20
Rg - Gate Resistance - 7
25
30
Figure 25. Energy Dissipated in the ACPL-P340/W340 for each IGBT switching
cycle.
16
LED Drive Circuit Considerations for High CMR Performance
Figure 26 shows the recommended drive circuit for the
ACPL-P340/W340 that gives optimum common-mode
rejection. The two current setting resistors balance the
common mode impedances at the LED’s anode and
cathode. Common-mode transients can be capacitive
coupled from the LED anode, through CLA (or cathode
through CLC) to the output-side ground causing current
to be shunted away from the LED (which is not wanted
when the LED should be on) or conversely cause current
to be injected into the LED (which is not wanted when the
LED should be off ).
if an imbalance between ILP and ILN results in a transient
IF equal to or greater than the switching threshold of the
optocoupler, the transient “signal” may cause the output
to spike above 1 V, which constitutes a CML failure. The
balanced ILED-setting resistors help equalize the common
mode voltage change at the anode and cathode. The
shunt drive input circuit will also help to achieve high CML
performance by shunting the LED in the off state.
+5 V
Table 8 shows the directions of ILP and ILN depend on the
polarity of the common-mode transient. For transients
occurring when the LED is on, common-mode rejection
(CMH, since the output is at “high” state) depends on
LED current (IF). For conditions where IF is close to the
switching threshold (IFLH), CMH also depends on the
extent to which ILP and ILN balance each other. In other
words, any condition where a common-mode transient
causes a momentary decrease in IF (i.e. when dVCM/dt > 0
and |ILP| > |ILN|, referring to Table 8) will cause a commonmode failure for transients which are fast enough.
Likewise for a common-mode transient that occurs when
the LED is off (i.e. CML, since the output is at “low” state),
VDD = 5.0 V:
R1 = 205 7 ±1%
R2 = 137 7 ±1%
R1/R2 ≈ 1.5
R1 ANODE
1
ILP
CLA
2
6
VCC
5
VOUT
4
VEE
ILN
R2
3
CATHODE
CLC
Figure 26. Recommended high-CMR drive circuit for the ACPL-P340/W340.
Table 8. Common Mode Pulse Polarity and LED current Transients
If |ILP| < |ILN|,
IF is momentarily
If |ILP| > |ILN|,
IF is momentarily
Away from LED cathode
through CLC
Increase
Decrease
Toward LED cathode
through CLC
Decrease
Increase
dVCM/dt
ILP Direction
ILP Direction
Positive (>0)
Away from LED anode
through CLA
Negative(<0)
Toward LED anode
through CLA
17
Dead Time and Propagation Delay Specifications
The ACPL-P340/W340 includes a Propagation Delay Difference (PDD) specification intended to help designers
minimize “dead time” in their power inverter designs. Dead
time is the time period during which both the high and
low side power transistors (Q1 and Q2 in Figure 22) are off.
Any overlap in Q1 and Q2 conduction will result in large
currents flowing through the power devices between the
high and low voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn off of LED1)
so that under worst-case conditions, transistor Q1 has
just turned off when transistor Q2 turns on, as shown in
Figure 27. The amount of delay necessary to achieve this
condition is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is
specified to be 100 ns over the operating temperature
range of 40° C to 105° C.
Figure 27. Minimum LED skew for zero dead time
18
Delaying the LED signal by the maximum propagation
delay difference ensures that the minimum dead time is
zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the difference between the maximum and minimum
propagation delay difference specifications as shown in
Figure 28. The maximum dead time for the ACPL-P340/
W340 is 200 ns (= 100 ns - (-100 ns)) over an operating
temperature range of -40° C to 105C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
Figure 28. Waveforms for dead time
LED Current Input with Hysteresis
The detector has optical receiver input stage with built in
Schmitt trigger to provide logic compatible waveforms,
eliminating the need for additional wave shaping. The
hysteresis (Figure 6) provides differential mode noise
immunity and minimizes the potential for output signal
chatter.
Under Voltage Lockout
The ACPL-P340/W340 Under Voltage Lockout (UVLO)
feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the ACPL-P340/
W340 output low during power-up. IGBTs typically require
gate voltages of 15 V to achieve their rated VCE(ON) voltage.
At gate voltages below 13 V typically, the VCE(ON) voltage
increases dramatically, especially at higher currents. At
very low gate voltages (below 10 V), the IGBT may operate
in the linear region and quickly overheat. The UVLO
function causes the output to be clamped whenever insufficient operating supply (VCC) is applied. Once VCC
exceeds VUVLO+ (the positive-going UVLO threshold), the
UVLO clamp is released to allow the device output to turn
on in response to input signals.
Thermal Model for ACPL-P340/W340 Stretched SO6
Package Optocoupler
Definitions:
R11: Junction to Ambient Thermal Resistance of LED due
to heating of LED
R12: Junction to Ambient Thermal Resistance of LED due
to heating of Detector (Output IC)
R21: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of LED.
R22: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of Detector (Output IC).
P1: Power dissipation of LED (W).
P2: Power dissipation of Detector / Output IC (W).
Ambient Temperature: Junction to Ambient Thermal Resistances were measured approximately 1.25 cm above
optocoupler at ~23° C in still air
Thermal Resistance
°C/W
R11
135
R12
27
R21
39
R22
47
This thermal model assumes that an 6-pin single-channel
plastic package optocoupler is soldered into a 7.62 cm x
7.62 cm printed circuit board (PCB) per JEDEC standards.
The temperature at the LED and Detector junctions of
the optocoupler can be calculated using the equations
below.
T1 = (R11 * P1 + R12 * P2) + Ta
(1)
T2 = (R21 * P1 + R22 * P2) + Ta
(2)
Using the given thermal resistances and thermal model
formula in this datasheet, we can calculate the junction
temperature for both LED and the output detector. Both
junction temperatures should be within the absolute
maximum rating.
For example, given P1 = 25 mW, P2 = 148 mW, Ta = 85° C:
LED junction temperature,
T1 = (R11 * P1 + R12 * P2) + Ta
= (135 * 0.025 + 27 * 0.148) + 85
= 92.4° C
Output IC junction temperature,
T2 = (R21 * P1 + R22 * P2) + Ta
= (39 *0.025 + 47 * 0.148) + 85
= 92.9° C
T1 and T2 should be limited to 125° C based on the board
layout and part placement.
Related Application Noted
T1: Junction temperature of LED (°C).
AN5336 – Gate Drive Optocoupler Basic Design for IGBT
/ MOSFET
T2: Junction temperature of Detector (°C).
AN1043 – Common-Mode Noise: Sources and Solutions
Ta: Ambient temperature.
For product information and a complete list of distributors, please go to our web site:
AV02-0310EN – Plastics Optocouplers Product ESD and
Moisture Sensitivity
www.avagotech.com
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Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved.
AV02-2930EN - November 8, 2011