ACPM-5002-TR1 Multimode PA - UMTS Band2, LTE Band25 and CDMA PCS 3x3mm Power Amplifier Module with Coupler Data Sheet Description Features The ACPM-5002-TR1 is a fully matched 10-pin surface mount module developed to support multimode applications including UMTS Band2 (1850-1910MHz) and CDMA PCS band including BC14 (1850-1915MHz). The ACPM-5002-TR1 meets stringent linearity requirements up to 28.6dBm output power for UMTS Rel.99 and 28.0dBm for CDMA. The 3mmx3mm form factor package is self contained, incorporating 50ohm input and output matching networks. The PA also contains internal DC blocking capacitors for RF input and output ports. Thin Package (0.9mm typ) The ACPM-5002-TR1 features 5th generation of CoolPAM (CoolPAM5) circuit technology which supports 3 power modes – active bypass, mid power and high power modes. The CoolPAM is stage bypass technology enhancing PAE (power added efficiency) at low and medium power range. The active bypass feature is added to CoolPAM5 to enhance the PAE further at low output range and it enables the PA to have exceptionally low quiescent current. It dramatically saves the average power consumption and accordingly extends the talk time of mobiles and prolongs a battery life. A directional coupler is integrated into the module and both coupling and isolation ports are available externally, supporting daisy chain. The integrated coupler has excellent coupler directivity, which minimizes the coupled output power variation or delivered power variation caused by the load mismatch from the antenna. The coupler directivity, or the output power variation into the mismatched load, is critical to the TRP and SAR performance of the mobile phones in real field operations as well as compliance tests for the system specifications. The ACPM-5002 has integrated on-chip Vref and on-module bias switch as the one of the key features of the CoolPAM-5, so an external constant voltage source is not required, eliminating the external LDO regulators and switches from circuit boards of mobile devices. It also makes the PA fully digital-controllable by the Ven pin that simply turns the PA on and off from the digital control logic input from baseband chipsets. All of the digital control input pins Excellent Linearity 3-mode power control with Vbp and Vmode – Bypass / Mid Power Mode / High Power Mode High Efficiency at max output power 10-pin surface mounting package Internal 50ohm matching networks for both RF input and output Integrated coupler – Coupler and Isolation ports for daisy chain Lead-free, RoHS compliant, Green Applications UMTS Band2 LTE Band25 CDMA PCS(BC1) and BC14 Ordering Information Part Number Number of Devices Container ACPM-5002-TR1 1000 178mm (7”) Tape/Reel ACPM-5002-BLK 100 Bulk Description (Cont.) such as the Ven, Vmode and Vbp are fully CMOS compatible and can operate down to the 1.35V logic. The current consumption by digital control pins is negligible. The power amplifier is manufactured on an advanced InGaP HBT (hetero-junction Bipolar Transistor) MMIC (microwave monolithic integrated circuit) technology offering state-of-the-art reliability, temperature stability and ruggedness. Absolute Maximum Ratings No damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. Operation of any single parameter outside these conditions with the remaining parameters set at or below nominal values may result in permanent damage. Description Min. RF Input Power (Pin) Typ. Max. Unit 0 10 dBm DC Supply Voltage (Vcc1, Vcc2) 0 3.4 5.0 V Enable Voltage (Ven) 0 2.6 3.3 V Mode Control Voltage (Vmode) 0 2.6 3.3 V Bypass Control (Vbp) 0 2.6 3.3 V Storage Temperature (Tstg) -55 25 +125 °C Description Min. Typ. Max. Unit DC Supply Voltage (Vcc1, Vcc2) 3.2 3.4 4.2 V Low High 0 1.35 0 2.6 0.5 3.1 V V Low High 0 1.35 0 2.6 0.5 3.1 V V Low High 0 1.35 0 2.6 0.5 3.1 V V UMTS CDMA 1850 1850 1910 1915 MHz MHz UMTS CDMA -20 -30 85 85 °C °C Recommended Operating Condition Enable Voltage (Ven) Mode Control Voltage (Vmode) Bypass Control Voltage (Vbp) Operating Frequency (fo) Ambient Temperature (Ta) 25 25 Operating Logic Table Power Mode Ven Vmode Vbp Pout (Rel99) Pout (HSDPA, HSUPA MPR=0dB) High Power Mode High Low X ~ 28.6 dBm ~ 27.6 dBm Mid Power Mode High High Low ~ 17 dBm ~ 16 dBm Bypass Mode High High High ~ 7 dBm ~ 6 dBm Shut Down Mode Low Low Low – – 2 Electrical Characteristics for WCDMA Mode – Conditions: Vcc = 3.4V, Ven = 2.6V, Ta = 25°C, Zin/Zout = 50ohm – Signal Configuration: 3GPP (DPCCH + 1DPDCH) Up-Link unless specified otherwise. Characteristics Condition Min. Typ. Operating Frequency Range Maximum Output Power (High Power Mode) Gain Power Added Efficiency Total Supply Current 1910 1915 MHz MHz 1850 1850 Rel99 28.6 dBm HSDPA, HSUPA MPR=0dB 27.6 dBm CDMA2000 RC1 28.25 High Power Mode, Pout=28.6dBm 25 dBm 28.5 dB Mid Power Mode, Pout=17dBm 14.5 18.5 dB Bypass Mode, Pout=7dBm 7 11 dB High Power Mode, Pout=28.6dBm 36.7 40.1 % Mid Power Mode, Pout=17dBm 15.3 20.2 % Bypass Mode, Pout=7dBm 6.8 12.3 % High Power Mode, Pout=28.6dBm 530 580 mA Mid Power Mode, Pout=17dBm 72 95 mA 20 mA Mid Power Mode, Pout=13.5dBm 50 Bypass Mode, Pout=7dBm 11 High Power Mode mA 8.5 85 117 mA 150 mA Mid Power Mode 10 20 30 mA Bypass Mode 1 3.1 5 mA High Power Mode Enable Current Unit UMTS CDMA Bypass Mode, Pout=3.5dBm Quiescent Current – - Max. A 5 Mid Power Mode 5 A Bypass Mode 5 A Mid Power Mode 5 A Bypass Mode 5 A Bypass Control Current Bypass 5 Total Current in Power-down mode Ven=0V, Vmode=0V, Vbp=0V UMTS Adjacent Channel Leakage Ratio (ACLR) Pout ≤ (max power – MPR) Mode Control Current Adjacent Channel Power Ratio (ACPR) A 5 A 5 MHz offset -41 -36 dBc 10 MHz offset -54 -46 dBc ±1.25 MHz offset Pout ≤ max power ±1.98 MHz offset -49 -58 -44 -53 dBc dBc LTE to LTE, E-UTRAACLR Pout ≤ (maximum power – MPR) -33 dBc UTRAACLR1 Pout ≤ (maximum power – MPR) -36 dBc UTRAACLR2 Pout ≤ (maximum power – MPR) -39 dBc -35 -42 dBc dBc LTE ACLR Harmonic Suppression Second Third Input VSWR High Power Mode, Pout=28.6dBm -41 -57 2.5:1 Stability (Spurious Output) VSWR 5:1, All phase Rx Band Noise Power (Vcc=4.2V) High Power Mode, Pout=28.6dBm -137 dBm/Hz GPS Band Noise Power (Vcc=4.2V) High Power Mode, Pout=28.6dBm -138 dBm/Hz ISM Band Noise Power (Vcc=4.2V) High Power Mode, Pout=28.6dBm -145 dBm/Hz 3 -60 dBc Electrical Characteristics for WCDMA Mode (Cont.) Rx Band Gain (2110–2170MHz) Where G is gain in Tx band G-2 dB GPS Band Gain (1574-1577MHz) Where G is gain in Tx band G-2.5 dB GLONASS Band Gain (1597-1607MHz) Where G is gain in Tx band G-1.5 dB ISM Band Gain (2400-2483.5MHz) Where G is gain in Tx band G-12 dB Media Band Gain (716-728MHz) Where G is gain in Tx band G-24 dB Phase Discontinuity low power modemid power mode, at Pout=7dBm mid power modehigh power mode, at Pout=17dBm 20 deg 30 deg Ruggedness Pout<28.6dBm, Pin<10dBm, All phase High Power Mode Coupling factor RF Out to CPL port 20 dB Daisy Chain Insertion Loss ISO port to CPL port, Ven=Low 0.25 dB 10:1 VSWR HSDPA Signal configuration used: 3GPP TS 34.121-1 Annex C (normative e): Measurement channels C.10.1 UL reference measurement channel for HSDPA tests Table C.10.1.4: values for transmitter characteristics tests with HS-DPCCH Sub-test 2 (CM=1.0, MPR=0.0) HSUPA signal configuration used: 3GPP TS 34.121-1 Annex C (normative): Measurement channels C.11.1 UL reference measurement channel for E-DCH tests Table C.11.1.3: values for transmitter characteristics tests with HS-DPCCH and E-DCH Sub-test 1 (CM=1.0, MPR=0.0) At 3.2V operation, 0.5dB backoff is allowed for maximum power output. Footprint All dimensions are in millimeter 1.50 0.10 0.125 Pin 1 0.60 0.35 0.35 0.25 0.3 X-Ray Top View 4 0.10 PIN Description Pin # Name Description 1 Vcc1 DC Supply Voltage 2 RFin RF Input 3 Vbp Bypass Control 4 Vmode Mode Control 5 Ven PA Enable 6 CPL Coupling port of Coupler 7 GND Ground 8 ISO Isolation port of Coupler 9 RFOut RF Out 10 Vcc2 DC Supply Voltage Package Dimensions All dimensions ae in millimeter 0.5 Pin 1 Mark 1 10 2 9 3 8 4 7 5 6 3 ± 0.1 3 ± 0.1 0.9 ± 0.1 Marking Specification Pin 1 Mark A5002 Manufacturing Part Number PYYWW Lot Number P Manufacturing Info YY Manufacturing Year WW Work Week QAAAAA Assembly Lot Number QAAAAA 5 Metallization PCB Design Guidelines on 0.5mm pitch Ø 0.3mm 0.45 0.30 The recommended PCB land pattern is shown in figures on the left side. The substrate is coated with solder mask between the I/O and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. 0.60 Stencil Design Guidelines A properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the PCB pads. 0.35 0.475 connected to a inner layer through a via hole for a better isolation between CPL_IN(ISO) and RFout 0.55 Solder Mask Opening 0.65 0.50 0.45 1.30 0.60 0.525 1.50 Solder Paste Stencil Aperture 0.55 0.45 0.35 1.10 0.60 0.475 1.10 6 The recommended stencil layout is shown here. Reducing the stencil opening can potentially generate more voids. On the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the I/O pads or conductive paddle to adjacent I/O pads. Considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100mm(4mils) or 0.127mm(5mils) thick stainless steel which is capable of producing the required fine stencil outline. Evaluation Board Schematic Vcc1 Vcc2 1 Vcc1 RF In C5 2.2uF Vcc2 10 C4 1000pF C6 1000pF RF Out 9 2 RF In ISO Vbp 3 Vbp Vmode C3 100pF Ven C2 100pF C1 100pF ISO 8 4 Vmode GND 7 5 Ven CPL 6 50ohm CPL Evaluation Board Description C5 C7 C4 C6 A5002 PYYWW QAAAAA C3 7 C7 2.2uF RF Out C2 C1 Tape and Reel Information A5002 PYYWW QAAAAA Dimension List Annote Millimeter Annote Millimeter A0 3.40±0.10 P2 2.00±0.05 B0 3.40±0.10 P10 40.00±0.20 K0 1.35±0.10 E 1.75±0.10 D0 1.55±0.05 F 5.50±0.05 D1 1.60±0.10 W 12.00±0.30 P0 4.00±0.10 T 0.30±0.05 P1 8.00±0.10 Tape and Reel Format – 3 mm x 3 mm 8 Reel Drawing BACK VIEW Shading indicates thru slots 18.4 max. 178 +0.4 -0.2 50 min. 25 min wide (ref) Slot for carrier tape insertion for attachment to reel hub (2 places 180° apart) 12.4 +2.0 -0.0 FRONT VIEW 1.5 min. 13.0 ± 0.2 21.0 ± 0.8 Plastic Reel Format (all dimensions are in millimeters) 9 NOTES: 1. Reel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. Avago Technologies part number c. purchase order number d. date code e. quantity of units 2. A certificate of compliance (c of c) shall be issued and accompany each shipment of product. 3. Reel must not be made with or contain ozone depleting materials. 4. All dimensions in millimeters (mm) Handling and Storage ESD (Electrostatic Discharge) Electrostatic discharge occurs naturally in the environment. With the increase in voltage potential, the outlet of neutralization or discharge will be sought. If the acquired discharge route is through a semiconductor device, destructive damage will result. ESD countermeasure methods should be developed and used to control potential ESD damage during handling in a factory environment at each manufacturing site. MSL (Moisture Sensitivity Level) Plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. Avago Technologies follows JEDEC Standard J-STD 020B. Each component and package type is classified for moisture sensitivity by soaking a known dry package at various temperatures and relative humidity, and times. After soak, the components are subjected to three consecutive simulated reflows. The out of bag exposure time maximum limits are determined by the classification test describe below which corresponds to a MSL classification level 6 to 1 according to the JEDEC standard IPC/JEDEC J-STD-020B and J-STD-033. ACPM-5002-TR1 is MSL3. Thus, according to the J-STD-033 p.11 the maximum Manufacturers Exposure Time (MET) for this part is 168 hours. After this time period, the part would need to be removed from the reel, de-taped and then re-baked. MSL classification reflow temperature for the ACPM-5002-TR1 is targeted at 260°C+0/-5°C. Figure and table on next page show typical SMT profile for maximum temperature of 260 +0/-5°C. Moisture Classification Level and Floor Life MSL Level Floor Life (out of bag) at factory ambient =< 30°C/60% RH or as stated 1 Unlimited at =< 30°C/85% RH 2 1 year 2a 4 weeks 3 168 hours 4 72 hours 5 48 hours 5a 24 hours 6 Mandatory bake before use. After bake, must be reflowed within the time limit specified on the label Note : 1. The MSL Level is marked on the MSL Label on each shipping bag. 10 Reflow Profile Recommendations tp Tp Critical Zone TL to Tp Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C Typical SMT Reflow Profile for Maximum Temperature = 260 +0/-5°C Profile Feature Sn-Pb Solder Pb-Free Solder Average ramp-up rate (TL to TP) 3°C/sec max 3°C/sec max Preheat – Temperature Min (Tsmin) – Temperature Max (Tsmax) – Time (min to max) (ts) 100°C 150°C 60-120 sec 150°C 200°C 60-120 sec Tsmax to TL – Ramp-up Rate Time maintained above: – Temperature (TL) – Time (TL) 3°C/sec max 183°C 60-150 sec 217°C 60-150 sec Peak temperature (Tp) 240 +0/-5°C 260 +0/-5°C Time within 5°C of actual Peak Temperature (tp) 10-30 sec 20-40 sec Ramp-down Rate 6°C/sec max 6°C/sec max Time 25°C to Peak Temperature 6 min max. 8 min max. 11 Storage Condition Baking of Populated Boards Packages described in this document must be stored in sealed moisture barrier, antistatic bags. Shelf life in a sealed moisture barrier bag is 12 months at <40°C and 90% relative humidity (RH) J-STD-033 p.7. Some SMD packages and board materials are not able to withstand long duration bakes at 125°C. Examples of this are some FR-4 materials, which cannot withstand a 24 hr bake at 125°C. Batteries and electrolytic capacitors are also temperature sensitive. With component and board temperature restrictions in mind, choose a bake temperature from Table 4-1 in J-STD 033; then determine the appropriate bake duration based on the component to be removed. For additional considerations see IPC-7711 and IPC-7721. Out-of-Bag Time Duration After unpacking the device must be soldered to the PCB within 168 hours as listed in the J-STD-020B p.11 with factory conditions <30°C and 60% RH. Baking It is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. Baking must be done if at least one of the conditions above have not been satisfied. The baking conditions are 125°C for 12 hours J-STD-033 p.8. CAUTION Tape and reel materials typically cannot be baked at the temperature described above. If out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (See moisture sensitive warning label on each shipping bag for information of baking). Board Rework Component Removal, Rework and Remount If a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200°C. This method will minimize moisture related component damage. If any component temperature exceeds 200°C, the board must be baked dry per 4-2 prior to rework and/or component removal. Component temperatures shall be measured at the top center of the package body. Any SMD packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. Removal for Failure Analysis Not following the above requirements may cause moisture/reflow damage that could hinder or completely prevent the determination of the original failure mechanism. 12 Derating due to Factory Environmental Conditions Factory floor life exposures for SMD packages removed from the dry bags will be a function of the ambient environmental conditions. A safe, yet conservative, handling approach is to expose the SMD packages only up to the maximum time limits for each moisture sensitivity level as shown in next table. This approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30°C/60% RH. A solution for addressing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials ref. JESD22-A120). Recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. Table on next page lists equivalent derated floor lives for humidities ranging from 20-90% RH for three temperature, 20°C, 25°C, and 30°C. Table on next page is applicable to SMDs molded with novolac, biphenyl or multifunctional epoxy mold compounds. The following assumptions were used in calculating this table: 1. Activation Energy for diffusion = 0.35eV (smallest known value). 2. For ≤60% RH, use Diffusivity = 0.121exp ( -0.35eV/kT) mm2/s (this used smallest known Diffusivity @ 30°C). 3. For >60% RH, use Diffusivity = 1.320exp ( -0.35eV/kT) mm2/s (this used largest known Diffusivity @ 30°C). Recommended Equivalent Total Floor Life (days) @ 20°C, 25°C & 30°C, 35°C For ICs with Novolac, Biphenyl and Multifunctional Epoxies (Reflow at same temperature at which the component was classified) Maximum Percent Relative Humidity Maximum Percent Relative Humidity Package Type and Body Thickness Body Thickness ≥3.1 mm Including PQFPs >84 pin, PLCCs (square) All MQFPs or All BGAs ≥1 mm Moisture Sensitivity Level Level 2a Level 3 Level 4 Level 5 Level 5a Body 2.1 mm ≤ Thickness <3.1 mm including PLCCs (rectangular) 18-32 pin SOICs (wide body) SOICs ≥20 pins, PQFPs ≤80 pins Level 2a Level 3 Level 4 Level 5 Level 5a Body Thickness <2.1 mm including SOICs <18 pin All TQFPs, TSOPs or All BGAs <1 mm body thickness Level 2a Level 3 Level 4 Level 5 Level 5a 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 3 5 6 8 2 4 5 7 1 2 3 5 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 5 7 9 11 3 4 5 6 1 2 2 3 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 7 10 13 18 94 124 167 231 8 10 13 17 3 4 5 7 2 3 5 7 1 1 2 4 ∞ ∞ ∞ ∞ 12 19 25 32 4 5 7 9 2 3 4 5 1 1 2 2 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 7 13 18 26 2 3 5 6 44 60 78 103 7 9 11 14 3 4 5 7 2 3 4 6 1 1 2 3 ∞ ∞ ∞ ∞ 9 12 15 19 3 4 5 7 2 3 3 5 1 1 2 2 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 7 9 12 17 3 5 6 8 1 2 3 4 32 41 53 69 6 8 10 13 2 4 5 7 2 2 4 5 1 1 2 3 58 86 148 ∞ 7 9 12 15 3 4 5 6 2 2 3 4 1 1 2 2 ∞ ∞ ∞ ∞ ∞ ∞ ∞ ∞ 4 5 7 9 2 3 4 6 1 1 2 3 26 33 42 57 6 7 9 12 2 3 5 7 1 2 3 5 1 1 2 3 30 39 51 69 6 8 10 13 2 3 4 6 2 2 3 4 1 1 2 2 ∞ ∞ ∞ ∞ 8 11 14 20 3 4 5 7 2 2 3 5 1 1 2 2 16 28 36 47 6 7 9 12 2 3 4 6 1 2 3 4 1 1 2 2 22 28 37 49 5 7 9 12 2 3 4 5 1 2 3 4 1 1 2 2 17 28 ∞ ∞ 5 7 10 13 2 3 4 6 1 2 3 4 1 1 2 2 7 10 14 19 4 5 7 10 2 3 3 5 1 2 2 3 1 1 1 2 3 4 6 8 2 3 5 7 1 2 3 4 1 1 2 3 1 1 1 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 2 2 1 1 1 2 5 7 10 13 3 4 6 8 1 2 3 4 1 1 2 3 1 1 1 2 2 3 4 5 2 2 3 5 1 2 2 3 1 1 1 3 0.5 0.5 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2 0.5 1 1 2 4 6 8 10 3 4 5 7 1 2 3 4 1 1 2 3 1 1 1 2 1 2 3 4 1 2 3 4 1 1 2 3 1 1 1 2 0.5 0.5 1 1 0.5 1 1 1 0.5 1 1 1 0.5 1 1 1 0.5 1 1 1 0.5 0.5 1 1 For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. AV02-2477EN - April 27, 2012 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C 35°C 30°C 25°C 20°C