AMMP-6120 8-24 GHz x2 Frequency Multiplier Data Sheet Description Features Avago Technologies’ AMMP-6120 is an easy-to-use integrated frequency multiplier (x2) in a surface mount package designed for commercial communication systems. The MMIC takes a 4 to 12 GHz input signal and doubles it to 8 to 24 GHz. It has integrated amplification, matching, harmonic suppression, and bias networks. The input/output are matched to 50 Ω and fully DC blocked. The MMIC is fabricated using PHEMT technology. • 5x5mm Surface Mount Package The backside of the package is both RF and DC ground. This helps simplify the assembly process and reduces assembly related performance variations and costs. The surface mount package allows elimination of “chip & wire” assembly for lower cost. This MMIC is a cost effective alternative to hybrid (discrete-FET), passive, and diode doublers that require complex tuning and assembly processes. Package Diagram RF IN • Frequency Range : 8-24 GHz output (Useable to 26 GHz) • Broad input power range: -11 to +5 dBm • Output Power : +16 to +18 dBm • Harmonic Suppression : 20 dBc (Fundamental) • DC requirements : -1.4V and 5V, 112 mA @ Pin= +3dBm Applications • Microwave Radio systems • Satellite VSAT and DBS systems • 802.16 & 802.20 WiMax BWA systems • WLL and MMDS loops Functional Block Diagram Vd Vg NC 1 2 3 8 Vd 1 4 7 6 5 NC NC NC RF OUT Vg 2 3 4 RFout X2 RFin 8 7 6 5 top view package base: RF and DC GND Pin 1 2 3 4 5 6 7 8 Function Vd Vg RF Out RF In Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) = 40V ESD Human Body Model (Class 1A) = 250V Refer to Avago Application Note A004R: Electrostatic Discharge Damage and Control. Note: MSL Rating = Level 2A Electrical Specifications 1. Small/Large -signal data measured in a fully de-embedded test fixture form TA = 25°C. 2. Pre-assembly into package performance verified 100% on-wafer. 3. This final package part performance is verified by a functional test correlated to actual performance at one or more frequencies. 4. Specifications are derived from measurements in a 50 Ω test environment. Aspects of the amplifier performance may be improved over a more narrow bandwidth by application of additional conjugate, linearity, or low noise (Гopt) matching. Table 1. RF Electrical Characteristics TA=25°C, Vd=50V, Vg=-1.4V, Idq=85mA, Zin=Zout=50 Ω Parameter Min Typ. Output Power, Pout 13 16 dBm Input Power at 1dB Gain Compression, IP-1dB 2 dBm Input Return Loss, RLin -15 dB -10 dB 25 dBc 3rd Harmonic Suppression, Sup3 25 dBc 4th Harmonic Suppression, Sup4 35 dBc Single Side Band Phase Noise, SSBPN (@100kHz offset, fout=15.6GHz) -140 dBc Output Return Loss, RLout Fundamental Suppresion, Sup 18 Max Unit Table 2. Recommended Operating Range 1. Ambient operational temperature TA = 25°C unless otherwise noted. 2. Channel-to-backside Thermal Resistance (Tchannel (Tc) = 34°C) as measured using infrared microscopy. Thermal Resistance at backside temperature (Tb) = 25°C calculated from measured data. Description Min. Typical Max. Unit Comments Drain Supply Current, Id 85 110 mA Vd = 5V, Under any RF power drive and temperature Gate Current, Ig 9 uA Table 3. Thermal Properties Parameter Test Conditions Value Thermal Resistance, qch-b Channel-to-backside Thermal Resistance Tchannel(Tc)=34°C Thermal Resistance at backside temperature Tb=25°C qch-b = 34 °C/W Absolute Minimum and Maximum Ratings Table 4. Minimum and Maximum Ratings Description Min. Drain Supply Voltage, Vd Gate Supply Voltage, Vg Unit 7 V +0.5 V Drain Current, Idq 120 mA CW Input Power, Pin 15 dBm Channel Temperature, Tch +150 °C +150 °C +300 °C Storage Temperature , Tstg Maximum Assembly Temperature, Tmax -3.0 Max. -65 Notes: 1. Operation in excess of any one of these conditions may result in permanent damage to this device. 2 Comments 60 second maximum AMMP-6120 Typical Performances 20 15 10 5 0 -5 -10 -15 -20 -25 -30 2H 1H 3H 4H 8 10 12 14 16 Output Power (dBm) Output Power (dBm) (TA = 25°C,Zin = Zout = 50 Ω, Vd=5V, Vg=-1.4V) 18 20 22 24 26 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -40°C [2H] +25°C [2H] +85°C [2H] -40°C [1H] +25°C [1H] +85°C [1H] 8 10 12 Output Frequency (GHz) Figure 1. Output Power vs. Output Freq. @ Pin=+3dBm 16 Suppression [1H] (dBc) Output Power [2H] (dBm) 15 17 15 14 13 Pin=-2dBm Pin= 0dBm Pin=+2dBm Pin=+4dBm 12 11 8 10 12 14 16 18 20 Output Frequency (GHz) 22 24 20 25 30 Pin=-2dBm Pin= 0dBm Pin=+2dBm Pin=+4dBm 35 40 26 Figure 3. Output Power [2H] vs. Output Freq. at variable Pin 8 0 160 -5 150 -10 -15 -20 S11 S22 -25 -30 4 6 8 10 12 14 16 18 Frequncy (GHz) Figure 5. Input and Output Return Loss 20 10 12 14 16 18 20 Output Frequency [GHz] 22 24 26 9 11 Figure 4. Fundamental Suppression at variable Pin Total Drain Current [Id] (mA) I/P & O/P Return Loss (dB) 26 10 18 3 24 Figure 2. Output Power vs. Output Freq. over temp @ Pin=+3dBm 19 10 14 16 18 20 22 Output Frequency (GHz) 22 24 26 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 140 130 120 110 100 90 80 -11 -9 -7 -5 -3 -1 1 3 5 Input Power [1H] (dBm) Figure 6. Variation of total drain current with input power 7 20 18 16 20 Fout=8GHz Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 25 Suppression [1H] (dBc) Output Power [2H] (dBm) 14 12 10 8 6 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 4 2 0 -11 -9 -7 -5 -3 -1 1 3 Input Power [1H] (dBm) 5 7 9 18 35 Fout=8GHz 40 45 -11 11 Figure 7. 2H Output Power Vs Input Power @ Fout=8GHz 20 30 -9 25 Suppression [1H] (dBc) Output Power [2H] (dBm) 12 10 8 6 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 4 2 -5 -3 -1 1 3 Input Power [1H] (dBm) 5 7 9 12 Suppression [1H] (dBc) Output Power [2H] (dBm) 9 11 9 11 35 Fout=10GHz 40 -9 -7 -5 -3 -1 1 3 Input Power [1H] (dBm) 5 7 10 8 6 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V -9 -7 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 15 Fout=14GHz -5 -3 -1 1 3 Input Power [1H] (dBm) 5 Figure 11. 2H Output Power Vs Input Power @ Fout=14GHz 4 11 10 18 4 2 0 -11 9 Figure 10. Fundamental Supp. Vs Input Power @ Fout=10GHz 20 14 7 30 45 -11 11 Figure 9. 2H Output Power Vs Input Power @ Fout=10GHz 16 5 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 14 -7 -3 -1 1 3 Input Power [1H] (dBm) 20 Fout=10GHz -9 -5 Figure 8. Fundamental Supp. Vs Input Power @ Fout=8GHz 16 0 -11 -7 7 9 11 20 25 30 Fout=14GHz 35 -11 -9 -7 -5 -3 -1 1 3 Input Power [1H] (dBm) 5 7 Figure 12. Fundamental Supp. Vs Input Power @ Fout=14GHz 20 10 18 16 12 Suppression [1H] (dBc) Output Power [2H] (dBm) 14 Fout=16GHz 10 8 6 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 4 2 0 -11 -9 -7 -5 -3 -1 1 3 Input Power [1H] (dBm) 5 7 9 14 Suppression [1H] (dBc) Output Power [2H] (dBm) -9 -7 -5 -3 -1 1 3 Input Power [1H] (dBm) 5 7 9 11 9 11 9 11 Fout=20GHz 10 16 12 10 8 Fout=20GHz 6 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 4 2 -9 -7 -5 -3 -1 1 3 Input Power [1H] (dBm) 5 7 9 11 Figure 15. 2H Output Power Vs Input Power @ Fout=20GHz 15 20 25 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 30 35 -11 5 18 16 10 14 15 Suppression [1H] (dBc) 12 10 8 Fout=22GHz 6 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 4 2 -9 -7 -5 -3 -1 1 3 Input Power [1H] (dBm) 5 Figure 17. 2H Output Power Vs Input Power @ Fout=22GHz -9 -7 -5 -3 -1 1 3 Input Power [1H] (dBm) 5 7 Figure 16. Fundamental Supp. Vs Input Power @ Fout=20GHz 20 0 -11 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 30 5 18 Output Power [2H] (dBm) 25 Figure 14. Fundamental Supp. Vs Input Power @ Fout=16GHz 20 5 20 35 -11 11 Figure 13. 2H Output Power Vs Input Power @ Fout=16GHz 0 -11 Fout=16GH 15 7 9 11 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 20 25 Fout=22GHz 30 35 -11 -9 -7 -5 -3 -1 1 3 Input Power [1H] (dBm) 5 7 Figure 18. Fundamental Supp. Vs Input Power @ Fout=22GHz 5 Fout=26GHz Fout=26GHz Vd=4.5V, Vg=-1.2V 10 Suppression [1H] (-dBc) Output Power [2H] (dBm) 20 18 16 14 12 10 8 6 4 2 0 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V -11 -9 -7 -5 -3 -1 1 3 5 7 9 11 15 20 Vg=-1.2V, Vd=4.5V Vg=-1.2V, Vd=5.0V Vg=-1.4V, Vd=4.5V Vg=-1.4V, Vd=5.0V 25 30 35 -11 -9 -7 -5 Input Power [1H] (dBm) SSB Phase Noise (dBc/Hz) Figure 19 . 2H Output Power Vs Input Power @ Fout=26GHz -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 1.E+02 -3 -1 1 3 Input Power [1H] (dBm) 5 7 9 11 Figure 20 . Fundamental Supp. Vs Input Power @ Fout=26GHz Fout=15.6GHz F1 M/N @ fo Active Balun S Filter @ 2fo Amp F2 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Offset Frequency [Hz] Figure 21. SSB Phase Noise of frequency doubler (Pin=+2dBm, fout=15.6GHz) Figure 22. Top Level Schematic of Frequency doubler Biasing and Operation The frequency doubler MMIC consists of a balun. The outputs of this balun feed the gates of balanced FETs and the drains are connected to form the single-ended output. This results in fundamental frequency & odd harmonics cancellation. The even harmonic drain currents are in phase and thus add in phase. The input matching network (M/N) is designed to provide good match at fundamental frequencies and produces high impedance mismatch to higher harmonics. The AMMP-6120 is biased with a single positive drain supply Vdd and a single negative gate supply using separate bypass capacitors. It is normally biased with the drain supply connected to Vd and the gate supply connected to Vg. For most applications it is recommended to use a Vg =-1.2V to -1.4V and Vd=4.5V to 5.0V. The RF input and output ports are AC coupled thus no DC voltage is present at either port. The ground connection is made via the package base.” 6 The AMMP-6120 performance changes with Drain Voltage (Vd) and Gate bias (Vg) as shown in the previous graphs. Improvements in output power or fundamental suppression performance are possible by optimizing the Vg from -1.2V to -1.4V and/or Vd from 4.5 to 5.0V. A simplified schematic of the frequency multiplier is shown in figure 22. The active balun circuit and the output amplifier of the circuit are self biased. The Vg negative bias (below pinch off ) is only applied to FETs ‘F1’ and ‘F2’. FETs ‘F1’ and ‘F2’ have no significant contribution to total drain current therefore Vg cannot be used to set drain current. It should only be used to optimize the output power and fundamental & higher harmonics suppression of the doubler. Refer to the Absolute Maximum Ratings table for allowed DC and thermal conditions. Typical Scattering Parameters Please refer to <http://www.avagotech.com> for typical scattering parameters data. Package Dimension, PCB Layout and Tape and Reel information Please refer to Avago Technologies Application Note 5520, AMxP-xxxx production Assembly Process (Land Pattern A). AMMP-6120 Part Number Ordering Information Part Number Devices Per Container Container AMMP-6120-BLK 10 Antistatic bag AMMP-6120-TR1 100 7” Reel AMMP-6120-TR2 500 7” Reel For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes AV01-0119EN AV02-0441EN - July 8, 2013