AZ100LVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable www.azmicrotek.com FEATURES DESCRIPTION • Minimizes External Components • High Bandwidth for ≥1GHz • Similar Operation as AZ100LVEL16VR except with selectable data input pairs • -147 dBc/Hz Typical Noise Floor The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain output buffer including an enable. Selectable data input pairs permit switching between two different oscillator frequencies. The QHG/Q ¯ HG outputs have a voltage gain several times greater than the Q/Q ¯ outputs. An enable allows continuous oscillator operation by only controlling the QHG /Q ¯ HG outputs. The AZ100LVEL16VV also provides a reference voltage (VBB) with internal biasing resistors to each input to minimize external components. BLOCK DIAGRAM APPLICATIONS • • Dual frequency oscillators Crystal or saw oscillators that require minimal external components. PACKAGE AVAILABILITY • MLP16 o Green/RoHS Compliant/Pb-Free Order Number Package Marking AZ100LVEL16VRL1 MLP16 AZM+16K <Date Code>2 1 Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in 2 See www.azmicrotek.com for date code format www.azmicrotek.com +1-480-962-5881 Request a Sample 1630 S Stapley Dr, Suite 127 Mesa, AZ 85204 USA May 2012, Rev 2.0 Arizona Microtek, Inc. AZ100LVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description AZ100LVEL16VTNA+ Pin Name Type Function 1 D0 Input Data Input 2 D0 ¯¯ Input Inverting Data Input 3 D1 Input Data Input 4 D1 ¯¯ Input Inverting Data Input 5 VBB Output Reference Voltage 6 NC - N/A 7 VEE Power Negative Supply 8 NC - N/A 9 EN Input Output Enable 10 Q ¯ HG Output High Gain Inverting PECL Output 11 QHG Output High Gain PECL Output 12 SEL Input Data Input Select 13 VCC Power Positive Supply 14 NC - N/A 15 Q Output PECL Output 16 Q ¯ Output Inverting PECL Output D0 1 D0 2 D1 3 D1 4 Q Q NC VCC 16 15 14 13 12 SEL Leave Pad Open or Connect to VEE 11 QHG 10 QHG 9 5 6 7 8 VBB NC VEE NC EN Figure 1 - Pin Configuration www.azmicrotek.com +1-480-962-5881 Request a Sample 2 May 2012, Rev 2.0 Arizona Microtek, Inc. AZ100LVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable ENGINEERING NOTES The data inputs are selected with the select pin (SEL). When SEL is LOW or open (NC) data from the D0/D0 ¯¯ is selected. When SEL is HIGH data from the D1/D1 ¯¯ is selected. See Table 2 for data selection. The enable pin (EN) works with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets of outputs. When EN is LOW, the QHG/Q ¯ HG outputs will be forced LOW/HIGH respectively, while input data will continue to be passed to the Q/Q ¯ outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply swing CMOS type logic signal. See table 2 for enable operation. Internal Input biasing is accomplished with a VBB and separate 470Ω bias resistors connecting each data input to VBB . The VBB pin supports 1.5mA sink/source current and should be bypassed to ground with a 0.01µF capacitor. Each Q/Q ¯ output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase pull-down current of the Q/Q ¯ to a maximum of 25mA each (includes a 4 mA on-chip current source). NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established. Table 2 - Truth Table EN CS-SEL Q Q ¯ QHG Q ¯ HG High/Open High/Open Low Low Low/Open High Low/Open High D0/D0 ¯¯ D1/D1 ¯¯ D0/D0 ¯¯ D1/D1 ¯¯ D0/D0 ¯¯ D1/D1 ¯¯ D0/D0 ¯¯ D1/D1 ¯¯ D0/D0 ¯¯ D1/D1 ¯¯ Low Low D0/D0 ¯¯ D1/D1 ¯¯ High High D0 D1 EN SEL Q Q QHG QHG Figure 2 - Timing Diagram www.azmicrotek.com +1-480-962-5881 Request a Sample 3 May 2012, Rev 2.0 Arizona Microtek, Inc. AZ100LVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable 0.00 0.95 -5.00 0.9 -10.00 0.85 -15.00 0.8 -20.00 0.75 -25.00 0.7 Phase Magnitude 1 S11 MAG S11 PHASE -30.00 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 Frequency (MHz) 0.02 250.00 0.0175 225.00 0.015 200.00 0.0125 175.00 0.01 150.00 0.0075 125.00 0.005 100.00 0.0025 75.00 Phase Magnitude Figure 3 - S11 S12 MAG S12 PHASE 50.00 0 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 Frequency (MHz) Figure 4 - S12 www.azmicrotek.com +1-480-962-5881 Request a Sample 4 May 2012, Rev 2.0 AZ100LVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable 30 200.00 25 150.00 20 100.00 15 50.00 10 Phase Magnitude Arizona Microtek, Inc. S21 MAG S21 PHASE 0.00 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 Frequency (MHz) 0.8 30.00 0.7 25.00 0.6 20.00 0.5 15.00 0.4 10.00 0.3 5.00 Phase Magnitude Figure 5 – S21 S22 MAG S22 PHASE 0.00 0.2 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 Frequency (MHz) Figure 6 – S22 www.azmicrotek.com +1-480-962-5881 Request a Sample 5 May 2012, Rev 2.0 Arizona Microtek, Inc. AZ100LVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable PERFORMANCE DATA Table 3 – Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol Characteristic Condition Rating Unit VCC PECL Power Supply VEE = 0V 0 to + 6.0 V VI PECL Input Voltage VEE = 0V 0 to + 6.0 V VD/D¯ D/D ¯ Input Voltage Referenced to VBB ±0.75 V Continuous Q/Q ¯ 25 Surge Q/Q ¯ 50 Continuous QHG/Q ¯ HG 50 Surge QHG/Q ¯ HG 100 IOUT Output Current mA TA Operating Temperature Range - -40 to +85 °C TSTG Storage Temperature Range - -65 to +150 °C ESDHBM Human Body Model Electro Static Discharge - 2500 V ESDMM Machine Model Electro Static Discharge - 200 V ESDCDM Charged Device Model Electro Static Discharge - 2000 V Table 4 - 100K ECL DC Characteristics 100K ECL DC Characteristics (VEE = -3.0V to -5.5V, VCC = GND) -40°C Symbol Characteristic VOH VOL Output LOW Voltage VBB VIH VIL 1. 0°C 25°C 85°C Unit Min Max Min Max Min Max Min Max Output HIGH Voltage1 -1045 -835 -1025 -835 -1025 -835 -1025 -835 mV 1 -1925 -1555 -1900 -1620 -1900 -1620 -1900 -1620 mV Reference Voltage -1390 -1250 -1390 -1250 -1390 -1250 -1390 -1250 mV Input HIGH Voltage D/D ¯ -1165 -740 -1165 -740 -1165 -740 -1165 -740 mV Input HIGH Voltage EN, SEL -1165 VCC -1165 VCC -1165 VCC -1165 VCC mV Input LOW Voltage D/D ¯ -1900 -1475 -1900 -1475 -1900 -1475 -1900 -1475 mV Input LOW Voltage EN, SEL VEE -1475 VEE -1475 VEE -1475 VEE -1475 mV 150 µA IIH Input HIGH Current EN IIL Input LOW Current EN IEE 1 Power Supply Current 150 150 -100 -100 47 150 -100 47 -100 47 µA 51 mA Specified with Q/Q ¯ open and each QHG/Q ¯ HG output terminated through a 50Ω resistor to VCC-2V. www.azmicrotek.com +1-480-962-5881 Request a Sample 6 May 2012, Rev 2.0 Arizona Microtek, Inc. AZ100LVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable Table 5 - 100K LVPECL DC Characteristics 100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V) -40°C Symbol Characteristic VOH VOL Output LOW Voltage VBB Reference Voltage1 VIL 1. 2. 3. 25°C 85°C Unit Min Max Min Max Min Max Min Max Output HIGH Voltage1,2 2255 2465 2275 2465 2275 2465 2275 2465 mV 1,2 1375 1745 1400 1680 1400 1680 1400 1680 mV 1910 2050 1910 2050 1910 2050 1910 2050 mV 2135 2560 2135 2560 2135 2560 2135 2560 mV Input HIGH Voltage EN, SEL 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV Input LOW Voltage D/D ¯1 1400 1825 1400 1825 1400 1825 1400 1825 mV 1 mV 1 VIH 0°C Input HIGH Voltage D/D ¯ 1 Input LOW Voltage EN, SEL IIH Input HIGH Current EN IIL 3 Input LOW Current EN IEE Power Supply Current VEE 1825 1 VEE 1825 150 1 VEE 1825 150 -400 1 1825 150 -400 150 -400 47 VEE µA -400 47 µA 47 51 mA For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value. ¯ HG output terminated through a 50Ω resistor to VCC-2V. Specified with Q/Q ¯ open and each QHG/Q Specified with EN and SEL forced to VEE. Table 6 - 100K PECL DC Characteristics 100K PECL DC Characteristics (VEE = GND, VCC = +5.0V) Symbol Characteristic VOH VOL VBB -40°C 1. 2. 3. 85°C Unit Max Min Max Min Max Min Max Output HIGH Voltage1,2 3955 4165 3975 4165 3975 4165 3975 4165 mV Output LOW Voltage1,2 3075 3445 3100 3380 3100 3380 3100 3380 mV 3610 3750 3610 3750 3610 3750 3610 3750 mV 3835 4260 3835 4260 3835 4260 3835 4260 mV 2000 VCC 2000 VCC 2000 VCC 2000 VCC mV 3100 3525 3100 3525 3100 3525 3100 3525 mV 1 mV Reference Voltage 1 Input HIGH Voltage D/D ¯ 1 Input HIGH Voltage EN, SEL 1 VIL 25°C Min 1 VIH 0°C Input LOW Voltage D/D ¯ Input LOW Voltage EN, SEL IIH Input HIGH Current EN IIL 3 Input LOW Current EN IEE Power Supply Current VEE 3525 1 VEE 150 3525 1 VEE 150 -1000 -1000 47 3525 1 VEE 150 -1000 47 3525 150 -1000 47 µA µA 51 mA For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value. ¯ HG output terminated through a 50Ω resistor to VCC-2V. Specified with Q/Q ¯ open and each QHG/Q Specified with EN and SEL forced to VEE. www.azmicrotek.com +1-480-962-5881 Request a Sample 7 May 2012, Rev 2.0 Arizona Microtek, Inc. AZ100LVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable Table 7 - AC Characteristics AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V) Symbol -40°C Characteristic Min Typ 0°C Max Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit Propagation Delay tPLH/tPHL D to Q/Q ¯1 400 400 400 430 ps 2 550 550 550 630 ps 20 ps D to QHG/Q ¯ HG tSKEW 3 Duty Cycle Skew 5 20 5 20 5 20 5 4 Input Swing Vpp (AC) tr/tf 1. 2. 3. Differential 80 1000 80 1000 80 1000 80 1000 mV Single Ended 150 2000 150 2000 150 2000 150 2000 mV 260 100 260 100 260 100 260 ps Output Rise/Fall1,2 (20%-80%) 100 Specified with each output terminated through a 50Ω resistor to VCC-2V. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. VPP is the minimum peak-to-peak input swing for which AC parameters guaranteed. The device has a voltage gain of ≈20 to Q/Q ¯ ¯ HG outputs. outputs and a voltage gain of ≈100 to QHG/Q www.azmicrotek.com +1-480-962-5881 Request a Sample 8 May 2012, Rev 2.0 Arizona Microtek, Inc. AZ100LVEL16VV Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable PACKAGE DIAGRAM MLP16 Green/RoHS compliant/Pb-Free MSL=1 Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part. www.azmicrotek.com +1-480-962-5881 Request a Sample 9 May 2012, Rev 2.0