Single Phase Energy Meter IC with Integrated Oscillator BL6502A FEATURES DESCRIPTION High accuracy, less than 0.1% error over a The BL6502A is a low cost, high accuracy, high dynamic range of 500 : 1 stability, simple peripheral circuit electrical energy meter IC. The meter based on the BL6502A is Exactly measure the real power in the positive orientation and negative orientation, calculate the intended energy in the same orientation distribution systems. It can exactly measure the real Two current monitors continuously monitor the power in the positive orientation and negative phase and neutral currents in two-wire distribution orientation and calculate the energy in the same systems. Uses the larger of two currents to bill, even orientation. during a Fault condition for using in single-phase, two-wire The BL6502A incorporates a novel A PGA in the current channel allows using small fault detection scheme that both warns of fault conditions value shunt and burden resistance and allows the BL6502A to continue accurate billing The low frequency outputs F1 and F2 can during a fault event. The BL6502A does this by directly drive electromechanical counters and two continuously monitoring both the phase and neutral phase stepper motors and the high frequency output (return) currents. Fault condition is indicated by CF, supplies instantaneous real power, is intended for PIN19 (FAULT), when these currents differ by more calibration and communications than 12.5%. Billing is continued using the larger of the two currents when the difference is greater than 14%. Two logic outputs REVP and FAULT can be used to indicate a potential orientation or Fault condition The BL6502A supplies average real power On-Chip power supply detector information on the low frequency outputs F1 (Pin23) On-Chip anti-creep protection and F2 (Pin24). These logic outputs may be used to On-Chip voltage reference of 2.5V±8% (typical directly drive an electromechanical counter and temperature coefficient of 30ppm/℃)，with external two-phase stepper motors. The CF (Pin22) logic overdrive capability output gives instantaneous real power information. Single 5V supply This output is intended to be used for calibration Low static power (typical value of 25mW). purposes or interface to an MCU. The technology of SLiM (Smart–Low–current– Management ) is used. BL6502A thinks over the stability of reading error in the process of calibration.. An internal no-load threshold ensures that the BL6502A does not exhibit Interrelated patents are pending BLOCK DIAGRAM VDD 1 24 F1 NC 2 23 F2 22 CF 21 NC NC 3 V1A 4 V1B 5 20 REVP 6 19 FAULT V1N V2N 7 V2P 8 NC BL6502A NC 17 9 16 G0 10 15 G1 GND 11 12 VREF 14 S0 13 S1 VDD input contron voltage reference V1A V1B V1N current sampling V2P V2N voltage sampling NC 18 VREF SCF any creep when there is no load. internal oscillator power detector BL6502A analog to digital high pass filter analog to digital high pass filter digital multiplic ation low pass filter digital to frequency and output FAULT REVP CF F1 F2 logic contron G0 G1 SCF S0 S1 DIP/SSOP 24 http://www.belling.com.cn -1Total 14 Pages 3/15/2007 BL6502A Single Phase Energy Meter IC with Integrated Oscillator PIN DESCRIPTIONS Pin Symbol DESCRIPTIONS 1 VDD Power Supply (+5V). Provides the supply voltage for the circuitry. It should be maintained at 5 V±5% for specified operation. 2 NC No connect. 3 NC No connect 4,5 V1A,V1B 6 V1N 7,8 V2N,V2P 9 NC Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum signal level of ±660 mV with respect to pin6 (V1N) for specified operation. Negative Input Pin for Differential Voltage Inputs V1A and V1B. Negative and Positive Inputs for Voltage Channel. These inputs provide a fully differential input pair. The maximum differential input voltage is ±660 mV for specified operation. No connect 10 VREF On-Chip Voltage Reference. The on-chip reference has a nominal value of 2.5V ± 8% and a typical temperature coefficient of 30ppm/℃. An external reference source may also be connected at this pin. 11 GND Ground Reference. Provides the ground reference for the circuitry. 12 SCF Calibration Frequency Select. This logic input is used to select the frequency on the calibration output CF. 13,14 S1,S0 Output Frequency Select. These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion. This offers the designer greater flexibility when designing the energy meter. 15,16 G1,G0 Gain Select. These logic inputs are used to select one of four possible gains for current channel. The possible gains are 1, 2, 8, and 16. 17 NC No connect 18 NC No connect 19 FAULT Fault Indication. Logic high indicates fault condition. Fault is defined as a condition under which the signals on V1A and V1B differ by more than 12.5%. The logic output will be reset to zero when fault condition is no longer detected. Negative Indication. Logic high indicates negative power, i.e., when the phase angle 20 REVP 21 NC No connect 22 CF Calibration Frequency. The CF logic output gives instantaneous real power information. This output is intended to use for calibration purposes. 23,24 F1,F2 Low-Frequency. F1 and F2 supply average real power information. The logic outputs can be used to directly drive electromechanical counters and 2-phase stepper motors. between the voltage and current signals is greater that 90°. This output is not latched and will be reset when positive power is once again detected. http://www.belling.com.cn -2Total 14 Pages 3/15/2007 BL6502A Single Phase Energy Meter IC with Integrated Oscillator ABSOLUTE MAXIMUM RATINGS ( T = 25 ℃ ) Parameter Symbol Value Unit Analog Power Voltage VDD VDD -0.3~+7(max) V Analog Input Voltage of Channel 2 to GND V (V) VSS+0.5≤V(v)≤VDD-0.5 V Analog Input Voltage of Channel 1 to GND V (I) VSS+0.5≤V(i)≤VDD-0.5 V Operating Temperature Range Topr -40~+85 ℃ Storage Temperature Range Tstr -55~+150 ℃ 400 mW Power Dissipation（SSOP24） Electronic Characteristic Parameter (T=25℃, VDD=5V) Parameter Symbol 1 Power Supply Current Test Condition IVDD VIH Input Low Voltage VIL Input Capacitance CIN VDD=5V 5 Unit mA 2 V 10 V pF Pin23, 24 Output High Voltage VOH1 IH=10mA Output Low Voltage VOL1 IL=10mA 4.4 V 0.5 IO1 10 4 Logic Output Pins CF, REVP, FAULT V mA Pin22, 20,19 Output High Voltage VOH2 IH=10mA Output Low Voltage VOL2 IL=10mA 4.4 Vref V 0.5 IO2 10 VDD=5V 6 Analog Input Pins V1A, V1B, V1N, V2N, V2P Maximum Input Voltage Max Value 1 3 Logic Output Pins F1, F2 5 On-chip Reference Typical Value Pin12, 13,14,15,1 6 Input High Voltage Output Current Min Value Pin1 2 Logic Input Pins SCF, S1, S0 , G1, G0 Output Current Measure Pin Pin10 2.3 2.5 V mA 2.7 V ±1 V Pin4, 5,6, 7,8 VAIN DC Input Impedance 330 Kohm Input Capacitance 10 pF 7 Accuracy Measurement Error on Channel 1 and 2 http://www.belling.com.cn -3Total 14 Pages 3/15/2007 BL6502A Gain=1 ENL1 Gain=2 ENL2 Gain=8 ENL8 Gain=16 ENL16 Both Channels with Full-Scale Signal Single Phase Energy Meter IC with Integrated Oscillator Pin22 0.1 0.3 % Pin22 0.1 0.3 % Pin22 0.1 0.3 % Pin22 0.1 0.3 % Channel 1 Lead 37° (PF=0.8Capacitive) Pin22 0.3 % Channel 1 Lags (PF=0.5Inductive) Pin22 0.3 % ±660mV Over a Dynamic Range 500 to 1 Phase Error between Channels 8 Start Current ISTART Ib=5A C=3200, Pin5 cosϕ=1 Voltage Channel 0.2%I b A Inputs ±110mV Gain of Current Channel 16 9 Positive and Negative Real Power Error (%) ENP Vv=±110mV,V(I)= 2mV, cosϕ=1 Vv=±110mV,V(I)= 2mV, cosϕ=-1 Pin22 1 % 10 Gain Error Gain error External 2.5V Reference,Gain=1, V1=V2=500mV DC Pin22 ±5 % TERMINOLOGY 1) Nonlinear Error The Nonlinear Error is defined by the following formula: eNL%＝[(Error at X-Error at Ib) / (1+Error at Ib )]*100% When V(v)= ±110mV, cosϕ=1, over the arrange of 5%Ib to 800%Ib, the nonlinear error should be less than 0.1%. 2) Start Current When meter constant C=3200, Ib=5A, cosϕ=1, V(V)=±110mV, 5％Ib error in normal range, the min AC current in current loop. 3) Positive And Negative Real Power Error When the positive real power and the negative real power is equal, and V(v) =±110mV, the test current is Ib, then the positive and negative real power error can be achieved by the following formula: eNP%=|[(eN%-eP%)/(1+eP%)]*100%| Where: eP% is the Positive Real Power Error, eN% is the Negative Real Power Error. http://www.belling.com.cn -4Total 14 Pages 3/15/2007 BL6502A Single Phase Energy Meter IC with Integrated Oscillator 4) Phase Error Between Channels The HPF (High Pass Filter) in Channel 1 has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is also placed in Channel 1. The phase correction network matches the phase to within ±0.1°over a range of 45 Hz to 65 Hz and ±0.2°over a range 40Hz to 1KHz. 5) Gain Error The gain error of the BL6502A is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. It is measured with a gain of 1 in channel V1. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the BL6502A transfer function. 6) Gain Error Match The gain error match is defined as the gain error (minus the offset) obtained when switching between a gain of 1 and a gain of 2, 8, or 16. It is expressed as a percentage of the output frequency obtained under a gain of 1. This gives the gain error observed when the gain selection is changed from 1 to 2, 8 or 16. 7) Power Supply Monitor BL6502A has the on-chip Power Supply monitoring The BL6502A will remain in a reset condition until the supply voltage on VDD reaches 4 V. If the supply falls below 4 V, the BL6502A will also be reset and no pulses will be issued on F1, F2 and CF. TIMING CHARACTERISTIC (VDD =5V, GND=0V, On-Chip Reference, On-Chip Oscillator, Temperature range: -40~+85°C) Parameter Value Comments t1 144ms F1 and F2 pulse-width (Logic Low). When the power is low, the t1 is equal to 144ms; when the power is high, and the output period exceeds 550ms, t1 equals to half of the output period. t2 F1 or F2 output pulse period. t3 ½ t2 Time between F1 falling edge and F2 falling edge. t4 71ms CF pulse-width (Logic high). When the power is low, the t4 is equal to 71ms; when the power is high, and the output period exceeds 180ms, t4 equals to half of the output period. t5 t6 CF Pulse Period. See Transfer Function section. CLKIN/4 http://www.belling.com.cn Minimum Time Between F1 and F2. -5Total 14 Pages 3/15/2007 BL6502A Single Phase Energy Meter IC with Integrated Oscillator Notes: 1) CF is not synchronous to F1 or F2 frequency outputs. 2) Sample tested during initial release and after any redesign or process change that may affect this parameter. THEORY OF OPERATION Principle of Energy Measure In energy measure, the power information varying with time is calculated by a direct multiplication of the voltage signal and the current signal. Assume that the current signal and the voltage signal are cosine functions; Umax, Imax are the peak values of the voltage signal and the current signal; ωis the angle frequency of the input signals; the phase difference between the current signal and the voltage signal is expressed asφ. Then the power is given as follows: p (t ) = U max cos( wt ) × I max cos( wt + ϕ ) If φ=0: p (t ) = U max I max [1 + cos(2 wt )] 2 If φ≠0: p (t ) = U max cos(ωt ) × I max cos(ωt + Φ ) = U max cos(ωt ) × [I max cos(ωt ) cos(Φ ) + I max sin(ωt ) sin(Φ )] U max I max [1 + cos(2ωt )] cos(Φ ) + U max I max cos(ωt ) sin(ωt ) sin(Φ ) 2 U I U I = max max [1 + cos(2ωt )] cos(Φ ) + max max sin( 2ωt ) sin(Φ) 2 2 U I U I = max max cos(Φ) + max max [cos(2ωt ) cos(Φ ) + sin(2ωt ) sin(Φ)] 2 2 U I U I = max max cos(Φ) + max max cos(2ωt + Φ) 2 2 = P(t) is called as the instantaneous power signal. The ideal p(t) consists of the dc component and ac component whose frequency is 2ω. The dc component is called as the average active power, that is: P= U max I max cos(ϕ ) 2 The average active power is related to the cosine value of the phase difference between the voltage signal and the current signal. This cosine value is called as Power Factor (PF) of the two channel signals. http://www.belling.com.cn -6Total 14 Pages 3/15/2007 Single Phase Energy Meter IC with Integrated Oscillator BL6502A Figure1. The Effect of phase When the signal phase difference between the voltage and current channels is more than 90°, the average active power is negative. It indicates the user is using the electrical energy reversely. Operation Process In BL6502A, the two ADCs digitize the voltage signals from the current and voltage transducers. These ADCs are 16-bit second order sigma-delta with an oversampling rate of 900 kHz. This analog input structure greatly simplifies transducer interfacing by providing a wide dynamic range for direct connection to the transducer and also simplifying the antialiasing filter design. A programmable gain stage in the current channel further facilitates easy transducer interfacing. A high pass filter in the current channel removes any dc component from the current signal. This eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current signals. The real power calculation is derived from the instantaneous power signal. The instantaneous power signal is generated by a direct multiplication of the current and voltage signals. In order to extract the real power component (i.e., the dc component), the instantaneous power signal is low-pass filtered. Figure 2 illustrates the instantaneous real power signal and shows how the real power information can be extracted by low-pass filtering the instantaneous power signal. This scheme correctly calculates real power for nonsinusoidal current and voltage waveforms at all power factors. All signal processing is carried out in the digital domain for superior stability over temperature and time. I V current sampling voltage sampling analog to digital high pass filter analog to digital digital multiplication high pass filter CF low pass filter digital to frequency F1 F2 instantaneous real power signal instantaneous power signal p(t) V*I integral p(t)=i(t)*v(t) v(t)=V*cos(wt) i(t)=I*cos(wt) V*I 2 p(t)= V*I 2 V*I 2 [1+cos(2wt)] t t Figure 2. Signal Processing Block Diagram The low frequency output of the BL6502A is generated by accumulatingm this real power information. This low frequency inherently means a long accumulation time between output http://www.belling.com.cn -7Total 14 Pages 3/15/2007 BL6502A Single Phase Energy Meter IC with Integrated Oscillator pulses. The output frequency is therefore proportional to the average real power. This average real power information can, in turn, be accumulated (e.g., by a counter) to generate real energy information. Because of its high output frequency and hence shorter integration time, the CF output is proportional to the instantaneous real power. This is useful for system calibration purposes that would take place under steady load conditions. Offset Effect The dc offsets come from the input signals and the forepart analog circuitry. Assume that the input dc offsets on the voltage channel and the current channel are Uoffset and Ioffset, and PF equals 1 (φ=0). p (t ) = [U cos(ωt ) + U offset ] × [ I cos(ωt + Φ ) + I offset ] = UI UI + I offsetU cos(ωt ) + U offset I cos(ωt ) + cos(2ωt ) 2 2 Figure 3. Effect of Offset As can be seen, for each phase input, if there are simultaneous dc offsets on the voltage channel and the current channel, these offsets contribute a dc component for the result of multiplication. That is, the offsets bring the error of Uoffset×Ioffset to the final average real power. Additionally, there exists the component of Uoffset×I+U×Ioffset at the frequency of ω. The dc error on the real power will result in measure error, and the component brought to the frequency of ω will also affect the output of the average active power when the next low-pass filter can’t restrain the ac component very completely. When the offset on the one of the voltage and the current channels is filtered, for instance, the offset on the current channel is removed; the result of multiplication is improved greatly. There is no dc error, and the additional component at the frequency of ω is also decreased. When the offsets on the voltage channel and the current channel are filtered respectively by two high-pass filters, the component at the frequency of ω (50Hz) is subdued, and the stability of the output signal is advanced. Moreover, in this case, the phases of the voltage channel and the current channel can be matched completely, and the performance when PF equal 0.5C or 0.5L is improved. In BL6502A, this structure is selected. Though it is given in the system specification that the ripple of the output signal is less than 0.1%, in real measure of BL6502A, the calibration output is very stable, and the ripple of the typical output signal is less than 0.05%. Additionally, this structure can ensure the frequency characteristic. When the input signal changes from 45Hz to 65Hz, the complete machine error due to the frequency change is less than 0.1%. In http://www.belling.com.cn -8Total 14 Pages 3/15/2007 BL6502A Single Phase Energy Meter IC with Integrated Oscillator such, the meter designed for the 50Hz input signal can be used on the transmission-line system of electric power whose frequency is 60Hz. VOLTAGE CHANNEL INPUT The output of the line voltage transducer is connected to the BL6502A at this analog input. As Figure4 shows that channel V2 is a fully differential voltage input. The maximum peak differential signal on Channel 2 is ±660mV. Figure4 illustrates the maximum signal levels that can be connected to the BL6502A Voltage Channel. V1 +660mV GAIN V1A Maximun input differential voltage ±660mV + V1 V2 V1N - V2 -660mV GAIN V1 Maximun input common-mode voltage ±100mV V1B + AGND Figure 4. Voltage Channels Voltage Channel must be driven from a common-mode voltage, i.e., the differential voltage signal on the input must be referenced to a common mode (usually GND). The analog inputs of the BL6502A can be driven with common-mode voltages of up to 100 mV with respect to GND. However, best results are achieved using a common mode equal to GND. Figure5 shows two typical connections for Channel V2. The first option uses a PT (potential transformer) to provide complete isolation from the mains voltage. In the second option, the BL6502A is biased around the neutral wire and a resistor divider is used to provide a voltage signal that is proportional to the line voltage. Adjusting the ratio of Ra and Rb is also a convenient way of carrying out a gain calibration on the meter. RF CT VAP CF + ±660mV RF AGND VN - CF AGND Phase Neutral AGND CF Ra Rb AGND Rv AGND ±660mV VAP Phase Neutral RF AGND VN Ra >> RF Rb+Rv=RF Figure 5. http://www.belling.com.cn + - CF AGND AGND Typical Connections for Voltage Channels -9Total 14 Pages 3/15/2007 Single Phase Energy Meter IC with Integrated Oscillator BL6502A CURRENT CHANNEL INPUT The voltage outputs from the current transducers are connected to the BL6502A here. As Figure6 shows that channel V1 has two voltage inputs, namely V1A and V1B. These inputs are fully differential with respect to V1N. However, at any one time, only one is selected to perform the power calculation. V1 +660mV V2P Maximun input differential voltage ±660mV + V1 - V2N V2 V2 Maximun input common-mode voltage ±100mV AGND -660mV Figure 6. Current Channels The analog inputs V1A, V1B and V1N have same maximum signal level restrictions as V2P and V2N. However, Channel 1 has a programmable gain amplifier (PGA) with user-selectable gains of 1, 2, 8, or 16. These gains facilitate easy transducer interfacing. Figure illustrates the maximum signal levels on V1A, V1B, and V1N. The maximum differential voltage is ±660 mV divided by the gain selection. Again, the differential voltage signal on the inputs must be referenced to a common mode, e.g., GND. The maximum common-mode signal is ±100 mV. Figure7 shows a typical connection diagram for Channel V1. Here the analog inputs are being used to monitor both the phase and neutral currents. Because of the large potential difference between the phase and neutral, two CTs (current transformers) must be used to provide the isolation. The CT turns ratio and burden resistor (Rb) are selected to give a peak differential voltage of ±660 mV/gain. RF CT V1A Rb IP ±660mV GAIN + CF V1N IN AGND Rb ±660mV GAIN - CF + V1B CT RF Phase Neutral CF Ra Rb Rv AGND Ra >> RF Rb+Rv=RF ±660mV V1A AGND IP + - V1N IN AGND Rb CT ±660mV GAIN - CF V1B + RF Phase Neutral Figure 7. http://www.belling.com.cn Typical Connections for Current Channels - 10 Total 14 Pages 3/15/2007 BL6502A Single Phase Energy Meter IC with Integrated Oscillator FAULT DETECTION The BL6502A incorporates a novel fault detection scheme that warns of fault conditions and allows the BL6502A to continue accurate billing during a fault event. The BL6502A does this by continuously monitoring both the phase and neutral (return) currents. A fault is indicated when these currents differ by more than 12.5%. However, even during a fault, the output pulse rate on F1 and F2 is generated using the larger of the two currents. Because the BL6502A looks for a difference between the signals on V1A and V1B, it is important that both current transducers are closely matched. On power-up the output pulse rate of the BL6502A is proportional to the product of the signals on Channel V1A and Voltage Channel. If there is a difference of greater than 12.5% between V1A and V1B on power-up, the fault indicator (FAULT) will go active after about one second. In addition, if V1B is greater than V1A the BL6502A will select V1B as the input. The fault detection is automatically disabled when the voltage signal on Channel 1 is less than 0.5% of the full-scale input range. This will eliminate false detection of a fault due to noise at light loads. If V1A is the active current input (i.e., is being used for billing), and the signal on V1B (inactive input) falls by more than 12.5% of V1A, the fault indicator will go active. Both analog inputs are filtered and averaged to prevent false triggering of this logic output. As a consequence of the filtering, there is a time delay of approximately one second on the logic output FAULT after the fault event. The FAULT logic output is independent of any activity on outputs F1 or F2. Figure 8 illustrates one condition under which FAULT becomes active. Since V1A is the active input and it is still greater than V1B, billing is maintained on VIA, i.e., no swap to the V1B input will occur. V1A remains the active input. V1A V1B V1A V1B V1N 0V FAULT current sampling to ADC V1B < 87.5% V1A Figure 8. Fault Conditions for Inactive Input Less than Active Input Figure 9 illustrates another fault condition. If V1A is the active input (i.e., is being used for billing) and the voltage signal on V1B (inactive input) becomes greater than 114% of V1A, the FAULT indicator goes active, and there is also a swap over to the V1B input. The analog input V1B has now become the active input. Again there is a time delay of about 1.2 seconds associated with this swap. V1A will not swap back to being the active channel until V1A becomes greater than 114% of V1B. However, the FAULT indicator will become inactive as soon as V1A is within 12.5% of V1B. This threshold eliminates potential chatter between V1A and V1B. V1B V1A V1A 0V V1B V1N FAULT current sampling to ADC V1A < 87.5% V1B Figure 9. Fault Conditions for Inactive Input Greater than Active Input http://www.belling.com.cn - 11 Total 14 Pages 3/15/2007 BL6502A Single Phase Energy Meter IC with Integrated Oscillator Power Supply Monitor The BL6502A contains an on-chip power supply monitor. If the supply is less than 4V±5% then the BL6502A will go in an inactive state, i.e. no energy will be accumulated when the supply voltage is below 4V. This is useful to ensure correct device operation at power up and during power down. The power supply monitor has built-in hysteresis and filtering. This gives a high degree of immunity to false triggering due to noisy supplies. The trigger level is nominally set at 4V, and the tolerance on this trigger level is about ±5%. The power supply and decoupling for the part should be such that the ripple at VDD does not exceed 5V±5% as specified for normal operation. SLiM technology The BL6502A adopts the technology of SLiM (Smart Low current Management) to decrease the static power greatly. The static power of BL6502A is about 12mW. It is half of the previous product BL0951 (about 25mW ).This technology also decreases the request for power supply design. BL65XX series products used 0.35um CMOS process. The reliability and consistency are advanced. OPERATION MODE Transfer Function The BL6502A calculates the product of two voltage signals (on Channel 1 and Channel 2) and then low-pass filters this product to extract real power information. This real power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active low pulses. The pulse rate at these outputs is relatively low. It means that the frequency at these outputs is generated from real power information accumulated over a relatively long period of time. The result is an output frequency that is proportional to the average real power. The average of the real power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation. Freq = 3.5 × V (v) × V (i ) × gain × FZ 2 VREF Freq——Output frequency on F1 and F2 (Hz) V(v)——Differential rms voltage signal on Channel 1 (volts) V(i)——Differential rms voltage signal on Channel 2 (volts) Gain——1, 2, 8 or 16, depending on the PGA gain selection, using logic inputs G0 and G1 Vref——The reference voltage (2.50 V±8%) (volts) Fz——One of four possible frequencies selected by using the logic inputs S0 and S1. S1 S0 Fz(Hz) XTAL/CLKIN 0 0 1.7 CLKIN/2^21 0 1 3.4 CLKIN/2^20 1 0 6.8 CLKIN/2^19 1 1 13.6 CLKIN/2^18 http://www.belling.com.cn - 12 Total 14 Pages 3/15/2007 BL6502A Single Phase Energy Meter IC with Integrated Oscillator Frequency Output CF The pulse output CF (Calibration Frequency) is intended for use during calibration. The output pulse rate on CF can be up to 128 times the pulse rate on F1 and F2. The following Table shows how the two frequencies are related, depending on the states of the logic inputs S0, S1 and SCF. Mode SCF S1 S0 CF/F1 (or F2) 1 1 0 0 128 2 0 0 0 64 3 1 0 1 64 4 0 0 1 32 5 1 1 0 32 6 0 1 0 16 7 1 1 1 16 8 0 1 1 8 Because of its relatively high pulse rate, the frequency at this logic output is proportional to the instantaneous real power. As is the case with F1 and F2, the frequency is derived from the output of the low-pass filter after multiplication. However, because the output frequency is high, this real power information is accumulated over a much shorter time. Hence less averaging is carried out in the digital-to-frequency conversion. With much less averaging of the real power signal, the CF output is much more responsive to power fluctuations. GAIN SELECTION By select the digital input G0 and G1 voltage (5V or 0V), we can adjust the gain of current channel. We can see that while increasing the gain, the input dynamic range is decreasing. G1 G0 Gain Maximum Differential Signal 1 1 1 ±660mV 1 0 2 ±330mV 0 1 8 ±82mV 0 0 16 ±41mV ANALOG INPUT RANGE The maximum peak differential signal on Voltage Channel is ± 660 mV, and the common-mode voltage is up to 100 mV with respect to GND. The analog inputs V1A, V1B, and V1N have the same maximum signal level restrictions as V2P and V2N. However, The Current Channel has a programmable gain amplifier (PGA) with user-selectable gains of 1, 2, 8, or 16. These gains facilitate easy transducer interfacing. The maximum differential voltage is ±660 mV and the maximum common-mode signal is ±100 mV. The corresponding Max Frequency of CF/F1/F2 is shown in the following table. http://www.belling.com.cn - 13 Total 14 Pages 3/15/2007 BL6502A SCF S1 S0 Fz Max Frequency of F1, F2 (Hz) DC Single Phase Energy Meter IC with Integrated Oscillator CF Max Frequency (Hz) AC DC AC 1 0 0 1.7 0.68 0.34 128×F1,F2=87.04 128×F1,F2=43.52 0 0 0 1.7 0.68 0.34 64×F1,F2=43.52 64×F1,F2=21.76 1 0 1 3.4 1.36 0.68 64×F1,F2=87.04 64×F1,F2=43.52 0 0 1 3.4 1.36 0.68 32×F1,F2=43.52 32×F1,F2=21.76 1 1 0 6.8 2.72 1.36 32×F1,F2=87.04 32×F1,F2=43.52 0 1 0 6.8 2.72 1.36 16×F1,F2=43.52 16×F1,F2=21.76 1 1 1 13.6 5.44 2.72 16×F1,F2=87.04 16×F1,F2=43.52 0 1 1 13.6 5.44 2.72 8×F1,F2=43.52 8×F1,F2=21.76 PACKAGE DIMENSIONS SSOP24 Notice： Sample tested during initial release and after any redesign or process change that may affect parameter. Specification subject to change without notice. Please ask for the newest product specification at any moment. http://www.belling.com.cn - 14 Total 14 Pages 3/15/2007