BL7448SM Intelligent 8K-bit EEPROM Description BL7448SM is an IC Card chip (module) made by 0.35um CMOS EERPOM process. It has 1024 byte EEPROM with logical encryption and function. Figure 1 Features • • • • • • • • • 1024 x 8 bit EEPROM organization Byte-wise addressing Irreversible byte-wise write protection of every Byte 1024 x1 bit organization of protection memory Serial three-wire link End of processing indicated at data output Minimum of 100,000 write/erase cycles Data retention time :>10 years Contacts configuration and serial interface according to ISO 7816 standard (synchronous transmission) Data can only be changed after entry of the correct 2-byte Programmable security code Pin Description Pin No. 1 2 3 4 5 6 7 8 Parameter C1 C2 C3 C4 C5 C6 C7 C8 http://www.belling.com.cn Symbol Vdd RST CLK N.C. GND NC I/O NC -1Total 7 Pages Function Description Supply Voltage Reset signal Clock input Not connected Ground Not connected Bidirectional data line (open drain) Not connected 8/16/2006 BL7448SM Intelligent 8K-bit EEPROM Function Description Block Diagram Figure 2 The BL7448SM consists of 1024 x 8 bit EEPROM main memory and a 1024-bit protection-memory With PROM functionality .The main memory can be irreversibly protected against data change by writing the corresponding bit in the protection memory. Once written the protection bit cannot be erased. The main memory is erased and written byte by byte. Normally a data change consists of an erase and write procedure. It depends on the contents of the data byte in the main memory and the new data byte whether the EEPROM is really erased and/or written. If none of the 8 bits in the addressed byte requires a zero-toone transition the erase access will be suppressed. Vice versa the write access will be suppressed if no oneto-zero transition is necessary. Additionally to the above functions the BL7448SM provides a security code logic, which controls the write/erase access to the memory. For this purpose, the BL7448SM contains a 3byte security memory with an error counter EC and 2 bytes reference data. These 2 bytes as a whole are called programmable security code (PSC). After power on the whole memory, except for the reference data, the memory can only be read. (The value of PSC is “00”)Writing and erasing is only possible after a successful comparison of verification data with the internal reference data. http://www.belling.com.cn -2Total 7 Pages 8/16/2006 BL7448SM Intelligent 8K-bit EEPROM After eight successive unsuccessful comparisons the error counter blocks any subsequent attempt, and hence any possibility to write and erase. Reset and Answer-to-Reset *Reset After connecting the operating voltage to Vcc, the chip will hold and wait the operation of reset. The operation of reset begins with RST from L to H, and ends with CLK from L to H. During the operation of reset, all commands will be ignored. After power on reset, the operation of reading must be execute before data can be altered. . *Answer-to-Reset Answer-to-Reset set the address counter to zero and output the first data. The other data can be read with CLK signal. Command RST RST 1 0 I/O Command Input Data Output Command Byte2 Address Byte1 A8 A9 Byte3 Data A0~A7 Operation S0 S1 S2 S3 S4 S5 1 0 0 0 1 1 Data 1 1 0 0 1 1 Data 0 0 0 0 1 1 Comp. data 0 0 1 1 0 0 No effect 0 1 1 1 0 0 No effect Mode D0~D7 Updata main memory & protection memory Updata main memory Write protection memory Read main memory & protection memory Read main memory Processing Processing Processing Data Output Data Output VCC RST 1 CLK I/O RST 2 1 td4 2 31 3 td2 td4 CLK 3 31 tH IC sets I/O to State H 32 32 tL td5 I/O Figure 3 Reset and Answer-to-Reset http://www.belling.com.cn -3Total 7 Pages 8/16/2006 BL7448SM Intelligent 8K-bit EEPROM 0 1 2 3 5 4 6 7 0 1 2 3 4 5 6 7 0 2 1 3 4 5 6 S0 S1 S2 S3 S4 S5 A8 A9 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 Bute 1 Control Byte Bute 3 Data Bute 2 Address Figure 4 Command Input Command Mode Write/Erase Operation Write/Erase, except for protection-memory Note: Write means from H to L, Erase means from L to H There are three kinds of Write/Erase operations: Erase and Write (The number of clock pulses=203, frequency <=20KHZ) Write only: means the 8 bits in the addressed byte from H to L( The number of clock pulses =103, frequency <=20KHZ) Erase only(=FF; The number of clock pulses =103, frequency <= 20KHZ) Write/Erase, include protection-memory As shipped, the protection-memory has been erased, it can be written only once. Write protection-memory and compare data When comparison of the entered data byte is same as the assigned byte in the EEPROM. the protection-memory is written. After sent a certain CLK, the command of Write/Erase will be over. After operation, the state of I/O pin will be changed from H to L. The I/O state can be changed when RST change from L to H. Processing Command Input RES CLK 0 23 0 1 2 99 TE 102 199 202 TW E/W Internal signal I/O S0 S1 D6 D7 Figure 5 Erase and Write timing Processing Command Input RES CLK 0 23 0 1 2 99 TE 102 199 202 TW E/W Internal signal I/O S0 S1 D6 D7 Figure 6 Only Write or Erase Read operation Read main memory (See Figure 7) This operation don’t read the protection-memory. After 8 CLK, the address of memory will be increased by additional pulse . http://www.belling.com.cn -4Total 7 Pages 8/16/2006 BL7448SM Intelligent 8K-bit EEPROM Read main memory and protection-memory (See Figure 8) After input this command, the next 8 CLK will read out 8 bits data; the ninth CLK will read out the content of protection-memory. After 9 CLK, the address of memory will be increased by additional pulse. Security code verification Byte1 Byte2 Address Byte3 Address Operation 0 1 0 0 1 1 1 1 253 Bit mask 1 0 1 1 0 0 1 1 254 PSC byte1 1 0 1 1 0 0 1 1 255 PSC byte2 Write error counter Verification 1st PSC byte nd Verification 2 PSC byte Mode Processing Processing Processing Command Input DataOutput RST CLK A8 A9 I/O D6 D7 random value StartingAddress 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 StartingAddress 0 1 2 3 4 5 6 7 StartingAddress+1 StartingAddress+n Figure 7 Read main memory Data CommandInput Output RST CLK 23 0 I/O A8 A9 StartingAddress D6 D7 random value 0 1 2 3 4 5 6 7 P0 0 1 2 3 4 5 6 7 P0 StartingAddress P0 0 1 2 3 4 5 6 7 P0 StartingAddress+1 StartingAddress+n Figure 8 read main memory and protection-memory Security code verification User verification operation BL7448SM only can read when the security code verification is unsuccessful. The content of security code cannot be read out. If you try to read security code, you only can get “00” The processing is: *Write a bit of EC(the bit is not written before), the address of EC is “1021” *Input the first byte of PSC, the address is “1022” *Input the second byte of PSC, the address is “1023” *If the security verification is successful , the EC can be erased. http://www.belling.com.cn -5Total 7 Pages 8/16/2006 BL7448SM Intelligent 8K-bit EEPROM After security code identification , I/O will be changed from H to L. I/O will return to H when RST change from L to H. EC cannot be erased automatically. Write Error Counter (EC) Before security code identification, only Error Counter (EC) can be written. A number of erased bit of EC means what times EC can be written. After security code verification is successful, EC should be erased before power off. After security code verification is unsuccessful, if it is verified again, EC must be written. Input PSC PSC input start from lowest bit of low byte to high byte. If comparison of data is right, EEPROM can be written or erased before power-off and the corresponding protection bit of PSC is H, PSC can be changed. Write EC No compare fobidden EC write Enable？ Yes compare 1st PSC Byte No compare failed OK？ Yes compare 2nd PSC Byte No compare Failed OK？ Yes Password Verification OK,Erase EC->FF Figure 9 Verification Procedure Data CommandInput Output RST CLK 23 0 I/O A8 A9 StartingAddress D6 D7 random value 0 1 2 3 4 5 6 7 P0 0 1 2 3 4 5 6 7 P0 StartingAddress StartingAddress+1 P0 0 1 2 3 4 5 6 7 P0 StartingAddress+n Figure 10. PSC Verification timing http://www.belling.com.cn -6Total 7 Pages 8/16/2006 BL7448SM Intelligent 8K-bit EEPROM Electrical Parameter • Absolute Maximum Ratings Parameter Supply voltage Input voltage (any pin) Storage temperature Power comsumption Operation temperature • VCC VI TS PT Ta min. -0.3 -0.3 -40 0 -35 Limit Values typ. Max 6.0 6.0 125 60 70 Unit V V ℃ mw ℃ DC Characteristics Parameter Supply voltage Supply current High-level input voltage (I/O,CLK,RST) Low-level input voltage (I/O,CLK,RST) High-level input current (I/O,CLK,RST) Low-level output current VOL =0.4V,open drain High-level leakage current VOH = VCC,open drain Input capacitance • Symbol Symbol VCC ICC min. 3.0 Limit Values typ. Max 5.0 5.5 3 10 Unit V mA VIH 0.7VCC - VCC +0.3 V VIL VGND0.2 - 0.15VGND V IH - - 50 uA IOL 0.5 - - mA IOH - - 50 A CI - - 10 pF AC Characteristics Parameter Symbol Clock frequency Clock high period Clock low period Setup time data Delay time Clock setup time for RST RST setup time for clock Hold time data Eraser time Write time CLK tH tL td1 td2 td3 td4 td5 TER tWR http://www.belling.com.cn min. Limit Values typ. Max 20 10 10 4 6 4 4 4 5 5 -7Total 7 Pages Unit kHz µs µs µs µs µs µs µs ms ms 8/16/2006