BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator FEATURES DESCRIPTION Up to 300mA Output Current(Each LDO) The BL9180 dual, low noise, low-dropout regulator Dual Shutdown Pins Control Each Output supplying up to 300mA output current at each 90uA Operating supply current per LDO channel. The output voltage for each regulator is set Excellent Line regulation:0.05%/V independently by trimming. Voltages are selectable Low Dropout:220mV@300mA in 50mV steps within a range of 1.2V to 3.3V by High Power Supply Rejection Ratio operating from a 2V to 6V input. The BL9180 Wide Operating Voltage Range:2.0V to 6.0V includes two independent logic-controlled shutdown 1.2V to 3.3V Factory-Preset Output inputs and allows the output of each regulator to be High Accuracy: ±1% or ±2% turned off independently. When both outputs Internal Pulled down(8 MΩ)resistor shutdown simultaneously, the chip will be turn off Current Limiting and Thermal Protection and consumes nearly zero operation current which Two LDOs in SOT-23-6 and ESOP-8 Package is suitable for battery-power devices. RoHS Compliant and 100% Lead(Pb)-Free The BL9180 includes high accuracy voltage reference, error amplifier, current limit circuit and APPLICATIONS output driver module. Cellular and Smart Phones The BL9180 has excellent load and line transient Battery-Powered Equipment response and good temperature characteristics, Laptop, Palmtops, Notebook Computers which can assure the stability of chip and power Hand-Held Instruments system. PCMCIA Cards and Wireless LAN MP3/MP4/MP5 Players guarantee output voltage accuracy within ±1% or ±2%. The BL9180 is available in SOT-23-6 and Portable Information Appliances ESOP-8 package which is Lead(Pb)-free. And it uses trimming ORDERING INFORMATION TYPICAL APPLICATION BL9180 X X X XX BL9180 XXX RB PPMIC BU BL9180 Rev 2.1 8/2010 Package: RA:SOT-23-6A RB:SOT-23-6B EP:ESOP-8 Features: P:Standard(default, lead free) C:Customized Output Voltage Accuracy A:±1% B:±2% Output Voltage A: 1.3V(Output1),2.8V(Output2) B: 1.5V(Output1),3.0V(Output2) C: 1.8V(Output1),2.5V(Output2) D: 1.8V(Output1),2.8V(Output2) E: 2.5V(Output1),1.8V(Output2) F: 2.8V(Output1),1.8V(Output2) G: 2.8V(Output1),3.0V(Output2) H: 2.8V(Output1),3.3V(Output2) I: 3.0V(Output1),1.5V(Output2) J: 3.3V(Output1),2.8V(Output2) K: 3.3V(Output1),3.3V(Output2) L:2.8V(Output1),1.2V(Output2) M:1.8V(Output1),3.3V(Output2) N:1.5V(Output1),3.3V(Output2) O: 1.2V(Output1),3.3V(Output2) 1 2 VIN 3 EN1 VOUT1 VDD GND EN2 VOUT2 1uF technique 6 5 4 to VOUT1 1uF VOUT2 BL9180 1uF Application hints: Output capacitor (COUT≥2.2uF) is recommended in BL9180 applications to assure the circuit’s stability for output voltage ≤ 1.8V. www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 1 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator Absolute Maximum Rating Input Supply Voltage (VIN) EN Input Voltage Output Voltage Output Current (Note 1) -0.3V to +7V -0.3V to +VIN -0.3V to VIN+0.3V 400mA Maximum Junction Temperature 125°C (Note2) Operating Temperature Range -40°C to 85°C Storage Temperature Range -65°C to 125°C Lead Temperature (Soldering, 10s) 300°C Package Information SOTSOT-2323-6A TOP VIEW 2 VOUT2 VOUT2 3 EN1 EN1 5 GND 4 EN1 EN1 1 VDD EN2 EN2 EN2 EN2 Part Number 3 VOUT1 VOUT1 5 GND 4 VOUT2 VOUT2 Top Mark VOUT1 VOUT1 1 VIN1 VIN1 2 VOUT2 VOUT2 3 VIN2 VIN2 4 EVYW BL9180-XXXRB EVYW -40°C to +85°C BL9180-XXXEP BL9180 (Note3) VYWEP -40°C to +85°C EN1 EN1 7 GND 6 GND 5 EN2 EN2 -40°C to +85°C Thermal Resistance (Note 4): Name Function VOUT1 LDO1 Output Pin VDD Input Pin VOUT2 LDO2 Output Pin EN2 LDO2 Enable Pin GND Ground Pin EN1 LDO1 Enable Pin1 VIN1 Input Pin1 VIN2 Input Pin2 ӨJA 250°C/W 50°C/W Package SOT23-6 ESOP-8 9 2009 A 2010 B 2011 C 2012 D 2013 1 A … … 25 Y 26 Z 27 a W Week 8 Temp Range (Note3) BL9180-XXXRA Pin Description Y Year 2 6 MARKING VDD 6 ESOPESOP-8 TOP VIEW MARKING 1 MARKING VOUT1 VOUT1 SOTSOT-2323-6B TOP VIEW … … 51 y ӨJC 130°C/W 10°C/W 52 z Product Classification Output Voltage 1.3V/2.8V 1.5V/3.0V 1.8V/2.5V 1.8V/2.8V 2.5V/1.8V Voltage Code A B C D E PPMIC BU BL9180 Rev 2.1 8/2010 Accuracy ±2% ±2% ±2% ±2% ±2% Package Type SOT-23-6A SOT-23-6A SOT-23-6A SOT-23-6A SOT-23-6A Product Name BL9180-ABPRA BL9180-BBPRA BL9180-CBPRA BL9180-DBPRA BL9180-EBPRA Package Type SOT-23-6B SOT-23-6B SOT-23-6B SOT-23-6B SOT-23-6B Product Name BL9180-ABPRB BL9180-BBPRB BL9180-CBPRB BL9180-DBPRB BL9180-EBPRB Package Type ESOP-8 ESOP-8 ESOP-8 ESOP-8 ESOP-8 www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved Product Name BL9180-ABPEP BL9180-BBPEP BL9180-CBPEP BL9180-DBPEP BL9180-EBPEP 2 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator 2.8V/1.8V 2.8V/3.0V 2.8V/3.3V 3.0V/1.5V 3.3V/2.8V 3.3V/3.3V 2.8V/1.2V 1.8V/3.3V 1.5V/3.3V 1.2V/3.3V F G H I J K L M N O ±2% ±2% ±2% ±2% ±2% ±2% ±2% ±2% ±2% ±2% SOT-23-6A SOT-23-6A SOT-23-6A SOT-23-6A SOT-23-6A SOT-23-6A SOT-23-6A SOT-23-6A SOT-23-6A SOT-23-6A BL9180-FBPRA BL9180-GBPRA BL9180-HBPRA BL9180-IBPRA BL9180-JBPRA BL9180-KBPRA BL9180-LBPRA BL9180-MBPRA BL9180-NBPRA BL9180-OBPRA SOT-23-6B SOT-23-6B SOT-23-6B SOT-23-6B SOT-23-6B SOT-23-6B SOT-23-6B SOT-23-6B SOT-23-6B SOT-23-6B BL9180-FBPRB BL9180-GBPRB BL9180-HBPRB BL9180-IBPRB BL9180-JBPRB BL9180-KBPRB BL9180-LBPRB BL9180-MBPRB BL9180-NBPRB BL9180-OBPRB ESOP-8 ESOP-8 ESOP-8 ESOP-8 ESOP-8 ESOP-8 ESOP-8 ESOP-8 ESOP-8 ESOP-8 BL9180-FBPEP BL9180-GBPEP BL9180-HBPEP BL9180-IBPEP BL9180-JBPEP BL9180-KBPEP BL9180-LBPEP BL9180-MBPEP BL9180-NBPEP BL9180-OBPEP Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The BL9180 is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by des ign, characterization and correlation with statistical process controls. Note 3: E: BL9180 with RA package E: BL9180 with RB package V: Voltage code Y: Year of wafer manufacturing W: Week of wafer manufacturing EP: ESOP-8 Note 4: Thermal Resistance is specified with approximately 1 square of 1 oz copper. Block Diagram SOT23-6 PPMIC BU BL9180 Rev 2.1 8/2010 ESOP-8 www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 3 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator Electrical Characteristics (Note 5) (VIN=3.6V, EN1=EN2=VIN, CIN=COUT=1µF, TA=25°C, unless otherwise noted.) Parameter Symbol Conditions MIN TYP Input Voltage VIN 2 Output Voltage Accuracy -1 VIN=3.6V, ∆VOUT (Note 6) IOUT=1mA -2 Current Limit ILIM 400 430 RLOAD=1Ω Quiescent Current IQ VEN>1.2V, IOUT=0mA 180 IOUT=200mA, 130 VOUT=2.8V Dropout Voltage VDROP IOUT=300mA, 210 VOUT=2.8V VIN=3.6V to 5.5V (Note 7) ∆VLINE 0.05 Line Regulation IOUT=1mA (Note 8) ∆VLOAD 1mA<IOUT<300mA Load Regulation (Note 9) Output Voltage TCVOUT IOUT=1mA ±60 Temperature Coefficient Standby Current ISTBY VEN=GND,Shutdown 0.01 EN Input Bias Current IIBSD VEN=GND or VIN 0 VIN=3V to 5.5V, EN Logic Low VIL Shutdown Input VIN=3V to 5.5V, Threshold Logic High VIH 1.2 Start up 10Hz to100KHz, Output Noise 100 eNO IOUT=200mA Voltage COUT=1uF Power f=217Hz -73 Supply PSRR IOUT=100mA f=1KHz -70 Rejection f=10KHz -50 Ratio Thermal Shutdown Shutdown, Temp TSD 165 Temperature increasing Thermal Shutdown TSDHY 30 Hysteresis MAX 6 +1 +2 260 unit V % mA µA 180 mV 300 0.17 %/V 2 %/A ppm/°C 1 100 µA nA 0.4 V V µVRMS dB °C °C Note 5: 100% production test at +25°C. Specifications over the temperature range are guaranteed by design and characterization. Note 6: This IC includes two kinds of output voltage accuracy versions. A: ±1%, B: ±2%. VOUT 1 − VOUT 2 ∆V × V OUT ( normal ) IN Note 7: Line regulation is calculated by ∆V LINE = × 100 Where VOUT1 is the output voltage when VIN=5.5V, and VOUT2 is the output voltage when VIN=3.6V, △VIN=1.9V. VOUT(normal)=2.8V. VOUT 1 − VOUT 2 Note 8: Load regulation is calculated by ∆V ×100 LOAD = ∆I × V OUT OUT ( normal ) Where VOUT1 is the output voltage when IOUT=1mA, and VOUT2 is the output voltage when IOUT=300mA. △IOUT=0.299A, VOUT(normal)=2.8V. ∆VOUT Note 9: The temperature coefficient is calculated by TC VOUT = ∆T × VOUT PPMIC BU BL9180 Rev 2.1 8/2010 www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 4 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator Typical Performance Characteristics Output Voltage Vs. Temperature IQ Vs.VIN(BL9180-HBPRB) 3.0 220 CIN=1uF COUT1=1uF,COUT2=1uF No Load VIN=3.6V CIN=COUT=1uF 215 Quiescent Current(uA) Output Voltage(V) 2.9 2.8 2.7 2.6 210 205 200 2.5 -50 -25 0 25 50 75 100 195 3.50 125 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 Input Voltage(V) Temperaute(°C) Dropout Voltage Vs. Load Current PSRR(VOUT1) 300 0 CIN=COUT=1uF CIN=COUT1=COUT2=1uF VOUT1=2.8V VOUT2=3.0V -10 VOUT=2.8V -20 200 PSRR(dB) Dropout Voltage(mV) 250 150 -30 -40 -50 100 TJ=85°C TJ=25°C TJ=-40°C 50 -70 0 0 50 100 150 200 250 1mA Load 100mA Load 200mA Load -60 -80 10 300 100 1000 Load Current(mA) 100000 1000000 VOUT Vs. VIN(BL9180-HBPRB) EN Pin Shutdown Threshold Vs. Temperature 1.05 3.4 VIN=3.6V 1.00 3.2 CIN=COUT=1uF 3.0 2.8 0.95 Output Voltage(V) EN Pin Shutdown Threshold(V) 10000 Frequency(Hz) 0.90 0.85 2.6 2.4 2.2 2.0 1.8 CIN=1uF COUT1=COUT2=1uF IOUT1=IOUT2=100mA 1.6 1.4 0.80 VOUT1(2.8V) VOUT2(3.3V) 1.2 0.75 -50 -25 PPMIC BU BL9180 Rev 2.1 8/2010 0 25 50 Temperature(°C) 75 100 125 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage(V) www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 5 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator PPMIC BU BL9180 Rev 2.1 8/2010 www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 6 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator Output Voltage(V) VOUT Vs.VIN 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 1.0 CIN=COUT=1uF ILoad=1mA ILoad=100mA ILoad=300mA 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Voltage(V) PPMIC BU BL9180 Rev 2.1 8/2010 www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 7 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator Applications Information The BL9180 is integrated with two low noise, low dropout and low quiescent current linear regulators designed primarily for battery applications. Output voltages are optional ranging from 1.2V to 3.3V, and each channel can supply current up to 300 mA. Enable Function The BL9180 is shutdown by pulling the EN input low, and turn on by driving the input high. If this feature is not be used, the EN input should be tied to VIN to keep the regulator on at all times. The BL9180 includes two independent current limit structure which monitor and control each pass transistor’s gate voltage limiting the guaranteed maximum output current to 300mA. Thermal overload protection limits total power dissipation in the BL9180. When the junction temperature exceeds TJ=165°C, the OTP circuit starts the thermal shutdown function turn the pass element off and allowing the IC to cool. The OTP circuit turn on the pass element again after IC’s junction temperature cool by 30°C, result in a pulsed output during continuous thermal overload conditions. Thermal-overloaded protection is designed to protect the BL9180 in the event of fault conditions. Do not exceed the absolute maximum junction temperature rating of TJ=125°C for continuous operation. The output can be shorted to ground for an indefinite amount of time without damaging the part by cooperation of current limit and thermal BL9180 Rev 2.1 8/2010 Operating Region and Power Dissipation The maximum power dissipation of BL9180 depends on the thermal resistance of the case and circuit board, the temperature difference between the die junction and ambient air, and the rate of airflow. The power dissipation across the device is PD = (VIN−VOUT) ×IOUT + VIN×IQ The maximum power dissipation is: PD(MAX) = ( TJ(MAX) − TA ) /θJA Current Limit and Thermal Protection PPMIC BU protection. Where TJ(MAX) is the maximum operation junction temperature 125°C, T A is the ambient temperature and the θJA is the junction to ambient thermal resistance. The GND pin of the BL9180 performs the dual function of providing an electrical connection to ground and channeling heat away. Connect the GND pin to ground using a large pad or ground plane. Capacitor Selection and Regulator Stability Like any low-dropout regulator, the external capacitors used with the BL9180 must be carefully selected for regulator stability and performance. The BL9180 requires an output capacitor between the VOUT and GND pins for phase compensation. Using a capacitor whose value is > 1µF on the BL9180 input and the amount of www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 8 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator capacitance can be increased without limit. The input capacitor must be located a distance of not more than 0.5 inch from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDOs applications. The BL9180 is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least 1µF with ESR is > 5mΩ on the BL9180 output ensures stability. The BL9180 still works well with output capacitor of other types due to the wide stable ESR range. Output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and PSRR. The output capacitor should be located not more than 0.5 inch from the VOUT pin of the BL9180 and returned to a clean analog ground. Load-Transient Considerations The BL9180 load-transient response graphs show two components of the output response: a DC shift from the output PPMIC BU BL9180 Rev 2.1 8/2010 impedance due to the load current change, and the transient response. The DC shift is quite small due to the excellent load regulation of the IC. Typical output voltage transient spike for a step change in the load current from 0mA to 50mA is tens of mV, depending on the ESR of the output capacitor. Increasing the output capacitor's value and decreasing the ESR attenuates the overshoot. Input-Output (Dropout) Voltage A regulator's minimum input-output voltage differential (or dropout voltage) determines the lowest usable supply voltage. In battery-powered systems, this will determine the useful end-of-life battery voltage. Because the BL9180 uses a P-Channel MOSFET pass transistor, the dropout voltage is a function of drain-to-source on resistance [RDS(ON)] multiplied by the load current. Layout Considerations To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the PCB be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND pin of the device. www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 9 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator BL9180 Layout Circuit J1 1 2 3 VIN VIN 2 3 1 VIN 2 J2 3 1 C1 1 2 3 1 2 EN1 VOUT1 VDD GND EN2 VOUT2 BL9180 Rev 2.1 8/2010 5 VOUT1 C2 4 VOUT2 VIN BL9180 C3 3 Top Layer Layout PPMIC BU 6 Bottom Layer Layout www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 10 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator Package Description PPMIC BU BL9180 Rev 2.1 8/2010 www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 11 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator PPMIC BU BL9180 Rev 2.1 8/2010 www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 12 BL9180 Dual,3 Dual,300mA UltraUltra-low Noise CMOS LDO Regulator ESOP-8 Symbol A A1 A2 A3 b b1 c c1 D E E1 e L L1 Θ D1 E2 Dimensions In Millimeters Min NOM 0.08 1.2 0.55 0.39 0.38 0.21 0.19 4.7 5.8 3.7 0.18 1.4 0.65 0.5 0.41 0.2 4.9 6 3.9 1.27BSC 0.65 1.05BSC 0 Max 1.77 0.28 1.6 0.75 0.48 0.43 0.26 0.21 5.1 6.2 4.1 0.8 8° 3.30REF 2.40REF ESOP-8 Surface Mount Package PPMIC BU BL9180 Rev 2.1 8/2010 www.belling.com.cn Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited ©2010 Belling All Rights Reserved 13