Shanghai Belling Corp., Ltd BL93C46 BL93C46 1K bits (128 X 8 or 64 X 16) Three-wire Serial EEPROM Features Three-wire Serial Interface VCC = 1.8V to 5.5V 2 MHz Rate (5V) Compatibility Self-timed Write Cycle (5 ms max) 1 Million Write Cycles guaranteed Data Retention > 100 Years 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP Packages Description The BL93C46 provides 1024 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 64 words of 16 bits each, when the ORG pin is connected to VCC and 128 words of 8 bits each when it is tied to ground. TheBL93C46 is available in space-saving 8-lead PDIP, 8-lead TSSOP and 8-lead JEDEC SOIC packages. The BL93C46 is enabled through the Chip Select pin (CS), and accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The WRITE cycle is completely self-timed and no separate erase cycle is required before write. The Write cycle is only enabled when it is in the Erase/Write Enable state. When CS is brought “high” following the initiation of a write cycle, the DO pin outputs the Ready/Busy status. Order information Part Number Package shipping BL93C46-DIP PDIP8 tube BL93C46-SOP SOP8 tube；2500 pcs / Tape & Reel BL93C46-TSSOP TSSOP8 tube；3000 pcs / Tape & Reel 1 Shanghai Belling Corp., Ltd BL93C46 Pin Descriptions Block Diagram 2 Shanghai Belling Corp., Ltd BL93C46 Electrical Characteristics 3 Shanghai Belling Corp., Ltd BL93C46 AC Electrical Characteristics 4 Shanghai Belling Corp., Ltd BL93C46 Functional Description The BL93C46 is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic“1”) followed by the appropriate op code and the desired memory address location. READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable(EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). A logic “1” at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the selftimed programming cycle, TWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is 5 Shanghai Belling Corp., Ltd BL93C46 brought high after being kept low for a minimum of 250 ns (TCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (TCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. Timing Diagrams 6 Shanghai Belling Corp., Ltd BL93C46 7 Shanghai Belling Corp., Ltd BL93C46 8 Shanghai Belling Corp., Ltd BL93C46 Package Information 8-lead PDIP Outline Dimensions MILLIMETER SYMBOL MIN NOM MAX A 3.60 3.80 4.00 A2 3.10 3.30 3.50 b 0.44 - 0.53 B1 1.52BSC c 0.25 - 0.31 c1 0.24 0.25 0.26 D 9.05 9.25 9.45 E1 6.15 6.35 6.55 e 2.54BSC eA 7.62BSC L 3.00 - - 9 Shanghai Belling Corp., Ltd BL93C46 8-lead SOIC Outline Dimensions SYMBOL MILLIMETER MIN NOM MAX A - - 1.77 A1 0.08 0.18 0.28 b 0.44 - 0.53 c 0.21 - 0.26 D 4.70 4.90 5.10 E 5.80 6.00 6.20 E1 3.70 3.90 4.10 e Θ 1.27BSC 0 - 8° 10 Shanghai Belling Corp., Ltd BL93C46 8-lead TSSOP Outline Dimensions SYMBOL MILLIMETER MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.90 1.00 1.05 A3 0.34 0.44 0.54 b 0.20 - 0.28 b1 0.20 0.22 0.24 c 0.10 - 0.19 c1 0.10 0.13 0.15 D 2.83 2.93 3.03 E 6.20 6.40 6.60 11 Shanghai Belling Corp., Ltd E1 4.30 e L BL93C46 4.40 4.50 0.65BSC 0.45 0.60 L1 1.00REF L2 0.25BSC 0.75 R 0.09 - - R1 0.09 - - S 0.20 - - Θ1 0° - 8° Θ2 10° 12° 14° Θ3 10° 12° 14° 12