54ABT652 Octal Transceivers and Registers with TRI-STATE ® Outputs General Description The ’ABT652 consists of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. n Multiplexed real-time and stored data n A and B output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9324201 Features n Independent registers for A and B buses Ordering Code: Commercial Package Package Description Number 54ABT652J-QML J24A 24-Lead Ceramic Dual-in-line 54ABT652W-QML W24C 24-Lead Cerpack 54ABT652E-QML E28A 28-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagram Pin Assignment for DIP and Flatpack DS100220-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100220 www.national.com 54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs August 1998 Connection Diagram (Continued) Pin Assignment for LCC DS100220-48 www.national.com 2 Pin Descriptions Pin Names Description A0–A7 Data Register A Inputs/TRI-STATE Outputs B0–B7 Data Register B Inputs/TRI-STATE Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Select Inputs OEAB, OEBA Output Enable Inputs Logic Diagram DS100220-3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Functional Description ate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the ’ABT652C. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropri- 3 www.national.com Functional Description (Continued) Note C: Storage Note A: Real-Time Transfer Bus B to Bus A DS100220-6 DS100220-4 OEAB OEBA CPAB CPBA SAB SBA OEAB OEBA CPAB CPBA SAB SBA X H N X X X L L X X X L L X X N X X L H N N X X Note D: Transfer Storage Data to A or B Note B: Real-Time Transfer Bus A to Bus B DS100220-7 DS100220-5 OEAB OEBA CPAB CPBA SAB SBA H H X X L X OEAB OEBA CPAB CPBA SAB SBA H L H or L H or L H H FIGURE 1. www.national.com 4 Functional Description (Continued) Inputs Inputs/Outputs (Note 1) OEAB OEBA CPAB CPBA L H H or L H or L X X L H N N X X X H N H or L X H H N N L X H or L N L L N L L L L H SAB SBA A0 thru A7 Operating Mode B0 thru B7 Input Input Isolation X Input Not Specified Store A, Hold B X X Input Output Store A in Both Registers X X Not Specified Input Hold A, Store B N X X Output Input Store B in Both Registers X X X L Output Input Real-Time B Data to A Bus X H or L X H H X X L X Input Output Real-Time A Data to B Bus H H H or L X H X H L H or L H or L H H Output Output Stored A Data to B Bus and Store A and B Data Store B Data to A Bus Stored A Data to B Bus Stored B Data to A Bus H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW to HIGH Clock Transition Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs. 5 www.national.com Absolute Maximum Ratings (Note 2) Over Voltage Latchup (I/O) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current −65˚C to +150˚C −55˚C to +125˚C Recommended Operating Conditions −55˚C to +175˚C Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input Clock Input −0.5V to +7.0V −0.5V to +7.0V −30 mA to +5.0 mA −0.5V to +5.5V −0.5V to VCC 10V −55˚C to +125˚C +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns 100 mV/ns Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. twice the rated IOL (mA) −500 mA Note 3: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter ABT652 Min Typ Units VCC Conditions Max VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min V Min Recognized LOW Signal IIN = −18 mA (Non I/O Pins) IOH = −3 mA, (An, Bn) 0.55 V Min IOH = −24 mA, (An, Bn) IOL = 48 mA, (An, Bn) Input HIGH Current 2 µA Max Input HIGH Current 7 µA Max VIN = 2.7V (Non-I/O Pins) (Note 4) VIN = VCC (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) 100 µA Max VIN = 5.5V (An, Bn) VOH VOL 2.0 Output HIGH 54ABT 2.5 Voltage 54ABT 2.0 Output LOW 54ABT V Recognized HIGH Signal Voltage IIH IBVI Breakdown Test IBVIT Input HIGH Current Breakdown Test (I/O) IIL Input LOW Current −2 µA Max IIH + IOZH Output Leakage Current 50 µA 0V–5.5V VIN = 0.5V (Non-I/O Pins) (Note 4) VIN = 0.0V (Non-I/O Pins) VOUT = 2.7V (An, Bn); IIL + IOZL Output Leakage Current −50 µA 0V–5.5V OEBA = 2.0V and OEAB = GND = 2.0V VOUT = 0.5V (An, Bn); IOS Output Short-Circuit Current −180 mA Max OEBA = 2.0V and OEAB = GND = 2.0V VOUT = 0V (An, Bn) −50 ICEX Output HIGH Leakage Current 50 µA Max VOUT = VCC (An, Bn) ICCH Power Supply Current 250 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 250 µA Max Outputs TRI-STATE; ICCT Additional ICC/Input 2.5 mA Max All others at VCC or GND VI = VCC − 2.1V All others at VCC or GND Note 4: Guaranteed but not tested. Note 5: For 8 outputs toggling, ICCD < 1.4 mA/MHz. Note 6: Guaranteed, but not tested. www.national.com 6 DC Electrical Characteristics Symbol Parameter Max Units VCC VOLP Quiet Output Maximum Dynamic VOL 1.2 V 5.0 VOLV Quiet Output Minimum Dynamic VOL -1.8 V 5.0 Conditions CL = 50 pF, RL = 500Ω TA = 25˚C (Note 7) TA = 25˚C (Note 7) Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. AC Electrical Characteristics Symbol 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V Parameter Fig. Units No. CL = 50 pF Min Max fmax Max Clock Frequency 125 tPLH Propagation Delay 1.4 7.8 tPHL Clock to Bus 1.2 8.4 tPLH Propagation Delay 1.5 6.7 tPHL Bus to Bus 1.5 6.7 tPLH Propagation Delay 1.2 6.9 tPHL SBA or SAB to An to Bn 1.2 7.7 tPZH Enable Time 1.3 5.6 MHz tPZL OEBA or OEAB to An or Bn 2.0 7.8 tPHZ Disable Time 1.5 8.2 tPLZ OEBA or OEAB to An or Bn 1.5 7.3 ns Figure 5 ns Figure 5 ns Figure 5 ns Figure 7 ns Figure 7 AC Operating Requirements Symbol 54ABT TA = −55˚C to +125˚C VCC = 4.5V–5.5V Parameter Fig. Units No. 3.5 ns Figure 8 1.5 ns Figure 8 4.0 ns Figure 6 CL = 50 pF Min tS(H) Setup Time, HIGH tS(L) or LOW Bus to Clock tH(H) Hold Time, HIGH tH(L) or LOW Bus to Clock tW(H) Pulse Width, tW(L) HIGH or LOW Max 7 www.national.com Capacitance Symbol Parameter Max Units CIN Input Capacitance 14.0 pF CI/O (Note 8) I/O Capacitance 19.5 pF Note 8: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883D, Method 3012. www.national.com 8 Conditions (TA = 25˚C) VCC = 0V (non I/O pins) VCC = 5.0V (An, Bn) Capacitance (Continued) tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching Clock to Bus tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching Clock to Bus DS100220-16 tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Bus DS100220-17 tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching Bus to Bus DS100220-18 tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching SBA or SAB to An or Bn DS100220-19 tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching SBA or SAB to An or Bn DS100220-20 DS100220-21 9 www.national.com Capacitance (Continued) tPLH vs Load Capacitance 1 Output Switching, TA = 25˚C Clock to Bus tPHL vs Load Capacitance 1 Output Switching, TA = 25˚C Clock to Bus DS100220-22 tPLH vs Load Capacitance 1 Output Switching, TA = 25˚C Bus to Bus DS100220-23 tPHL vs Load Capacitance 1 Output Switching, TA = 25˚C Bus to Bus DS100220-24 tPLH vs Load Capacitance 1 Output Switching, TA = 25˚C SBA or SAB to An or Bn DS100220-25 tPHL vs Load Capacitance 1 Output Switching, TA = 25˚C SBA or SAB to An or Bn DS100220-26 www.national.com DS100220-27 10 Capacitance (Continued) tPLH vs Load Capacitance 8 Outputs Switching, TA = 25˚C Clock to Bus tPHL vs Load Capacitance 8 Outputs Switching, TA = 25˚C Clock to Bus DS100220-28 tPLH vs Load Capacitance 8 Outputs Switching, TA = 25˚C Bus to Bus DS100220-29 tPHL vs Load Capacitance 8 Outputs Switching, TA = 25˚C Bus to Bus DS100220-30 tPLH vs Load Capacitance 8 Outputs Switching, TA = 25˚C SBA or SAB to An or Bn DS100220-31 tPHL vs Load Capacitance 8 Outputs Switching, TA = 25˚C SBA or SAB to An or Bn DS100220-32 DS100220-33 11 www.national.com Capacitance (Continued) tPZL vs Temperature (TA) CL = 50 pF, 1 Output Switching tPLZ vs Temperature (TA) CL = 50 pF, 1 Output Switching DS100220-35 DS100220-34 tPZH vs Temperature (TA) CL = 50 pF, 1 Output Switching tPHZ vs Temperature (TA) CL = 50 pF, 1 Output Switching DS100220-36 tPZH vs Temperature (TA) CL = 50 pF, 8 Outputs Switching DS100220-37 tPHZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching DS100220-38 www.national.com DS100220-39 12 Capacitance (Continued) tPZL vs Temperature (TA) CL = 50 pF, 8 Outputs Switching tPLZ vs Temperature (TA) CL = 50 pF, 8 Outputs Switching DS100220-40 tPZL vs Load Capacitance 8 Outputs Switching TA = 25˚C DS100220-41 tPZH vs Load Capacitance 8 Outputs Switching TA = 25˚C DS100220-42 tPLH and tPHL vs Number Output Switching VCC = 5V, TA = 25˚C, CL = 50 pF Clock to Bus DS100220-43 tPLH and tPHL vs Number Output Switching VCC = 5V, TA = 25˚C, CL = 50 pF Bus to Bus DS100220-44 DS100220-45 13 www.national.com Capacitance (Continued) tPLH and tPHL vs Number Output Switching VCC = 5V, TA = 25˚C, CL = 50 pF SBA or SAB to Anor Bn DS100220-46 www.national.com 14 AC Loading DS100220-8 *Includes jig and probe capacitance FIGURE 2. Standard AC Test Load DS100220-9 FIGURE 6. Propagation Delay, Pulse Width Waveforms DS100220-10 DS100220-11 FIGURE 3. Test Input Signal Levels FIGURE 7. TRI-STATE Output HIGH and LOW Enable and Disable Times Input Pulse Requirements Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 4. Test Input Signal Requirements DS100220-13 FIGURE 8. Setup Time, Hold Time and Recovery Time Waveforms DS100220-12 FIGURE 5. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 15 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Ceramic Dual-in-line NS Package Number J24A 24-Lead Cerpack NS Package Number W24C www.national.com 16 54ABT652 Octal Transceivers and Registers with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Ceramic Leadless Chip Carrier, Type C NS Package Number E28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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