January 2000 COP840CJ/COP842CJ/COP940CJ/COP942CJ 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector General Description The COP840CJ is a member of the COP8™feature family 8-bit microcontroller. It is a fully static Microcontroller, fabricated using double-metal silicon gate microCMOS technology. This low cost microcontroller is a complete microcomputer containing all system timing, interrupt logic, ROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications. Features include an 8-bit memory mapped architecture, MICROWIRE™ serial I/O, a 16-bit timer/counter with capture register, a multi-sourced interrupt, Comparator, WATCHDOG™ Timer, Modulator/Timer, Brown out detection and Multi Input Wake-up. Each I/O pin has software selectable options to adapt the device to the specific application. The device operates over a voltage range of 2.5V–6.0V. High throughput is achieved with an efficient, regular instruction set operating at a 1 ms per instruction rate. Low radiated emissions are achieved by gradual turn on output drivers and internal ICC filters on the chip logic and crystal oscillator. Features Multi-Input wake-up (on the 8-bit Port L) Brown out detection Analog comparator Modulator/Timer (high speed PWM timer for IR transmission) n 16-bit multi-function timer supporting — PWM mode — External event counter mode — Input capture mode n Quiet design (low radiated emissions) n n n n Integrated capacitor for the R/C oscillator 2048 bytes of ROM 128 bytes of RAM Memory mapped I/O Software selectable I/O options (TRI-STATE ® , push-pull, weak pull-up input, high impedance input) n High current outputs (8 pins) n Schmitt trigger inputs on Port G n MICROWIRE/PLUS™ serial I/O n Packages: 20 DIP/SO with 16 I/O pins 28 DIP/SO with 24 I/O pins n 1 µs instruction cycle time n Three multi-source interrupts servicing — External interrupt with selectable edge — Timer interrupt — Software interrupt n Versatile and easy to use instruction set n 8-bit Stack Pointer (SP) — stack in RAM n Two 8-bit register indirect data memory pointers (B and X) Fully Static CMOS n Low current drain (typically < 1 µA) n Single supply operation: 2.5V to 6.0V n Temperature ranges: 0˚C to +70˚C, −40˚C to +85˚C −55˚C to +125˚C Development Support n Emulation and OTP devices n Real time emulation and full program debug offered by MetaLink’s development system n n n n n TRI-STATE ® is a registered trademark of National Semiconductor Corporation. WATCHDOG™, MICROWIRE/PLUS™, COP8™, and MICROWIRE™ are trademarks of National Semiconductor Corporation. iceMASTER™ is a trademark of MetaLink Corporation. © 2000 National Semiconductor Corporation DS012851 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector OBSOLETE COP840CJ/COP842CJ/COP940CJ/COP942CJ Block Diagram DS012851-1 Connection Diagrams DS012851-3 Top View Order Number COP842CJ-XXX/N or COP842CJ-XXX/M COP942CJ-XXX/N or COP942CJ-XXX/M See NS Package Number N20A or M20B DS012851-2 Top View Order Number COP840CJ-XXX/N or COP840CJ-XXX/M, COP940CJ-XXX/N or COP940CJ-XXX/M See NS Package Number N28B or M28B FIGURE 1. Connection Diagrams www.national.com 2 COP840CJ/COP842CJ/COP940CJ/COP942CJ Pin Assignment Port Type PIN L0 ALT 20-Pin 28-Pin 7 11 8 12 9 13 Funct. I/O MIWU/ CMPOUT L1 I/O L2 I/O MIWU/ CMPIN− MIWU/ CMPIN+ L3 I/O MIWU 10 14 L4 I/O MIWU 11 15 L5 I/O MIWU 12 16 L6 I/O MIWU 13 17 L7 I/O MIWU/ 14 18 17 25 MODOUT G0 I/O INTR G1 I/O 18 26 G2 I/O 19 27 G3 I/O TIO 20 28 G4 I/O SO 1 1 G5 I/O SK 2 2 G6 I SI 3 3 G7 I CKO 4 4 I0 I 7 I1 I 8 I2 I 9 I3 I 10 D0 O 19 D1 O 20 D2 O 21 D3 O 22 VCC 6 6 GND 15 23 CKI 5 5 RESET 16 24 3 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Absolute Maximum Ratings (Note 1) Total Current into VCC Pin (source) Total Current out of GND Pin (sink) Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at Any Pin 80 mA 80 mA −65˚C to +150˚C Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. 7.0V −0.3V to VCC +0.3V DC Electrical Characteristics COP94x 0˚C ≤ TA ≤ +70˚C unless otherwise specified Parameter Condition Min Brown Out Disabled 2.5 Typ Max Units 4.5 V Operating Voltage COP94xCJ COP94xCJH Power Supply Ripple (Note 2) Supply Current (Notes 3, 6) CKI = 10 MHz, R = 2.2k CKI = 4 MHz, R = 4.7k CKI = 4 MHz, R = 4.7k CKI = 1 MHz, R = 20k HALT Current with Brown Out 4.5 Peak-to-Peak VCC = 6V, tC = 1 µs VCC = 6V, tC = 2.5 µs VCC = 4.5V, tC = 2.5 µs 6.0 V 0.1 VCC V 8.0 mA 6.0 mA 2.5 mA = 4.5V, tC = 10 µs = 6V, CKI = 0 MHz 1.5 mA < 2.2 8 µA VCC = 6V, CKI = 0 MHz < 50 100 µA 3.1 3.9 V VCC VCC Disabled (Note 4) HALT Current with Brown Out Enabled Brown Out Trip Level 1.9 (Brown Out Enabled) INPUT LEVELS (VIH, VIL) Reset, CKI: Logic High 0.8 VCC V Logic Low 0.2 VCC V All Other Inputs Logic High 0.7 VCC V Logic Low 0.2 VCC Hi-Z Input Leakage VCC Input Pullup Current VCC = 6.0V = 6.0V V −2 +2 µA −40 −250 µA 0.35 VCC V L- and G-Port Hysteresis 0.05 VCC Output Current Levels D Outputs: Source Sink L4–L7 Output Sink VCC = 4.5V, VOH = 3.8V VCC = 2.5V, VOH = 1.8V VCC = 4.5V, VOL = 1.0V VCC = 2.5V, VOH = 0.4V −0.4 mA −0.2 mA VCC = 4.5V, VOL = 2.5V 10 mA 2 mA 15 mA All others Source (Weak Pull-up Mode) Sink (Push-Pull Mode) VCC = 4.5V, VOH = 3.2V VCC = 2.5V, VOH = 1.8V VCC = 4.5V, VOL = 0.4V VCC = 2.5V, VOL = 0.4V −110 µA −33 µA 1.6 mA 0.7 TRI-STATE Leakage www.national.com −10 −2.5 −2.0 4 mA +2.0 µA (Continued) 0˚C ≤ TA ≤ +70˚C unless otherwise specified Parameter Condition Min Typ Max Units D Outputs 15 mA L4–L7 (sink) 20 mA All Others 3 mA ± 100 mA Allowable Sink/Source Current per Pin Maximum Input Current without Latchup (Note 5) RAM Retention Voltage, Vr 2.0 500 ns Rise and Fall Time (min) V Input Capacitance Load Capacitance on D2 Note 2: Rate of voltage change must be 7 pF 1000 pF < 10V/ms. Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 4: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. HALT test conditions: L, and G0..G5 ports configured as outputs and set high. The D port set to zero. All inputs tied to VCC. The comparator and the Brown Out circuits are disabled. Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. Note 6: The Resistor values are for R/C only. AC Electrical Characteristics COP94x 0˚C ≤ TA ≤ +70˚C unless otherwise specified Parameter Condition Min Typ Max Units Instruction Cycle Time (tC) Crystal/Resonator R/C Oscillator 4.5V ≤ VCC < 6.0V 1 DC µs 2.5V ≤ VCC < 4.5V 2.5 DC µs 4.5V ≤ VCC < 6.0V 2 DC µs 5 DC 2.5V ≤ VCC < 4.5V VCC Rise Time when Using Brown Out 50 µs µs Frequency at Brown Out Reset 4 MHz CKI Frequency for Modulator Output 4 MHz fr = Max fr = 10 MHz ext. clock fr = 10 MHz ext. clock 40 4.5V ≤ VCC < 6.0 200 ns 2.5V ≤ VCC < 4.5 500 ns tHold 4.5V ≤ VCC < 6.0 60 ns 2.5V ≤ VCC < 4.5 RL = 2.2k, CL = 100 pF 150 ns Output Propagation Delay CKI Clock Duty Cycle (Note 7) Rise Time (Note 7) Fall Time (Note 7) 60 % 12 ns 8 ns Inputs tSetup tPD1, tPD0 SO, SK All Others 4.5V ≤ VCC < 6.0 0.7 µs 2.5V ≤ VCC < 4.5 1.75 µs 4.5V ≤ VCC < 6.0 1 µs 2.5V ≤ VCC < 4.5 5 µs Input Pulse Width 1 tC Interrupt Input High Time 1 tC Interrupt Input Low Time 1 tC Timer Input High Time 1 tC Timer Input Low Time 1 tC 5 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ DC Electrical Characteristics COP94x COP840CJ/COP842CJ/COP940CJ/COP942CJ AC Electrical Characteristics COP94x (Continued) 0˚C ≤ TA ≤ +70˚C unless otherwise specified Parameter Condition Min Typ Max Units MICROWIRE Setup Time (tµWS) 20 ns MICROWIRE Hold Time (tµWH) 56 ns MICROWIRE Output Propagation Delay (tµPD) 220 Reset Pulse Width 1.0 Note 7: Parameter sampled but not 100% tested. www.national.com 6 ns µs Total current into VCC pin (source) Total current out of GND pin (sink) Storage Temperature Range If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) Voltage at any Pin 80 mA 80 mA −65˚C to +150˚C Note 8: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. 7.0V −0.3V to VCC +0.3V DC Electrical Characteristics COP84x −40˚C ≤ TA ≤ +85˚C unless otherwise specified Parameter Condition Operating Voltage Brown Out disabled Power Supply Ripple (Note 9) Peak-to-Peak Supply Current (Notes 10, 13) CKI = 10 MHz, R = 2.2k CKI = 4 MHz, R = 4.7k CKI = 4 MHz, R = 4.7k CKI = 1 MHz, R = 20k HALT Current with Brown Out Min Typ 2.5 VCC = 6V, tC = 1 µs VCC = 6V, tC = 2.5 µs VCC = 4.5V, tC = 2.5 µs VCC = 4.5V, tC = 10 µs Max Units 6.0 V 0.1 VCC V 8.0 mA 6.0 mA 2.5 mA 1.5 mA VCC = 6V, CKI = 0 MHz < 2.5 10 µA VCC = 6V, CKI = 0 MHz < 50 100 µA 3.1 4.2 V Disabled (Note 10) HALT Current with Brown Out Enabled Brown Out Trip Level 1.8 (Brown Out Enabled) INPUT LEVELS (VIH, VIL) Reset, CKI: Logic High 0.8 VCC V Logic Low 0.2 VCC V All Other Inputs Logic High 0.7 VCC V Logic Low Hi-Z Input Leakage Input Pullup Current VCC = 6.0V VCC = 6.0V 0.2 VCC V −2 +2 µA −40 −250 µA 0.35 VCC V L- and G-Port Hysteresis 0.05 VCC Output Current Levels D Outputs: −0.4 Sink VCC = 4.5V, VOH = 3.8V VCC = 2.5V, VOH = 1.8V VCC = 4.5V, VOL = 1.0V L4–L7 Output Sink VCC = 2.5V, VOH = 0.4V VCC = 4.5V, VOL = 2.5V Source mA −0.2 mA 10 mA 2 mA 15 mA All Others Source (Weak Pull-Up Mode) Sink (Push-Pull Mode) VCC = 4.5V, VOH = 3.2V VCC = 2.5V, VOH = 1.8V VCC = 4.5V, VOL = 0.4V −10 −110 −2.5 −33 1.6 VCC = 2.5V, VOL = 0.4V −2.0 µA mA 0.7 TRI-STATE Leakage µA mA +2.0 µA D Outputs 15 mA L4–L7 (sink) 20 mA All Others 3 mA Allowable Sink/Source Current per Pin 7 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Absolute Maximum Ratings (Note 8) COP840CJ/COP842CJ/COP940CJ/COP942CJ DC Electrical Characteristics COP84x (Continued) −40˚C ≤ TA ≤ +85˚C unless otherwise specified Parameter Condition Min Typ Maximum Input Current Max Units ± 100 mA 7 pF 1000 pF without Latchup (Note 12) RAM Retention Voltage, Vr 500 ns Rise and Fall Time (min) 2.0 V Input Capacitance Load Capacitance on D2 Note 9: Rate of voltage change must be < 10V/ms. Note 10: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open. Note 11: The HALT mode will stop CKI from oscillating in the RC and crystal configurations. HALT test conditions: L, and G0..G5 ports configured as outputs and set high. The D port set to zero. All inputs tied to VCC. The comparator and the Brown Out circuits are disabled. Note 12: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages greater than VCC and the pins will have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to < 14V. Note 13: The Resistor values are for R/C only. AC Electrical Characteristics COP84x −40˚C ≤ TA ≤ +85˚C unless otherwise specified. Parameter Condition Min Typ Max Units Instruction Cycle Time (tC) Crystal/Resonator R/C Oscillator 4.5V ≤ VCC < 6.0V 1 DC µs 2.5V ≤ VCC < 4.5V 2.5 DC µs 4.5V < VCC < 6.0V 2 DC µs 5 DC 2.5V ≤ VCC < 4.5V VCC Rise Time when Using Brown Out 50 Frequency at Brown Out Reset CKI Frequency for Modulator Output CKI Clock Duty Cycle (Note 14) Rise Time (Note 14) Fall Time (Note 14) µs µs 4 MHz 4 MHz fr = Max fr = 10 MHz ext. clock fr = 10 MHz ext. clock 40 4.5V ≤ VCC < 6.0V 200 ns 2.5V ≤ VCC < 4.5V 500 ns 60 % 12 ns 8 ns Inputs tSetup tHold 4.5V ≤ VCC < 6.0V 60 ns 150 ns Output Propagation Delay 2.5V ≤ VCC < 4.5V RL = 2.2k, CL = 100 pF tPD1, tPD0 SO, SK All Others 4.5V ≤ VCC < 6.0V 0.7 µs 2.5V ≤ VCC < 4.5V 1.75 µs 4.5V ≤ VCC < 6.0V 1 µs 5 µs 2.5V ≤ VCC < 4.5V Input Pulse Width 1 tC Interrupt Input High Time 1 tC Interrupt Input Low Time 1 tC Timer Input High Time 1 tC Timer input low time 1 tC MICROWIRE Setup Time (tµWS) 20 ns MICROWIRE Hold Time (tµWH) 56 ns MICROWIRE Output Propagation Delay (tµPD) 220 Reset Pulse Width 1.0 Note 14: Parameter sampled but not 100% tested. www.national.com 8 ns µs COP840CJ/COP842CJ/COP940CJ/COP942CJ AC Electrical Characteristics COP84x (Continued) DS012851-4 FIGURE 2. MICROWIRE/PLUS Timing Typical Performance Characteristics (−40˚C ≤ TA ≤ +85˚C) Port D Sink Current Halt Current with Brown Out Disabled DS012851-5 DS012851-6 Halt Current with Brown Out Enabled Halt Current with Comparator Enabled DS012851-8 DS012851-7 9 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Typical Performance Characteristics (−40˚C ≤ TA ≤ +85˚C) (Continued) Ports L/G Push-Pull Source Current Ports L/G Push-Pull Sink Current DS012851-9 Port D Source Current DS012851-10 Port D Sink Current DS012851-12 DS012851-11 Brown Out Voltage vs Temperature DS012851-13 www.national.com 10 VCC and GND are the power supply pins. CKI is the clock input. This can come from an external source, a R/C generated oscillator or a crystal (in conjunction with CKO). See Oscillator description. Config. Data 0 0 Hi-Z input (TRI-STATE) 0 1 Input with weak pull-up 1 0 Push-pull zero output 1 1 Push-pull one output Port L Setup Port G Port G PORT G Data Setup 0 0 Hi-Z input (TRI-STATE) 0 1 Input with weak pull-up 1 0 Push-pull zero output 1 1 Push-pull one output SO (MICROWIRE serial data output) G5 SK (MICROWIRE clock I/O) G6 SI (MICROWIRE serial data input) Note: Care must be exercised with the D2 pin operation. At RESET, the external loads on this pin must ensure that the output voltages stay above 0.8 VCC to prevent the chip from entering special modes. Also keep the external loading on D2 to < 1000 pF. Functional Description Three data memory address locations are allocated for this port, one each for data register [00D0], configuration register [00D1] and the input pins [00D2]. Port L has the following alternate features: L0 MIWU or CMPOUT L1 MIWU or CMPIN− L2 MIWU or CMPIN+ L3 MIWU L4 MIWU (high sink current capability) L5 MIWU (high sink current capability) L6 MIWU (high sink current capability) L7 MIWU or MODOUT (high sink current capability) The selection of alternate Port L functions is done through registers WKEN [00C9] to enable MIWU, and CNTRL2 [00CC] to enable comparator and modulator. All eight L-pins have Schmitt Triggers on their inputs. PORT G is an 8-bit port with 6 I/O pins (G0–G5) and 2 input pins (G6, G7). All eight G-pins have Schmitt Triggers on the inputs. There are two registers associated with the G port: a data register and a configuration register. Therefore each G port bit can be individually configured under software control as shown below: Config. G4 CKO crystal oscillator output (selected by mask option) or HALT restart input/general purpose input (if clock option is R/C- or external clock) Pins G1 and G2 currently do not have any alternate functions. The selection of alternate Port G functions is done through registers PSW [00EF] to enable external interrupt, and CNTRL1 [00EE] to select TIO and MICROWIRE operations. PORT D is a four bit output port that is preset high when RESET goes low. One data memory address location is allocated for the data register [00DC]. PORT I is a 4-bit Hi-Z input port. PORT L is an 8-bit I/O port. There are two registers associated with the L port: a data register and a configuration register. Therefore, each L I/O bit can be individually configured under software control as shown below: PORT L TIO (timer/counter input/output) G7 RESET is the master reset input. See Reset description. Port L G3 The internal architecture is shown in the block diagram. Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implementing the instruction set of the device. ALU AND CPU REGISTERS The ALU can do an 8-bit addition, subtraction, logical or shift operations in one cycle time. There are five CPU registers: A is the 8-bit Accumulator register PC is the 15-bit Program Counter register. PU is the upper 7 bits of the program counter (PC). PL is the lower 8 bits of the program counter (PC). B is the 8-bit address register and can be auto incremented or decremented. X is the 8-bit alternate address register and can be auto incremented or decremented. SP is the 8-bit stack pointer which points to the subroutine stack (in RAM). B, X and SP registers are mapped into the on-chip RAM. The B and X registers are used to address the on-chip RAM. The SP register is used to address the stack in RAM during subroutine calls and returns. The SP must be initialized by software before any subroutine call or interrupts occur. MEMORY The memory is separated into two memory spaces: program and data. PROGRAM MEMORY Program memory consists of 2048 x 8 ROM. These bytes of ROM may hold instructions or constant data. The memory is addressed by the 15-bit program counter (PC). ROM can be indirectly read by the LAID instruction for table lookup. Three data memory address locations are allocated for this port, one for data register [00D4], one for configuration register [00D5] and one for the input pins [00D6]. Since G6 and G7 are Hi-Z input only pins, any attempt by the user to configure them as outputs by writing a one to the configuration register will be disregarded. Reading the G6 and G7 configuration bits will return zeros. Note that the device will be placed in the Halt mode by writing a “1” to the G7 data bit. Six pins of Port G have alternate features: G0 INTR (an external interrupt) DATA MEMORY The data memory address space includes on-chip RAM, I/O and registers. Data memory is addressed directly by instructions or indirectly through the B, X and SP registers. The device has 128 bytes of RAM. Sixteen bytes of RAM are mapped as “registers”, these can be loaded immediately, 11 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Pin Descriptions COP840CJ/COP842CJ/COP940CJ/COP942CJ Functional Description The device comes out of the HALT mode when the RESET pin is pulled low. In this case, the user has to ensure that the RESET signal is low long enough to allow the oscillator to restart. An internal 256 tC delay is normally used in conjunction with the two pin crystal oscillator. When the device comes out of the HALT mode through Multi-Input Wake-up, this delay allows the oscillator to stabilize. (Continued) decremented and tested. Three specific registers: X, B, and SP are mapped into this space, the other registers are available for general usage. The instruction set permits any bit in memory to be directly set, reset or tested. All I/O and registers (except A and PC) are memory mapped; therefore, I/O bits and register bits can be directly and individually set, reset and tested; except the write once only bit (WDREN, WATCHDOG Reset Enable), and the unused and read only bits in the CNTRL2 and WDREG registers. The following additional actions occur after the device comes out of the HALT mode via the RESET pin. If a two pin crystal/resonator oscillator is being used: RAM Contents: Note: RAM contents are undefined upon power-up. Reset TRI-STATE Port D HIGH PC CLEARED RAM Contents RANDOM with Power On Reset UNCHANGED WATCHDOG Timer CHANGED The external RESET takes priority over the Brown Out Reset. Note: If the RESET pin is pulled low while Brown Out occurs (Brown Out circuit has detected Brown Out condition), the external reset will not occur until the Brown Out condition is removed. External reset has priority only if VCC is greater than the Brown Out Voltage. WATCHDOG RESET With WATCHDOG enabled, the WATCHDOG logic resets the device if the user program does not service the WATCHDOG timer within the selected service window. The WATCHDOG reset does not disable the WATCHDOG. Upon WATCHDOG reset, the WATCHDOG Prescaler/Counter are each initialized with FF Hex. The following actions occur upon WATCHDOG reset that are different from external reset. WDREN WATCHDOG Reset Enable bit UNCHANGED WDUDF WATCHDOG Underflow bit UNCHANGED Additional initialization actions that occur as a result of WATCHDOG reset are as follows: UNAFFECTED with external Reset (power already applied) B, X, SP Same as RAM PSW, CNTRL1, CNTRL2 CLEARED and WDREG Reg. Multi-Input Wake-up Reg. CLEARED UNKNOWN CLEARED Registers for L and G WATCHDOG Timer UNCHANGED Timer T1 and A Contents: Initialization Port G Data and Configuration RAM Contents: Prescaler/Counter: TRI-STATE (WKPND) CHANGED Prescaler/Counter: Register (WKEDG, WKEN) UNKNOWN WATCHDOG Timer If the external or RC clock option is being used: EXTERNAL RESET The RESET input pin when pulled low initializes the microcontroller. The user must insure that the RESET pin is held low until VCC is within the specified voltage range and the clock is stabilized. An R/C circuit with a delay 5x greater than the power supply rise time is recommended (Figure 3). The device immediately goes into reset state when the RESET input goes low. When the RESET pin goes high the device comes out of reset state synchronously. The device will be running within two instruction cycles of the RESET pin going high. The following actions occur upon reset: Port L UNAFFECTED Timer T1 and A Contents: Prescaler/Counter each loaded with FF Port L: TRI-STATE Port G: TRI-STATE Port D: HIGH PC: CLEARED RAM Contents: RANDOM B, X, SP: UNAFFECTED PSW, CNTRL1 and CNTRL2 CLEARED (except WDUDF Bit) Registers: Multi-Input Wake-up Registers (WKEDG,WKEN): CLEARED (WKPND): UNKNOWN Data and Configuration CLEARED Registers for L and G: WATCHDOG Timer: each loaded with FF DS012851-14 RC > 5 x Power Supply Rise Time FIGURE 3. Recommended Reset Circuit www.national.com Prescaler/Counter 12 The Brown Out circuit may be used as a power-up reset provided the power supply rise time is slower than 50 µs (0V–6.0V). Brown Out should not be used in frequencies over 4 MHz. (Continued) BROWN OUT RESET The on-board Brown Out detection circuit resets the device when the operating voltage (VCC) is lower than the Brown Out voltage. The device is held in reset when VCC stays below the Brown Out voltage. The device will remain in RESET as long as VCCis below the Brown Out Voltage. The device will resume execution if VCC rises above the Brown Out Voltage. If a two pin crystal/resonator clock option is selected, the Brown Out reset will trigger a 256 tc delay. This delay allows the oscillator to stabilize before the device exits the reset state. The delay is not used if the clock option is either R/C or external clock. The contents of data registers and RAM are unknown following a Brown Out reset. The external reset takes priority over Brown Out Reset and will deactivate the 256 tc cycles delay if in progress. The Brown Out reset takes priority over the WATCHDOG reset. The following actions occur as a result of Brown Out reset: Port L: TRI-STATE Port G: TRI-STATE Port D HIGH PC: CLEARED RAM Contents: RANDOM B, X, SP UNKNOWN PSW, CNTRL1, CNTRL2 CLEARED Note: Brown Out Circuit is active in HALT mode (with the Brown Out mask option selected). Oscillator Circuits EXTERNAL OSCILLATOR By selecting the external oscillator option, the CKI pin can be driven by an external clock signal provided it meets the specified duty cycle, rise and fall times, and input levels. The G7/CKO is available as a general purpose input G7 and/or Halt control. CRYSTAL OSCILLATOR By selecting the crystal oscillator option, the G7/CKO pin is connected as a clock output, CKI and G7/CKO can be connected to make a crystal controlled oscillator. Table 1 shows the clock frequency for different component values. See Figure 4 for the connections. R/C OSCILLATOR By selecting the R/C oscillator option, connecting a resistor from the CKI pin to VCC makes a R/C oscillator. The capacitor is on-chip. The G7/CKO pin is available as a general purpose input G7 and/or Halt control. Adding an external capacitor will jeopardize the clock frequency tolerance and increase EMI emissions. and WDREG Registers: Multi-Input Wake-up CLEARED Table 2 shows the clock frequency for the different resistor values. The capacitor is on-chip. See Figure 4 for the connections. Registers (WKEDG, WKEN): (WKPND): UNKNOWN Data and Configuration CLEARED Registers for L and G: WATCHDOG Timer: Prescaler/Counter each loaded with FF Timer T1 and Accumulator: Unknown data after coming out of the HALT (through Brown Out Reset) with any Clock option Note: The Development system will detect the BROWN OUT RESET externally and will force the RESET pin low. The Development System does not emulate the 256 tc delay. Brown Out Detection DS012851-15 FIGURE 4. Clock Oscillator Configurations An on-board detection circuit monitors the operating voltage (VCC) and compares it with the minimum operating voltage specified. The Brown Out circuit is designed to reset the device if the operating voltage is below the Brown Out voltage (between 1.8V–4.2V at −40C to +85C). The Minimum operating voltage for the device is 2.5V with Brown Out disabled, but with Brown Out enabled the device is guaranteed to operate properly down to minimum Brown Out voltage (Max frequency 4 MHz). For temperature range of 0˚C–70˚C the Brown Out voltage is expected to be between 1.9V and 3.9V. The circuit can be enabled or disabled by Brown Out mask option. If the device is intended to operate at lower VCC (lower than Brown Out voltage VBO max), the Brown Out circuit should be disabled by the mask option. 13 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Reset COP840CJ/COP842CJ/COP940CJ/COP942CJ Oscillator Circuits (Continued) TABLE 1. Crystal Oscillator Configuration (TA = 25˚C) R1 (kΩ) R2 (MΩ) C1 (pF) C2 (pF) CKI Freq. (MHz) 0 1 30 30–36 10 0 1 30 30–36 4 5.6 1 200 100–156 0.455 Conditions VCC = 5V VCC = 5V VCC = 5V TABLE 2. R/C Oscillator Configuration (Part- To- Part Variation) R (kΩ) (Note 15) CKI Freq. (MHz) Temp. VCC 2.2 7.0 ± 15% −40˚C − +85˚C 4.5V–5.5V 4.7 4.2 ± 10% −40˚C − +85˚C 4.5V–5.5V 20.0 1.1 ± 10% −40˚C − +85˚C 4.5V–5.5V Note 15: The resistance level is calculated with a total of 5.3 pF capacitance added from the printed circuit board. It is important to take this into account when figuring the clock frequency. HALT Mode The device is a fully static device. The device enters the HALT mode by writing a one to the G7 bit of the G data register. Once in the HALT mode, the internal circuitry does not receive any clock signal and is therefore frozen in the exact state it was in when halted. In this mode the chip will only draw leakage current (output current and DC current due to the Brown Out circuit if Brown Out is enabled). The device supports four different methods of exiting the HALT mode. The first method is with a low to high transition on the CKO (G7) pin. This method precludes the use of the crystal clock configuration (since CKO is a dedicated output). It may be used either with an RC clock configuration or an external clock configuration. The second method of exiting the HALT mode is with the Multi-Input Wake-up feature on the L port. The third method of exiting the HALT mode is by pulling the RESET input low. The fourth method is with the operating voltage going below Brown Out voltage (if Brown Out is enabled by mask option). If the two pin crystal/resonator oscillator is being used and Multi-Input Wake-up or Brown Out causes the device to exit the HALT mode, the WAKE-UP signal does not allow the chip to start running immediately since crystal oscillators have a delayed start up time to reach full amplitude and frequency stability. The WATCHDOG timer (consisting of an 8-bit prescaler followed by an 8-bit counter) is used to generate a fixed delay of 256 tC to ensure that the oscillator has indeed stabilized before allowing instruction execution. In this case, upon detecting a valid WAKE-UP signal only the oscillator circuitry is enabled. The WATCHDOG Counter and Prescaler are each loaded with a value of FF Hex. The WATCHDOG prescaler is clocked with the tC instruction cycle (The tC clock is derived by dividing the oscillator clock down by a factor of 10). The schmitt trigger following the CKI inverter on the chip ensures that the WATCHDOG timer is clocked only when the oscillator has a sufficiently large amplitude to meet the Schmitt trigger specs. This Schmitt trigger is not part of the oscillator closed loop. The start-up time-out from the WATCHDOG timer enables the clock signals to be routed to the rest of the chip. The delay is not activated when the device comes out of HALT mode through RESET pin. Also, if the clock option is either RC or External clock, the delay is not used, but the WATCHDOG Prescaler/ Counter contents are changed. The Development System will not emulate the 256 tC delay. www.national.com The RESET pin or Brown Out will cause the device to reset and start executing from address X’0000. A low to high transition on the G7 pin (if single pin oscillator is used) or Multi-Input Wake-up will cause the device to start executing from the address following the HALT instruction. When RESET/pin is used to exit the device from the HALT mode and the two pin crystal/resonator (CKI/CKO) clock option is selected the contents of the Accumulator and the Timer T1 are undetermined following the reset. All other information except the WATCHDOG Prescaler/Counter contents is retained until continuing. If the device comes out of the HALT mode through Brown Out reset, the contents of data registers and RAM are unknown following the reset. All information except the WATCHDOG Prescaler/Counter contents is retained if the device exits the HALT mode through G7 pin or Multi-Input Wake-up. G7 is the HALT-restart pin, but it can still be used as an input. If the device is not halted, G7 can be used as a general purpose input. If the Brown Out Enable mask option is selected, the Brown Out circuit remains active during the HALT mode causing additional current to be drawn. Note: To allow clock resynchronization, it is necessary to program two NOP’s immediately after the device comes out of the HALT mode. The user must program two NOP’s following the “enter HALT mode” (set G7 data bit) instruction. MICROWIRE/PLUS MICROWIRE/PLUS is a serial synchronous bidirectional communications interface. The MICROWIRE/PLUS capability enables the device to interface with any of National Semiconductor’s MICROWIRE peripherals (i.e., A/D converters, display drivers, EEPROMS, etc.) and with other microcontrollers which support the MICROWIRE/PLUS interface. It consists of an 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) and serial shift clock (SK). Figure 5 shows the block diagram of the MICROWIRE/PLUS interface. The shift clock can be selected from either an internal source or an external source. Operating the MICROWIRE/PLUS interface with the internal clock source is called the Master mode of operation. Operating the MICROWIRE/PLUS interface with an external shift clock is called the Slave mode of operation. 14 where, (Continued) tC is the instruction cycle time. MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS arrangement to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow < 8 bits to shift. The device may enter the MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 6 shows how two devices and several peripherals may be interconnected using the MICROWIRE/PLUS arrangement. MASTER MICROWIRE/PLUS OPERATION In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated internally by the device. The MICROWIRE/PLUS Master always initiates all data exchanges. (See Figure 6). The MSEL bit in the CNTRL register must be set to enable the SO and SK functions on the G Port. The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register. Table 4 summarizes the bit settings required for Master mode of operation. DS012851-16 FIGURE 5. MICROWIRE/PLUS Block Diagram The CNTRL register is used to configure and control the MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS, the MSEL bit in the CNTRL register is set to one. The SK clock rate is selected by the two bits, S0 and S1, in the CNTRL register. Table 3 details the different clock rates that may be selected. SLAVE MICROWIRE/PLUS OPERATION In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions on the G Port. The SK pin must be selected as an input and the SO pin selected as an output pin by appropriately setting up the Port G configuration register. Table 4 summarizes the settings required to enter the Slave mode of operation. The user must set the BUSY flag immediately upon entering the Slave mode. This will ensure that all data bits sent by the Master will be shifted properly. After eight clock pulses the BUSY flag will be cleared and the sequence may be repeated. (See Figure 6) TABLE 3. S1 S0 SK Cycle Time 0 0 2tC 0 1 4tC 1 x 8tC DS012851-17 FIGURE 6. MICROWIRE/PLUS Application 15 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ MICROWIRE/PLUS COP840CJ/COP842CJ/COP940CJ/COP942CJ MICROWIRE/PLUS MODE 3. TIMER WITH CAPTURE REGISTER (Continued) Timer T1 can be used to precisely measure external frequencies or events in this mode of operation. The timer T1 counts down at the instruction cycle rate. Upon the occurrence of a specified edge on the TIO pin the contents of the timer T1 are copied into the register R1. Bits in the control register CNTRL allow the trigger edge to be specified either as a positive edge or as a negative edge. In this mode the user can elect to be interrupted on the specified trigger edge. (See Figure 8). TABLE 4. G4 G5 Config. Config. Bit Bit 1 1 G4 Fun. SO G5 G6 Fun. Fun. Intl.SK SI Operation MICROWIRE Master 0 1 TRI-STATE Int. SK SI MICROWIRE Master 1 0 SO Ext. SI SK 0 0 TRI-STATE Ext. SK MICROWIRE Slave SI MICROWIRE Slave TIMER/COUNTER The device has a powerful 16-bit timer with an associated 16-bit register enabling it to perform extensive timer functions. The timer T1 and its register R1 are each organized as two 8-bit read/write registers. Control bits in the register CNTRL allow the timer to be started and stopped under software control. The timer-register pair can be operated in one of three possible modes. Table 5 details various timer operating modes and their requisite control settings. DS012851-19 FIGURE 8. Timer Capture Mode Block Diagram TIMER PWM APPLICATION Figure 9 shows how a minimal component D/A converter can be built out of the Timer-Register pair in the Auto-Reload mode. The timer is place in the “Timer with auto reload” mode and the TIO pin is selected as timer output. At the outset the TIO pin is set high, the timer T1 holds the on time and the register R1 holds the signal off time. Setting TRUN bit starts the timer which counts down at the instruction cycle rate. The underflow toggles the TIO output and copies the off time into the timer, which continues to run. By alternately loading in the on time and the off time at each successive interrupt a PWM frequency can be easily generated. MODE 1. TIMER WITH AUTO-LOAD REGISTER In this mode of operation, the timer T1 counts down at the instruction cycle rate. Upon underflow the value in the register R1 gets automatically reloaded into the timer which continues to count down. The timer underflow can be programmed to interrupt the microcontroller. A bit in the control register CNTRL enables the TIO (G3) pin to toggle upon timer underflows. This allows the generation of square-wave outputs or pulse width modulated outputs under software control. (See Figure 7.) DS012851-20 FIGURE 9. Timer Application DS012851-18 FIGURE 7. Timer/Counter Auto Reload Mode Block Diagram MODE 2. EXTERNAL COUNTER In this mode, the timer T1 becomes a 16-bit external event counter. The counter counts down upon an edge on the TIO pin. Control bits in the register CNTRL program the counter to decrement either on a positive edge or on a negative edge. Upon underflow the contents of the register R1 are automatically copied into the counter. The underflow can also be programmed to generate an interrupt. (See Figure 7). www.national.com 16 (Continued) TABLE 5. Timer Operating Modes CNTRL Bits Operating Mode 765 Timer T Interrupt Counter On 000 External Counter W/Auto-Load Reg. Timer Underflow 001 External Counter W/Auto-Load Reg. Timer Underflow TIO Pos. Edge TIO Pos. Edge 010 Not Allowed Not Allowed Not Allowed 011 Not Allowed Not Allowed Not Allowed 100 Timer W/Auto-Load Reg. Timer Underflow tC 101 Timer W/Auto-Load Reg./Toggle TIO Out Timer Underflow tC 110 Timer W/Capture Register TIO Pos. Edge tC 111 Timer W/Capture Register TIO Neg. Edge tC the underflow does not reset the device. Loading the 8-bit counter (load n-1 for n counts) sets the WDTEN bit (WATCHDOG Timer Enable) to “1”, loads the prescaler with FF, and starts the timer. The counter underflow stops the timer. The WDTEN bit serves as a start bit for the WATCHDOG timer. This bit is set when the 8-bit counter is loaded by the user program. The load could be as a result of WATCHDOG service (WATCHDOG timer dedicated for WATCHDOG function) or write to the counter (WATCHDOG timer used as a general purpose counter). The bit is cleared upon Brown Out reset, WATCHDOG reset or external reset. The bit is not memory mapped and is transparent to the user program. WATCHDOG The device has an on board 8-bit WATCHDOG timer. The timer contains an 8-bit READ/WRITE down counter clocked by an 8-bit prescaler. Under software control the timer can be dedicated for the WATCHDOG or used as a general purpose counter. Figure 10 shows the WATCHDOG timer block diagram. MODE 1: WATCHDOG TIMER The WATCHDOG is designed to detect user programs getting stuck in infinite loops resulting in loss of program control or “runaway” programs. The WATCHDOG can be enabled or disabled (only once) after the device is reset as a result of Brown Out reset or external reset. On power-up the WATCHDOG is disabled. The WATCHDOG is enabled by writing a 1 to WDREN bit (resides in WDREG register). Once enabled, the user program should write periodically into the 8-bit counter before the counter underflows. The 8-bit counter (WDCNT) is memory mapped at address 0CE Hex. The counter is loaded with n-1 to get n counts. The counter underflow resets the device, but does not disable the WATCHDOG. Loading the 8-bit counter initializes the prescaler with FF Hex and starts the prescaler/counter. Prescaler and counter are stopped upon counter underflow. Prescaler and counter are each loaded with FF Hex when the device goes into the HALT mode. The prescaler is used for crystal/ resonator start-up when the device exits the HALT mode through Multi-Input Wake-up. In this case, the prescaler/ counter contents are changed. Control/Status Bits WDUDF: WATCHDOG Timer Underflow Bit This bit resides in the CNTRL2 Register. The bit is set when the WATCHDOG timer underflows. The underflow resets the device if the WATCHDOG reset enable bit is set (WDREN = 1). Otherwise, WDUDF can be used as the timer underflow flag. The bit is cleared upon Brown-Out reset, external reset, load to the 8-bit counter, or going into the HALT mode. It is a read only bit. WDREN: WD Reset Enable WDREN bit resides in a separate register (bit 0 of WDREG). This bit enables the WATCHDOG timer to generate a reset. The bit is cleared upon Brown Out reset, or external reset. The bit under software control can be written to only once (once written to, the hardware does not allow the bit to be changed during program execution). WDREN = 1 WATCHDOG reset is enabled WDREN = 0 WATCHDOG reset is disabled. MODE 2: TIMER In this mode, the prescaler/counter is used as a timer by keeping the WDREN (WATCHDOG reset enable) bit at 0. The counter underflow sets the WDUDF (underflow) bit and Table 6 shows the impact of Brown Out Reset, WATCHDOG Reset, and External Reset on the Control/Status bits. TABLE 6. WATCHDOG Control/Status HALT Parameter 8-bit Prescaler MODE FF WD EXT/BOR (Note 16) Reset Reset FF FF FF Load Counter FF 8-bit WD counter FF FF WDREN bit Unchanged Unchanged 0 No effect User Value WDUDF bit 0 Unchanged 0 0 WDTEN Signal Unchanged 0 0 1 Note 16: BOR is Brown Out Reset 17 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ MICROWIRE/PLUS COP840CJ/COP842CJ/COP940CJ/COP942CJ WATCHDOG (Continued) DS012851-21 FIGURE 10. WATCHDOG Timer Block Diagram user program does not have to load the counter each time the counter is started. The counter can simply be started by setting the MC1 bit. Setting MC1 by software will load the counter with the value of the autoreload register. The software can reset MC1 to stop the counter. Modulator/Timer The MODULATOR/TIMER contains an 8-bit counter and an 8-bit autoreload register (MODRL address 0CF Hex). The Modulator/Timer has two modes of operation, selected by the control bit MC3. The Modulator/Timer Control bits MC1, MC2 and MC3 reside in CNTRL2 Register. MODE 2: PWM TIMER The counter can also be used as a PWM Timer. In this mode, an 8-bit register is used to serve as an autoreload register (MODRL). 1. 50% Duty Cycle: When MC1 is 1 and MC2, MC3 are 0, a 50% duty cycle free running signal is generated on the L7 output pin (Figure 12). The L7 pin must be configured as an output pin. In this mode the 8-bit counter is clocked by tC. Setting the MC1 control bit by software loads the counter with the value of the autoreload register and starts the counter. The counter underflow toggles the (L7) output pin. The 50% duty cycle signal will be continuously generated until MC1 is reset by the user program. MODE 1: MODULATOR The Modulator is used to generate high frequency pulses on the modulator output pin (L7). The L7 pin should be configured as an output. The number of pulses is determined by the 8-bit down counter. Under software control the modulator input clock can be either CKI or tC. The tC clock is derived by dividing down the oscillator clock by a factor of 10. Three control bits (MC1, MC2, and MC3) are used for the Modulator/Timer output control. When MC2 = 1 and MC3 = 1, CKI is used as the modulator input clock. When MC2 = 0, and MC3 = 1, tCis used as the modulator input clock. The user loads the counter with the desired number of counts (256 max) and sets MC1 to start the counter. The modulator autoreload register is loaded with n-1 to get n pulses. CKI or tC pulses are routed to the modulator output (L7) until the counter underflows (Figure 11). Upon underflow the hardware resets MC1 and stops the counter. The L7 pin goes low and stays low until the counter is restarted by the user program. The user program has the responsibility to time-out the low time. Unless the number of counts is changed, the www.national.com 18 2. TABLE 7. Modulator/Timer Modes (Continued) Control bits in Variable Duty Cycle: When MC3 = 0 and MC2 = 1, a variable duty cycle PWM signal is generated on the L7 output pin. The counter is clocked by tC. In this mode the 16-bit timer T1 along with the 8-bit down counter are used to generate a variable duty cycle PWM signal. The timer T1 underflow sets MC1 which starts the down counter and it also sets L7 high (L7 should be configured as an output). When the counter underflows the MC1 control bit is reset and the L7 output will go low until the next timer T1 underflow. Therefore, the width of the output pulse is controlled by the 8-bit counter and the pulse duration is controlled by the 16-bit timer T1 (Figure 13). Timer T1 must be configured in “PWM Mode/Toggle TIO Out” (CNTRL1 Bits 7,6,5 = 101). CNTRL2(00CC) Table 7 shows the different operation modes for the Modulator/Timer. OPERATION MODE L7 Function MC3 MC2 MC1 0 0 0 Normal I/O 0 0 1 50% duty cycle mode (clocked by tC) 0 1 X Variable duty cycle mode (clocked by tC) using Timer 1 underflow 1 0 X Modulator mode (clocked by tC) 1 1 X Modulator mode (clocked by CKI) Note 17: MC1, MC2 and MC3 control bits are cleared upon reset. INTERNAL DATA BUS DS012851-22 FIGURE 11. Mode 1: Modulator Block Diagram/Output Waveform 19 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Modulator/Timer COP840CJ/COP842CJ/COP940CJ/COP942CJ Modulator/Timer (Continued) DS012851-23 DS012851-24 FIGURE 12. Mode 2a: 50% Duty Cycle Output DS012851-25 DS012851-26 FIGURE 13. Mode 2b: Variable Duty Cycle Output Enables comparator output to pin L0 (“1” = enable), CMPEN bit must be set to enable this function. If CMPEN = 0, L0 will be 0. The Comparator Select/Control bits are cleared on RESET (the comparator is disabled). To save power the program should also disable the comparator before the device enters the HALT mode. The user program must set up L0, L1, and L2 ports correctly for comparator Inputs/Output. L1 and L2 need to be configured as inputs and L0 as output. Table 8 shows the DC and AC characteristics for the comparator. CMPOE Comparator The device has one differential comparator. Ports L0–L2 are used for the comparator. The output of the comparator is brought out to a pin. Port L has the following assignments: L0 Comparator output L1 Comparator negative input L2 Comparator positive input THE COMPARATOR STATUS/CONTROL BITS These bits reside in the CNTRL2 Register (Address 0CC) CMPEN Enables comparator (“1” = enable) CMPRD Reads comparator output internally (CMPEN = 1, CMPOE = X) www.national.com 20 (Continued) TABLE 8. DC and AC Characteristics (Note 18) 4V ≤ VCC ≤ 6V, −40˚C ≤ TA ≤ +85˚C Parameters Input Offset Voltage Conditions Min 0.4V < VIN < VCC −1.5V Input Common Mode Voltage Range Response Time Max Units ± 10 ± 25 mV 0.4 Voltage Gain DC Supply Current (when enabled) Typ VCC −1.5 300k VCC = 6.0V V V/V 250 100 mV Overdrive 60 100 140 500 mV Overdrive 80 125 165 1000 mV Overdrive 135 215 300 µA ns Note 18: For comparator output current characteristics see L-Port specs. select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled. An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L port bit 5, where bit 5 has previously been enabled for an input. The program would be as follows: RBIT 5,WKEN SBIT 5,WKEDG RBIT 5,WKPND SBIT 5,WKEN If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wake-Up, a safety procedure should also be followed to avoid inherited pseudo wake-up conditions. After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the associated WKPND bits being cleared. This same procedure should be used following RESET, since the L port inputs are left floating as a result of RESET. The occurrence of the selected trigger condition for Multi-Input Wake-Up is latched into a pending register called Reg:WKPND. The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin. The user has the responsibility of clearing these pending flags. Since the Reg:WKPND is a pending register for the occurrence of selected wake-up conditions, the device will not enter the HALT mode if any wake-up bit is both enabled and pending. Setting the G7 data bit under this condition will not allow the device to enter the HALT mode. Consequently, the user has the responsibility of clearing the pending flags before attempting to enter the HALT mode. If a crystal oscillator is being used, the wake-up signal will not start the chip running immediately since crystal oscillators have a finite start up time. The WATCHDOG timer prescaler generates a fixed delay to ensure that the oscillator has indeed stabilized before allowing the device to execute instructions. In this case, upon detecting a valid wake-up signal only the oscillator circuitry and the WATCHDOG timer are enabled. The WATCHDOG timer prescaler is loaded with a value of FF Hex (256 counts) and is clocked from the tC instruction cycle clock. The tCclock is derived dividing down the oscillator clock by a factor of 10. A Schmitt trigger following the CKI on-chip inverter ensures that the WATCHDOG timer is clocked only when the oscillator has a sufficiently Multi-Input Wake-Up The Multi-Input Wake-Up feature is used to return (wake-up) the device from the HALT mode. Figure 14 shows the Multi-Input Wake-Up logic. DS012851-27 FIGURE 14. Multi-Input Wake-Up Logic This feature utilizes the L Port. The user selects which particular L port bit or combination of L Port bits will cause the device to exit the HALT mode. Three 8-bit memory mapped registers, Reg:WKEN, Reg:WKEDG, and Reg:WKPNDare used in conjunction with the L port to implement the Multi-Input Wake-Up feature. All three registers Reg:WKEN, Reg:WKPND, and Reg:WKEDG are read/write registers, and are cleared at reset, except WKPND. WKPND is unknown on reset. The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). This selection is made via the Reg:WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin. Resetting the bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in order to avoid a pseudo wake-up condition as a result of the edge change. First, the associated WKEN bit should be reset, followed by the edge 21 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Comparator COP840CJ/COP842CJ/COP940CJ/COP942CJ Multi-Input Wake-Up (Continued) large amplitude to meet the Schmitt trigger specs. This Schmitt trigger is not part of the oscillator closed loop. The start-up time-out from the WATCHDOG timer enables the clock signals to be routed to the rest of the chip. Interrupts The device has a sophisticated interrupt structure to allow easy interface to the real world. There are three possible interrupt sources, as shown below. A maskable interrupt on external GO input (positive or negative edge sensitive under software control) A maskable interrupt on timer carry or timer capture A non-maskable software/error interrupt on opcode zero DS012851-28 FIGURE 15. Interrupt Block Diagram DETECTION OF ILLEGAL CONDITIONS The device incorporates a hardware mechanism that allows it to detect illegal conditions which may occur from coding errors, noise and “brown out” voltage drop situations. Specifically, it detects cases of executing out of undefined ROM area and unbalanced stack situations. Reading an undefined ROM location returns 00 (hexadecimal) as its contents. The opcode for a software interrupt is also “00”. Thus a program accessing undefined ROM will cause a software interrupt. Reading undefined RAM location returns an FF (hexadecimal). The subroutine stack on the device grows down for each subroutine call. By initializing the stack pointer to the top of RAM, the first unbalanced return instruction will cause the stack pointer to address undefined RAM. As a result the program will attempt to execute from FFFF (hexadecimal), which is an undefined ROM location and will trigger a software interrupt. INTERRUPT CONTROL The GIE (global interrupt enable) bit enables the interrupt function. This is used in conjunction with ENI and ENTI to select one or both of the interrupt sources. This bit is reset when interrupt is acknowledged. ENI and ENTI bits select external and timer interrupts respectively. Thus be user can select either or both source to interrupt the microcontroller when GIE is enabled. IEDG selects the external interrupt edge (0 — rising edge, 1 = falling edge). The user can get an interrupt on both rising and falling edges by toggling the state of IEDG bit after each interrupt. IPND and TPND bits signal which interrupt is pending. After an interrupt is acknowledged, the user can check these two bits to determine which interrupt is pending. This permits the interrupts to be prioritized under software. The pending flags have to be cleared by the user. Setting the GIE bit high inside the interrupt subroutine allows nested interrupts. The software interrupt does not reset the GIE bit. This means that the controller can be interrupted by other interrupt sources while servicing the software interrupt. Control Registers CNTRL1 REGISTER (ADDRESS 00EE) The Timer and MICROWIRE control register contains the following bits: SL1 and SL0 Select the MICROWIRE clock divide-by (00 = 2, 01 = 4, 1x = 8) IEDG External interrupt edge polarity select MSEL Selects G5 and G4 as MICROWIRE signals SK and SO respectively TRUN Used to start and stop the timer/counter (1 = run, 0 = stop) TC1 Timer T1 Mode Control Bit TC2 Timer T1 Mode Control Bit TC3 Timer T1 Mode Control Bit INTERRUPT PROCESSING The interrupt, once acknowledged, pushes the program countermen counter (PC) onto the stack and the stack pointer (SP) is decremental twice. The Global Interrupt Enable (GIE) bit is reset to disable further interrupts. The microcontroller then vectors to the address 00FFH and resumes execution from that address. This process takes 7 cycles to complete. At end of the interrupt subroutine, any of the following three instructions return the processor back to the main program: RET, RETSK or RETI. Either one of the three instructions will pop the stack into the program counter (PC). The stack pointer is then incremented twice. The RETI instruction additionally sets the GIE bit to re-enable further interrupts. Any of the three instructions can be used to return from a hardware interrupt subroutine. The RETSK instruction should be used when returning from a software interrupt subroutine to avoid entering an infinite loop. TC1 Bit 7 TC3 TRUN MSEL IEDG SL1 SL0 Bit 0 PSW REGISTER (ADDRESS 00EF) The PSW register contains the following select bits: GIE Global interrupt enable (enables interrupts) ENI External interrupt enable BUSY MICROWIRE busy shifting flag PND External interrupt pending ENTI Timer T1 interrupt enable TPND Timer T1 interrupt pending (timer Underflow or capture edge) C Carry Flip/flop HC Half carry Flip/flop Note: There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit. If this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt processing is started at the same time as the interrupt bit is being reset. To avoid this scenario, the user should always use a two, three, or four cycle instruction to reset interrupt enable bits. www.national.com TC2 22 HC C TPND ENTI (Continued) IPND BUSY ADDRESS ENI Bit 7 C9 MIWU Enable Register (Reg:WKEN) GIE CA MIWU Pending Register (Reg:WKPND) Bit 0 CB Reserved CC Control2 Register (CNTRL2) CD WATCHDOG Register (WDREG) CE WATCHDOG Counter (WDCNT) CF Modulator Reload (MODRL) D0 Port L Data Register D1 Port L Configuration Register D2 Port L input Pins (read only) D3 Reserved for Port L D4 Port G Data Register D5 Port G Configuration Register D6 Port G Input pins (read only) D7 Port I Input pins (read only) The Half-Carry bit is also effected by all the instructions that effect the Carry flag. The flag values depend upon the instruction. For example, after executing the ADC instruction the values of the Carry and the Half-Carry flag depend upon the operands involved. However, instructions like SET C and RESET C will set and clear both the carry flags. Table 9 lists the instructions that effect the HC and the C flags. TABLE 9. Instructions Effecting HC and C Flags Instr. HC Flag C Flag ADC Depends on operands Depends on operands SUBC Depends on operands Depends on operands SET C Set CONTENTS Set D8–DB Reserved for Port C DC Port D Data Register RESET C Set Set RRC Depends on operands Depends on operands DD–DF Reserved for Port D E0–EF On-Chip Functions and Registers E0–E7 Reserved for Future Parts E8 Reserved E9 MICROWIRE Shift Register MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF unused EA Timer Lower Byte R/W R/W R/W EB Timer Upper Byte EC Timer1 Autoreload Register Lower Byte ED Timer1 Autoreload Register Upper Byte EE CNTRL1 Control Register EF PSW Register CNTRL2 REGISTER (ADDRESS 00CC) R/W R/O R/W R/O Bit 7 MC3 MC2 MC1 CMPEN CMPRD CMPOE WDUDF Bit 0 Modulator/Timer Control Bit Modulator/Timer Control Bit Modulator/Timer Control Bit Comparator Enable Bit Comparator Read Bit Comparator Output Enable Bit WATCHDOG Timer Underflow Bit (Read Only) WDREN REGISTER (ADDRESS 00CD) WDRENWATCHDOG Reset Enable Bit (Write Once Only) UNUSED FE B Register REGISTER INDIRECT This is the “normal” addressing mode for the chip. The operand is the data memory addressed by the B or X pointer. TABLE 10. Memory Map CONTENTS REGISTER INDIRECT WITH AUTO POST INCREMENT OR DECREMENT This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B or X pointer. This is a register indirect mode that automatically post increments or post decrements the B or X pointer after executing the instruction. On-Chip RAM bytes (112 bytes) Unused RAM address (Reads as all ones) 80–BF SP Register OPERAND ADDRESSING MODES All RAM, ports and registers (except A and PC) are mapped into data memory address space. 70–7F FD There are ten addressing modes, six for operand addressing and four for transfer of control. Memory Map 00–6F X Register Addressing Modes Bit 0 ADDRESS On-Chip RAM mapped as Registers FC Reading other unused memory locations will return undefined data. WDREN Bit 7 F0–FF Unused RAM address (Reads Undefined Data) C0–C7 Reserved C8 MIWU Edge Select Register (Reg:WKEDG) 23 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Control Registers COP840CJ/COP842CJ/COP940CJ/COP942CJ Addressing Modes (Continued) DIRECT The instruction contains an 8-bit address field that directly points to the data memory for the operand. IMMEDIATE The instruction contains an 8-bit immediate field as the operand. SHORT IMMEDIATE This addressing mode issued with the LD B,# instruction, where the immediate # is < 16. The instruction contains a 4-bit immediate field as the operand. INDIRECT This addressing mode is used with the LAID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory. TRANSFER OF CONTROL ADDRESSING MODES RELATIVE This mode is used for the JP instruction with the instruction field being added to the program counter to produce the next instruction address. JP has a range from −31 to +32 to allow a one byte relative jump (JP + 1 is implemented by a NOP instruction). There are no “blocks” or “pages” when using JP since all 15 bits of the PC are used. ABSOLUTE This mode is used with the JMP and JSR instructions with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any location in the current 4k program memory segment. ABSOLUTE LONG This mode is used with the JMPL and JSRL instructions with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC). This allows jumping to any location in the entire 32k program memory space. INDIRECT This mode is used with the JID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory. The contents of this program memory location serves as a partial address (lower 8 bits of PC) for the jump to the next instruction. www.national.com 24 REGISTER AND SYMBOL DEFINITIONS Symbols Registers A 8-bit Accumulator register B 8-bit Address register X SP PC PU PL C HC GIE 8-bit Address register 8-bit Stack pointer register 15-bit Program counter register Upper 7 bits of PC Lower 8 bits of PC 1-bit of PSW register for carry 1-bit of PSW register for half carry 1-bit of PSW register for global interrupt enable Instr Function ADD A, MemI Add ADC A, MemI Add with carry SUBC A, MemI Subtract with carry AND A, MemI Logical AND [B] Memory indirectly addressed by B register [X] MD Memory indirectly addressed by X register Direct addressed memory Mem MemI Imm Reg Bit ← Direct addressed memory, or [B] Direct addressed memory, [B], or Immediate data 8-bit Immediate data Register memory: addresses F0 to FF (Includes B, X, and SP) Bit number (0 to 7) Loaded with ↔ Exchanged with Register Operation ← A A + MemI A ← A + MemI + C, C ← Carry A ← A + MemI +C, C ← Carry A ← A and MemI OR A, MemI Logical OR XOR A, MemI Logical Exclusive-OR A ← A or MemI A ← A xor MemI IFEQ A, MemI IF equal Compare A and MemI, Do next if A = MemI IFGT A, MemI IF greater than Compare A and MemI, Do next if A > MemI Do next if lower 4 bits of B not = Imm IFBNE # IF B not equal DRSZ Reg Decrement Reg., skip if zero SBIT #, Mem Set bit RBIT #, Mem Reset bit Reg ← Reg − 1, skip if Reg goes to 0 1 to Mem.bit (bit = 0 to 7 immediate) 0 to Mem.bit (bit = 0 to 7 immediate) IFBIT #, Mem If bit If Mem.bit is true, do next instruction X A, Mem Exchange A with memory A ↔ Mem A ← MemI LD A, MemI Load A with memory LD Mem, Imm Load Direct memory Immed. LD Reg, Imm Load Register memory Immed. X A, [B ± ] Exchange A with memory [B] X A, [X ± ] Exchange A with memory [X] LD A, [B ± ] Load A with memory [B] LD A, [X ± ] Load A with memory [X] LD [B ± ], Imm Load memory immediate CLRA Clear A INC Increment A DEC A Decrement A LAID A Load A indirect from ROM DCOR Mem ← Imm Reg ← Imm A ↔ [B] (B ← B ± 1) A ↔ [X] (X ← X ± 1) A ← [B] (B ← B ± 1) A ← [X] (X ← X ± 1) [B] ← Imm (B ← B ± 1) A←0 A←A+1 A←A−1 A ← ROM(PU,A) A ← BCD correction (follows ADC, SUBC) C → A7 → … → A0 → C Decimal Correct A RRC A Rotate right through carry SWAP A Swap nibbles of A SC A Set C A7 … A4 ↔ A3 … A0 C←1 RC Reset C C←0 IFC If C If C is true, do next instruction IFNC If Not C JMPL Jump absolute long If C is not true, do next instruction PC ← ii (ii = 15 bits, 0 to 32k) JMP Jump absolute PC11...PC0 ← i (i = 12 bits) Jump relative short PC15...PC12 remain unchanged PC ← PC + r (r is −31 to +32, not 1) JP Addr. 25 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Instruction Set COP840CJ/COP842CJ/COP940CJ/COP942CJ Instruction Set Instr JSRL (Continued) Function Addr. Jump subroutine long JID Disp. Jump indirect RET Addr. Return from subroutine RETSK Addr. JSR Register Operation [SP] ← PL, [SP−1] ← PU, SP−2, PC ← ii [SP] ← PL,[SP−1] ← PU, SP−2, PC11.. PC0 ← ii PL ← ROM(PU, A) Jump subroutine INTR Generate an interrupt SP+2, PL ← [SP], PU ← [SP−1] SP+2, PL ← [SP], PU ← [SP−1], Skip next instruction SP+2, PL ← [SP], PU ← [SP−1], GIE ← 1 [SP] ← PL, [SP−1] ← PU, SP−2, PC ← 0FF NOP No operation PC ← PC + 1 RETI www.national.com Return and skip Return from interrupt 26 DRSZ 0F4 DRSZ 0F5 DRSZ 0F6 DRSZ 0F7 DRSZ 0F8 DRSZ 0F9 DRSZ 0FA DRSZ 0FB DRSZ 0FE DRSZ 0FF JP−11 JP−27 LD 0F4, #i JP−10 JP−26 LD 0F5, #i JP−25 LD 0F6, #i JP−24 LD 0F7, #i JP−23 LD 0F8, #i JP−22 LD 0F9, #i JP−21 LD 0FA, #i JP−20 LD 0FB, #i JP−19 JP−18 JP−17 LD 0FE, #i JP−16 LD 0FF, #i JP−9 JP−8 JP−7 JP−6 JP−5 JP−4 JP−3 JP−2 JP−1 LD 0FD, #i DRSZ 0FD JID LAID X A,[B−] X A,[B+] SC RC A * LD A,[X] DIR LD Md,#i LD A,[X−] LD A,[X+] * NOP * * LD A,[B] JSRL JMPL LD A,[B−] LD A,[B+] * * * X A,[X] X A,[B] * * X A,[X−] X A,[X+] * RRCA B Where, i is the immediate data Md is a directly addressed memory location * is an unused opcode Note: The opcode 60 Hex is also the opcode for IFBIT #i,A JP−0 DRSZ 0F3 JP−12 JP−28 LD 0F3, #i DRSZ 0FC DRSZ 0F2 JP−13 JP−29 LD 0F2, #i LD 0FC, #i DRSZ 0F1 C JP−14 JP−30 LD 0F1, #i D DRSZ 0F0 E JP−15 JP−31 LD 0F0, #i F Opcode Table * LD [B],#i LD A,Md X A,Md LD [B−],#i LD [B+],#i * LD A,#i OR A,#i XOR A,#i AND A,#i ADD A,#i IFGT A,#i IFEQ A,#i SUBC A,#i ADC A,#i 9 RETI RET SBIT 7,[B] SBIT 6,[B] SBIT 5,[B] SBIT 4,[B] * SBIT 2,[B] SBIT 1,[B] SBIT 0,[B] IFBIT 7,[B] RBIT 7,[B] RBIT 6,[B] RBIT 5,[B] RBIT 4,[B] RBIT 3,[B] RBIT 2,[B] RBIT 1,[B] RBIT 0,[B] * IFBIT DCORA 6,[B] SBIT 3,[B] RETSK CLRA * * * * 6 IFBIT SWAPA 5,[B] IFBIT 4,[B] IFBIT 3,[B] IFBIT A,[B] IFBIT 1,[B] IFBIT 0,[B] DECA INCA IFNC IFC OR A,[B] XOR A,[B] AND A,[B] ADD A,[B] IFGT A,[B] IFEQ A,[B] SUBC A,[B] ADC A,[B] 7 Upper Nibble Bits 7–4 8 LD B, 0 LD B, 1 LD B, 2 LD B, 3 LD B, 4 LD B, 5 LD B, 6 LD B, 7 LD B, 8 LD B, 9 LD B, 0A LD B, 0B LD B, 0C LD B, 0D LD B, 0E LD B, 0F 5 IFBNE 0F IFBNE 0E IFBNE 0D IFBNE 0C IFBNE 0B IFBNE 0A IFBNE 9 IFBNE 8 IFBNE 7 IFBNE 6 IFBNE 5 IFBNE 4 IFBNE 3 IFBNE 2 IFBNE 1 IFBNE 0 4 2 1 JP+2 INTR 0 JP+9 JP+8 JP+7 JP+6 JP+5 JP+4 JSR JMP JP+32 JP+16 0F00–0FFF 0F00–0FFF JSR JMP JP+31 JP+15 0E00–0EFF 0E00–0EFF JSR JMP JP+30 JP+14 0D00–0DFF 0D00–0DFF JSR JMP JP+29 JP+13 0C00–0CFF 0C00–0CFF JSR JMP JP+28 JP+12 0B00–0BFF 0B00–0BFF JSR JMP JP+27 JP+11 0A00–0AFF 0A00–0AFF JSR JMP JP+26 JP+10 0900–09FF 0900–09FF JSR JMP JP+25 0800–08FF 0800–08FF JSR JMP JP+24 0700–07FF 0700–07FF JSR JMP JP+23 0600–06FF 0600–06FF JSR JMP JP+22 0500–05FF 0500–05FF JSR JMP JP+21 0400–04FF 0400–04FF JSR JMP JP+20 0300–03FF 0300–03FF JSR JMP JP+19 UJP+3 0200–02FF 0200–02FF JSR JMP JP+18 0100–01FF 0100–01FF JSR JMP JP+17 0000–00FF 0000–00FF 3 F E D C B A 9 8 7 6 5 4 3 2 1 0 Lower Nibble Bits 3–0 COP840CJ/COP842CJ/COP940CJ/COP942CJ 27 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Instruction Execution Time • • Instructions Using A and C (Bytes/Cycles) Instr Most instructions are single byte (with immediate addressing mode instructions requiring two bytes). Most single byte instructions take one cycle time to execute. • Skipped instructions require x number of cycles to be skipped, where x equals the number of bytes in the skipped instruction opcode. The following tables shows the number of bytes and cycles for each instruction in the format byte/cycle. Arithmetic and Logic Instructions (Bytes/Cycles) Instr Immediate Bytes/Cycles CLRA 1/1 INCA 1/1 DECA 1/1 LAID 1/3 DCOR 1/1 RRCA 1/1 SWAPA 1/1 SC 1/1 RC 1/1 IFC 1/1 IFNC 1/1 [B] Direct ADD 1/1 3/4 ADC 1/1 3/4 2/2 SUBC 1/1 3/4 2/2 AND 1/1 3/4 2/2 OR 1/1 3/4 2/2 JMPL XOR 1/1 3/4 2/2 JMP 2/3 IFEQ 1/1 3/4 2/2 JP 1/3 IFNE 1/1 3/4 2/2 JSRL 3/5 IFGT 1/1 3/4 2/2 JSR 2/5 IFBNE 1/1 2/2 JID 1/3 DRSZ 1/1 1/3 RET 1/5 SBIT 1/1 3/4 RETSK 1/5 RBIT 1/1 3/4 RETI 1/5 IFBIT 1/1 3/4 INTR 1/7 NOP 1/1 Transfer of Control Instructions (Bytes/Cycles) Instr Bytes/Cycles 3/4 Memory Transfer Instructions (Bytes/Cycles) Register Indirect Instr [B] X A, (Note 19) 1/1 LD A, (Note 19) 1/1 Register Indirect Direct Immed. [X] Auto Incr and Decr [B+, B−] 2/3 [X+, X−] 1/2 2/3 1/2 LD B,Imm 1/3 2/2 1/3 LD B,Imm 1/3 1/1 (Note 20) 1/3 LD Mem,Imm LD Reg,Imm 3/3 2/2 2/3 Note 19: Memory location addressed by B or X or directly Note 20: IF B Note 21: IF B < 16 > 15 www.national.com 28 2/3 (Note 21) 2/2 Development Support The mask programmable options are listed below. The options are programmed at the same time as the ROM pattern to provide the user with hardware flexibility to use a variety of oscillator configurations and the Brown Out feature. SUMMARY The following option information is to be sent to National along with the EPROM. Contact the sales office for more details. OPTION 1: CKI INPUT = 1 Crystal (CKI/10) G7/CKO for crystal configuration = 2 External (CKI/10) G7 available as input = 3 R/C (CKI/10) G7 available as input OPTION 2: ″Brown Out″ = 1 Enable Brown Out Detection = 2 Disable Brown Out Detection OPTION 3: BONDING = 1 28-Pin DIP/SO Package = 2 20-Pin DIP/SO Package • iceMASTER™: IM-COP8/400 — Full feature in-circuit emulation for all COP8 products. A full set of COP8 Basic and Feature Family device and package specific probes are available. • COP8 Debug Module: Moderate cost in-circuit emulation and development programming unit. • COP8 Evaluation and Programming Unit: EPU-COP880C — low cost In-circuit simulation and development programming unit. • Assembler: COP8-DEV-IBMA. A DOS installable cross development Assembler, Linker, Librarian and Utility Software Development Tool Kit. • C Compiler: COP8C. A DOS installable cross development Software Tool Kit. • OTP/EPROM Programmer Support: Covering needs from engineering prototype, pilot production to full production environments. How to Order To order a complete development package, select the section for the microcontroller to be developed and order the parts listed. Contact the sales office for more details. 29 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Mask Option COP840CJ/COP842CJ/COP940CJ/COP942CJ Development Support • Watch windows, content updated automatically at each execution break. IceMASTER (IM) IN-CIRCUIT EMULATION • The iceMASTER IM-COP8/400 is a full feature, PC based, in-circuit emulation tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products. Instruction by instruction memory/register changes displayed on source window when in single step operation. • See Figure 16 for configuration. The iceMASTER IM-COP8/400 with its device specific COP8 Probe provides a rich feature set for developing, testing and maintaining product: Single base unit and debugger software reconfigurable to support the entire COP8 family; only the probe personality needs to change. Debugger software is processor customized, and reconfigured from a master model file. • Processor specific symbolic display of registers and bit level assignments, configured from master model file. • • Halt/Idle mode notification. • Includes a copy of COP8-DEV-IBMA assembler and linker SDK. (Continued) • Real-time in-circuit emulation; full 2.4VDC–5.5VDC operation range, full DC-10 MHz clock. Chip options are programmable or jumper selectable. • Direct connection to application board by package compatible socket or surface mount assembly. • Full 32 kbyte of loadable programming space that overlays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated on the probe as necessary. • On-line HELP customized to specific processor using master model file. IM Order Information Base Unit IM-COP8/400-1 Full 4k frame synchronous trace memory. Address, instruction, and 8 unspecified, circuit connectable trace lines. Display can be HLL source (e.g., C source), assembly or mixed. IM-COP8/400-2 • A full 64k hardware configurable break, trace on, trace off control, and pass count increment events. iceMASTER Probe • Tool set integrated interactive symbolic debugger — supports both assembler (COFF) and C Compiler (.COD) linked object formats. • iceMASTER Base Unit, 110V Power Supply iceMASTER Base Unit, 220V Power Supply Real time performance profiling analysis; selectable bucket definition. MHW-840CJ28DWPC 28 DIP MHW-840CJ20DWPC 20 DIP MHW-SOIC28 28 SOIC Adapter Kit MHW-SOIC20 20 SOIC Adapter Kit DS012851-29 FIGURE 16. COP8 iceMASTER Environment www.national.com 30 (Continued) IceMASTER DEBUG MODULE (DM) The iceMASTER Debug Module is a PC based, combination in-circuit emulation tool and COP8 based OTP/EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products. See Figure 17 for configuration. The iceMASTER Debug Module is a moderate cost development tool. It has the capability of in-circuit emulation for a specific COP8 microcontroller and in addition serves as a programming tool for COP8 OTP and EPROM product families. Summary of features is as follows: • Real-time in-circuit emulation; full operating voltage range operation, full DC-10 MHz clock. • All processor I/O pins can be cabled to an application development board with package compatible cable to socket and surface mount assembly. • • • Full 32 kbytes of loadable programming space that overlays (replaces) the on-chip ROM or EPROM. On-chip RAM and I/O blocks are used directly or recreated as necessary. • Instruction by instruction memory/register changes displayed when in single step operation. • Processor specific symbolic display of registers and bit level assignments, configured from master model file. • • Halt/Idle mode notification. • Programming of 44 PLCC and 68 PLCC parts requires external programming adapters. • • Includes wall mount power supply. • On-line HELP customized to specific processor using master model file. • Includes a copy of COP8-DEV-IBMA assembler and linker SDK. Programming menu supports full product line of programmable OTP and EPROM COP8 products. Program data is taken directly from the overlay RAM. On-board VPP generator from 5V input or connection to external supply supported. Requires VPPlevel adjustment per the family programming specification (correct level is provided on an on-screen pop-down display). Debug Module Unit COP8-DM/840CJ Cable Adapters Configured break points; uses INTR instruction which is modestly intrusive. Software — only supported features are selectable. Debugger software is processor customized, and reconfigured from a master model file. DM Order Information 100 frames of synchronous trace memory. The display can be HLL source (C source), assembly or mixed. The most recent history prior to a break is available in the trace memory. • • • Tool set integrated interactive symbolic debugger — supports both assembler (COFF) and C Compiler (.COD) SDK linked object formats. DM-COP8/28D 28 DIP cable DM-COP8/28D-SO 28 DIP to 28 SOIC adapter DM-COP8/20D 20 DIP cable DM-COP8/20D-SO 20 DIP to 20 SOIC adapter DS012851-30 FIGURE 17. COP8-DM Environment 31 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Development Support COP840CJ/COP842CJ/COP940CJ/COP942CJ Development Support COP8 C COMPILER A C Compiler is developed and marketed by Byte Craft Limited. The COP8C compiler is a fully integrated development tool specifically designed to support the compact embedded configuration of the COP8 family of products. (Continued) COP8 ASSEMBLER/LINKER SOFTWARE DEVELOPMENT TOOL KIT National Semiconductor offers a relocateable COP8 macro cross assembler, linker, librarian and utility software development tool kit. Features are summarized as follows: Features are summarized as follows: • ANSI C with some restrictions and extensions that optimize development for the COP8 embedded application. • BITS data type extension. Register declaration #pragma with direct bit level definitions. • Basic and Feature Family instruction set by “device” type. • Nested macro capability. • Extensive set of assembler directives. • Supported on PC/DOS platform. • Generates National standard COFF output files. • Integrated Linker and Librarian. • Integrated utilities to generate ROM code file outputs. • DUMPCOFF utility. This product is integrated as a part of MetaLink tools as a development kit, fully supported by the MetaLink debugger. It may be ordered separately or it is bundled with the MetaLink products at no additional cost. • • C language support for interrupt routines. • Performs consistency checks against the architectural definitions of the target COP8 device. • • Generates program memory code. • • Global optimization of linked code. Order Information Assembler SDK COP8-DEV-IBMA Expert system, rule based code generation and optimization. Supports linking of compiled object or COP8 assembled object formats. Symbolic debug load format fully source level supported by the MetaLink debugger. INDUSTRY WIDE OTP/EPROM PROGRAMMING SUPPORT Programming support, in addition to the MetaLink development tools, is provided by a full range of independent approved vendors to meet the needs from the engineering laboratory to full production. Assembler SDK on installable 3.5" PC/DOS Floppy Disk Drive format. Periodic upgrades and most recent version is available on National’s BBS and Internet Approved List Manufacturer North Europe Asia America BP (800) 225-2102 +49-8152-4183 +852-234-16611 Microsystems (713) 688-4600 +49-8856-932616 +852-2710-8121 Fax: (713) 688-0920 Data I/O (800) 426-1045 +44-0734-440011 (206) 881-6444 Call North America Fax: (206) 882-1043 HI–LO (510) 623-8860 Call Asia +886-2-764-0215 Fax: +886-2-756-6403 ICE (800) 624-8949 +44-1226-767404 Technology (919) 430-7915 Fax: 0-1226-370-434 MetaLink (800) 638-2423 +49-80 9156 96-0 (602) 926-0797 Fax: +49-80 9123 86 +852-737-1800 Fax: (602) 693-0681 Systems (408) 263-6667 +41-1-9450300 General Needhams (916) 924-8037 Fax: (916) 924-8065 www.national.com +886-2-917-3005 Fax: +886-2-911-1283 32 CUSTOMER RESPONSE CENTER (Continued) Complete product information and technical support is available from National’s customer response centers. AVAILABLE LITERATURE For more information, please see the COP8 Basic Family User’s Manual, Literature Number 620895, COP8 Feature Family User’s Manual, Literature Number 620897 and National’s Family of 8-bit Microcontrollers COP8 Selection Guide, Literature Number 630009. CANADA/U.S.: Tel: EUROPE: DIAL-A-HELPER SERVICE Dial-A-Helper is a service provided by the Microcontroller Applications group. The Dial-A-Helper is an Electronic Information System that may be accessed as a Bulletin Board System (BBS) via data modem, as an FTP site on the Internet via standard FTP client application or as an FTP site on the Internet using a standard Internet browser such as Netscape or Mosaic. The Dial-A-Helper system provides access to an automated information storage and retrieval system. The system capabilities include a MESSAGE SECTION (electronic mail, when accessed as a BBS) for communications to and from the Microcontroller Applications Group and a FILE SECTION which consists of several file areas where valuable application software and utilities could be found. (800) 272-9959 email: support @ tevm2.nsc.com email: [email protected] Deutsch Tel: +49 (0) 180-530 85 85 English Tel: +49 (0) 180-532 78 32 Franc¸ais Tel: +49 (0) 180-532 93 58 Italiano Tel: +49 (0) 180-534 16 80 JAPAN: Tel: +81-043-299-2309 S.E. ASIA: Beijing Tel: (+86) 10-6856-8601 Shanghai Tel: (+86) 21-6415-4092 Hong Kong Tel: (+852) 2737-1600 Korea Tel: (+82) 2-3771-6909 Malaysia Tel: (+60-4) 644-9061 Singapore Tel: (+65) 255-2226 Taiwan Tel: +886-2-521-3288 DIAL-A-HELPER BBS via a Standard Modem AUSTRALIA: Tel: (+61) 3-9558-9999 Modem: INDIA: Tel: (+91) 80-559-9467 CANADA/U.S.: (800) NSC-MICRO EUROPE: (+49) 0-8141-351332 Baud: 14.4k Set-up: Length: (800) 672-6427 Parity: 8-Bit None Stop Bit: Operation: 1 24 Hrs., 7 Days DIAL-A-HELPER via FTP ftp nscmicro.nsc.com user: anonymous password: [email protected] DIAL-A-HELPER via a WorldWide Web Browser ftp://nscmicro.nsc.com National Semiconductor on the WorldWide Web See us on the WorldWide Web at: http://www.national.com 33 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ Development Support COP840CJ/COP842CJ/COP940CJ/COP942CJ Physical Dimensions inches (millimeters) unless otherwise noted Order Number COP842CJ-XXX/M or COP942CJ-XXX/M NS Package Number M20B Order Number COP840CJ-XXX/M or COP940CJ-XXX/M NS Package Number M28B www.national.com 34 COP840CJ/COP842CJ/COP940CJ/COP942CJ Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number COP842CJ-XXX/N or COP942CJ-XXX/N NS Package Number N20A Order Number COP840CJ-XXX/N or COP940CJ-XXX/N NS Package Number N28B 35 www.national.com COP840CJ/COP842CJ/COP940CJ/COP942CJ 8-Bit Microcontrollers with Multi-Input Wake-Up and Brown Out Detector Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.