MM54HC237/MM74HC237 3-to-8 Line Decoder With Address Latches General Description The 54HC/74HC logic family is speed, function and pin-out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by diodes to VCC and ground. These devices utilize advanced silicon-gate CMOS technology, to implement a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are low unless G1 is high and G2 is low. The ’HC237 is ideally suited for the implementation of glitch-free decoders in storedaddress applications in bus oriented systems. Features Y Y Y Y Typical propagation delay: 20 ns Wide supply range: 2 – 6V Latched inputs for easy interfacing Fanout of 10 LS-TTL loads Connection Diagram Dual-In-Line Package TL/F/5326 – 1 Top View Order Number MM54HC237 or MM74HC237 Truth Table INPUTS ENABLE OUTPUTS SELECT GL G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X X L H X X X X X X X L L L L L L L L L L L L L L L L L L L L H H H H L L L L L L L L L L L H H L H H H L L L L H L L L L H L L L L H L L L L L L L L L L L L L L L L L L L L H H H H L L L L H L L H L H H H L H H H L L L L L L L L L L L L L L L L H L L L L H L L L L H L L L L H H H L X X X Output corresponding to stored address, L; all others, H H e high level, L e low level, X e irrelevant C1995 National Semiconductor Corporation TL/F/5326 RRD-B30M105/Printed in U. S. A. MM54HC237/MM74HC237 3-to-8 Line Decoder With Address Latches January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V b 1.5 to VCC a 1.5V Operating Temp. Range (TA) MM74HC MM54HC b 0.5 to VCC a 0.5V g 20 mA Min 2 Max 6 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V g 25 mA g 50 mA b 65§ C to a 150§ C 600 mW 500 mW 260§ C DC Electrical Characteristics (Note 4) Symbol Parameter Conditions TA e 25§ C VCC 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 8.0 80 160 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units ns tPLH Maximum Propagation Delay A, B or C to any Y Output 20 41 tPLH Maximum Propagation Delay A, B or C to any Y Output 16 32 ns tPLH Maximum Propagation GL to any Y Output 22 44 ns tPHL Maximum Propagation Delay GL to any Y Output 17 33 ns tPLH Maximum Propagation Delay G1 or G2 to Output 16 35 ns tPHL Maximum Propagation Delay G1 or G2 to Output 14 25 ns tS Minimum Set Up Time at A, B and C Inputs 10 20 ns tH Minimum Hold Time at A, B and C Inputs b3 0 ns tW Minimum Pulse Width of Enabling Pulse at GL 9 16 ns AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA e 25§ C Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits tPLH Maximum Propagation Delay, A, B or C to any Y Output 2.0V 4.5V 6.0V 100 24 20 235 47 40 296 59 50 350 70 60 ns ns ns tPLH Maximum Propagation Delay, A, B or C to any Y Output 2.0V 4.5V 6.0V 80 19 17 185 37 31 233 47 40 276 55 47 ns ns ns tPLH Maximum Propagation GL to any Y Output 2.0V 4.5V 6.0V 125 25 20 250 50 43 315 63 54 373 75 63 ns ns ns tPHL Maximum Propagation Delay GL to any Y Output 2.0V 4.5V 6.0V 95 19 16 190 38 32 239 48 41 283 75 48 ns ns ns tPLH Maximum Propagation Delay, G1 or G2 to Output 2.0V 4.5V 6.0V 100 20 17 200 40 34 252 50 43 298 60 51 ns ns ns tPHL Maximum Propagation Delay G1 or G2 to Output 2.0V 4.5V 6.0V 73 15 12 145 29 25 183 37 31 216 43 37 ns ns ns tS Minimum Set Up Time at A, B and C Inputs 2.0V 4.5V 6.0V 100 20 17 125 25 21 150 30 25 ns ns ns tH Minimum Hold Time at A, B and C Inputs 2.0V 4.5V 6.0V 0 0 0 0 0 0 0 0 0 ns ns ns tW Minimum Pulse Width of Enabling Pulse at GL 2.0V 4.5V 6.0V 30 10 9 80 16 14 100 20 18 120 24 20 ns ns ns tTLH, tTHL Maximum Output Rise and Fall Time 2.0V 4.5V 6.0V 30 8 7 75 15 13 95 19 16 110 22 19 ns ns ns CPD Power Dissipation Capacitance (Note 5) 75 CIN Maximum Input Capacitance 5 pF 10 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 Functional Block Diagram TL/F/5326 – 2 Typical Application TL/F/5326 – 3 6-Line to 64-Line Decoder with Input Address Storage 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54HC237J or MM74HC237J NS Package Number J16A 5 MM54HC237/MM74HC237 3-to-8 Line Decoder With Address Latches Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM74HC237N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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