CGS700V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver Y General Description CGS700 is an off the shelf clock driver specifically designed for today’s high speed processors. It provides low skew outputs which are produced at different frequencies from three fixed input references. The XTALIN input pin is designed to be driven from three distinct crystal oscillators running at 25 MHz, 33 MHz or 40 MHz. The PLL, using a charge pump and an internal loop filter, multiplies this input frequency to create a maximum output frequency of four times the input. The device includes a TRI-STATEÉ control pin to disable the outputs while the PLL is still in lock. This function allows for testing the board without having to wait to acquire the lock once the testing is complete. (continued) Y Y Y Y Y Y Y Y Y Y Features Y Y Guaranteed and tested: Ð 500 ps pin-to-pin skew (tOSHL and tOSLH) on 1X outputs Y Y Guaranteed: Ð 400 ps pin-to-pin skew (tOSHL and tOSLH) on 1Xoutputs PentiumTM and PowerPCTM compatible Output buffer of nine drivers for large fanout 25 MHz – 160 MHz output frequency range Outputs operating at 4X, 2X, 1X of the reference frequency for multi-frequency bus applications Selectable output frequency TRI-STATE output control with the PLL is in the lock state Internal loop filter to reduce noise and jitter Separate analog and digital VCC and Ground pins Low frequency test mode by disabling the PLL Implemented on National’s Core CMOS process Symmetric output current drive: a 30 mA/ b 30 mA IOL/IOH 28-pin PCC for optimum skew performance Guaranteed 2k ESD protection Pin Description PLCC Package Connection Diagram Pin Pin Assignment for PLCC TL/F/11955 – 1 See NS Package Number V28A TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. PowerPCTM is a trademark of IBM. PentiumTM is a trademark of Intel Corporation. C1996 National Semiconductor Corporation TL/F/11955 Name Description 1 VCC Digital VCC 2 SKWSEL Skew Test Selector Pin 3 CLK4 4X Clock Output 4 VCC Digital VCC 5 XTALIN Crystal Oscillator Input 6 GND Digital Ground 7 CLK1Ð0 1X Clock Output 8 VCC Digital VCC 9 CLK1Ð1 1X Clock Output 10 GND Digital Ground 11 CLK1Ð2 1X Clock Output 12 TRI-STATE Output TRI-STATE Control 13 SKWTST Skew Testing Pin 14 CLK1Ð3 1X Clock Output 15 GND Digital Ground 16 CLK1Ð4 1X Clock Output 17 VCC Digital VCC 18 EXTCLK External Test Clock 19 GNDA Analog Ground 20 VCCA Analog VCC 21 EXTSEL External Clock Mux Selector 22 GND Digital Ground 23 CLK1Ð5 1X Clock Output 24 VCC Digital VCC 25 CLK1Ð6 1X Clock Output 26 CLK1SEL CLK1 Multiplier Selector 27 GND Digital Ground 28 CLK2 2X Clock Output RRD-B30M66/Printed in U. S. A. CGS700V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver September 1995 General Description (Continued) as SKWTST input frequency, while CLK2 is (/2 and CLK1 frequencies are (/4 respectively (refer to the truth table). In addition CLK1SEL functionality is also true under this test condition. Also included, are two EXTSEL and EXTCLK pins to allow testing the chip via an external source. The EXTSEL pin, once set to high, causes the External-ClockÐMux to change its input from the output of the VCO and Counter to the external clock signal provided via EXTCLK input pin. CLK1SEL pin changes the output frequency of the CLK1Ð0, CLK1Ð6 outputs. During normal operation, when CLK1SEL pin is high, these outputs are at the same frequency as the input crystal oscillator, while CLK2 and CLK4 outputs are at twice and four times the input frequency respectively. Once CLK1SEL pin is set to a low logic level, the CLK1 outputs will be at twice the input frequency, the same as the CLK2 output, with CLK4 output still being at four times the input frequency. In addition two other pins are added for increasing the test capability. SKWSEL and SKWTST pins allow testing of the counter’s output and skew of the output drivers by bypassing the VCO. In this test mode CLK4 frequency is the same Typical Application TL/F/11955 – 3 Block Diagram CGS700 TL/F/11955 – 2 Truth Table Input Output CLK1 SEL EXT SEL EXT CLK SKW SEL SKW TST TRI-STATE CLK4 CLK2 *H L X L X H 4 c fIN 2 c fIN fIN *L L X L X H 4 c fIN 2 c fIN 2 c fIN X H É X X H É É É H L X H É H 1 c ftst (/2 c ftst (/4 c ftst L L X H É H 1 c ftst (/2 c ftst (/2 c ftst X X X X X L Z Z Z *Steady State phase, frequency lock. http://www.national.com CLK1 2 CGS700 Absolute Maximum Ratings (Note A) Note B: Power dissipation is calculated using 49§ /W as the thermal coefficient for the PCC package at 225 LFM airflow. The input frequency is assumed @ 33 MHz with CLK4 at 132 MHz and CLK2 and CLK1’s being at 66 MHz. In addition the ambient temperature is assumed with power supply at 5.0V. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 0.5V to a 7.0V Supply Voltage (VCC) DC Input Voltage Diode Current (IIK) b 20 mA V e b0.5V a 20 mA V e VCC a 0.5V b 0.5V to VCC a 0.5V DC Input Voltage (VI) DC Output Diode Current (IO) b 20 mA V e b0.5V a 20 mA V e VCC a 0.5V b 0.5V to VCC a 0.5V DC Output Voltage (VO) g 60 mA DC Output Source or Sink Current (IO) DC VCC or Ground Current g 60 mA per Output Pin (ICC or IGND) b 65§ C to a 150§ C Storage Temperature (TSTG) Junction Temperature 150§ C Power Dissipation (Static and Dynamic) (Note B) 1400 mW Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) 4.5V to 5.5V 0V to VCC 0V to VCC Input Crystal Frequency 25 MHz to 40 MHz Operating Temperature (TA) 0§ C to a 70§ C External Clock Frequency (EXTCLK Pin) 1 MHz to 10 MHz XTALIN Duty Cycle Range 25/75 (75/25)% Input Rise and Fall Times (0.8V to 2.0V) Crystal Input 5 ns max All Other Inputs 10 ns max Typical iJA 0 LFM 54 § C/W 225 LFM 45 § C/W 500 LFM 38 § C/W 900 LFM 34 § C/W Note A: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation. DC Electrical Characteristics Over recommended operating free air temperature range. All typical values are measured at VCC e 5V, TA e 25§ C Symbol Parameter Conditions VCC e 4.5V – 5.5V TA e 0§ C–70§ C Min VIH Minimum Input High Level Voltage VIL Maximum Input Low Level Voltage VOH Minimum Output High Level Voltage VOL Maximum Output Low Level Voltage Typ Units Max 2.0 V 0.8 IOUT e b50 mA VCC b 0.1 IOH e b30 mA VCC b 0.6 V V IOUT e 50 mA 0.1 IOL e 30 mA 0.6 V IOHD High Level Output Current VOH e VCC b 1.0V 50 110 170 mA IOLD Low Level Output Current VOL e 1.0V 50 110 170 mA IIN Leakage Current VIN e 0.4V or 4.6V 50 mA IOZL/H Output Leakage Current CIN Input Capacitance 10.0 pF ICC Quiescent Digital a Analog Current (No Load) ICCT ICC per TTL Input VIN e VCC, GND VIN e VCC b 2.1, GND 3 b 50 3.0 5.0 mA 2.5 http://www.national.com CGS700 (Continued) AC Electrical Characteristics Over recommended operating free air temperature range. All typical values are measured at VCC e 5V, TA e 25§ C Symbol VCC e 4.5V – 5.5V FIN e 25 MHz – 40 MHz TA e 0§ C–70§ C CL e Circuit 1 and 2 RL e Circuit 1 and 2 Parameter Min trise Output Rise CLK4 CLK2 CLK1 ALL tfall Output Fall CLK4 CLK2 CLK1 ALL tskew Maximum Edgeto-Edge Output Skew a to a Edges a to a Edges a to a Edges Typ Units Notes ns (Notes 1, 5) ns (Notes 1, 5) 400 1000 1000 ps (Notes 2, 5) 100 ms 51 51 65 % (Notes 3, 5) (Notes 4, 5) Max 0.8V – 2.6V 1.0V – VCC b 1.0V 1.0V – VCC b 1.0V 2.0 0.8V – 2.0V 1.5 2.6V – 0.8V VCC b 1.0V – 1.0V VCC b 1.0V – 1.0V 2.0 2.0V – 0.8V 1.5 CLK1ÐCLK1 CLK1ÐCLK4 CLK2ÐCLK4 tlock Time to Lock the Output to the Synch Input tcycle Output Duty Cycle CLK1 Outputs CLK2 Output CLK4 Output 49 49 35 JLT Output Jitter (Long Term) 0.3 ns FMIN Minimum XTALIN Frequency 15 MHz FMAX Maximum XTALIN Frequency 43 MHz Circuit 1. Test Circuit for CLK1 and CLK2 TL/F/11955 – 4 Circuit 2. Test Circuit for CLK4 TL/F/11955 – 9 http://www.national.com 4 CGS700 (Continued) Note 1: trise and tfall parameters are measured at the pin of the device. Note 2: Skew is measured at 50% of VCC for CLK1 and CLK2 while it is measured @ 1.4V for CLK4. Limits are guaranteed by design. Note 3: Output duty cycle is measured at VDD/2 for CLK1 and CLK2 while it is measured @ 1.4V for CLK4. Limits are guaranteed by design. Note 4: Jitter parameter is characterized and is guaranteed by design only. It measures the uncertainty of either the positive or the negative edge over 1000 cycles. It is also measured at output levels of VCC/2. Refer to Figure 2 for further explanation. Note 5: The GNDA pins of the 700 must be as free of noise as possible for minimum jitter. Separate analog ground plane is recommended for the PCB. Also the VCCA pin requires extra filtering to further reduce noise. Ferrite beads for filtering and bypass capacitors are suggested for VCCA pin. TL/F/11955 – 5 TL/F/11955 – 6 TL/F/11955 – 7 FIGURE 1. Waveforms TL/F/11955 – 8 Jitter e l Period(1) b Period(n a 1) l e 300 ps for either the rising or falling edge, where n is 1 to 1000 cycles. FIGURE 2. Jitter Application References and Bibliography Information relating to EMI as well as general application issues are in the following application notes: AN-988ÐEMI App Note AN-640 AN-991 5 http://www.national.com CGS700V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver Ordering Information (Contact NSC Marketing for specific date of availability) CGS 700 T V Family Clock Generation and Support Packaging V e PCC Device Type 700 Operating Temperature Range Blank e Commercial T e Industrial Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Plastic Leaded Chip Carrier NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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