NSC 54ABT16245W-QML

54ABT16245
16-Bit Transceiver with TRI-STATE ® Outputs
General Description
The ’ABT16245 contains sixteen non-inverting bidirectional
buffers with TRI-STATE outputs and is intended for bus
oriented applications. The device is byte controlled. Each
byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the
direction of data flow through the device. The OE inputs
disable both the A and B ports by placing them in a high
impedance state.
n Separate control logic for each byte
n 16-bit version of the ’ABT245
n A and B output sink capability of 48 mA, source
capability of 24 mA
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9317501
Features
n Bidirectional non-inverting buffers
Package
Number
Military
54ABT16245W-QML
WA48A
Package Description
48-Lead Cerpack
Logic Symbol
DS100200-1
Pin Description
Pin Names
Description
OEn
Output Enable Input (Active Low)
T/Rn
Transmit/Receive Input
A0–A15
Side A Inputs/Outputs
B0–B15
Side B Inputs/Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation
DS100200
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54ABT16245 16-Bit Transceiver with TRI-STATE Outputs
August 1998
54ABT16245
Connection Diagram
Logic Diagrams
Pin Assignment for Cerpack
DS100200-3
DS100200-2
Functional Description
The ’ABT16245 contains sixteen non-inverting bidirectional
buffers with TRI-STATE outputs. The device is byte controlled with each byte functioning identically, but independent
of the other. The control pins can be shorted together to
obtain full 16-bit operation.
Inputs
OE1
Outputs
T/R1
L
L
Bus B0–B7 Data to Bus A0–A
7
L
H
Bus A0–A7 Data to Bus B0–B
7
H
X
HIGH-Z State on A0–A7, B0–B
Inputs
OE2
DS100200-4
7
Outputs
T/R2
L
L
Bus B8–B15 Data to Bus A8–A
15
L
H
Bus A8–A15 Data to Bus B8–B
15
H
X
HIGH-Z State on A8–A15, B8–B
15
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
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2
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
Over Voltage Latchup (I/O)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
VCC Pin Potential to
Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-off State
in the HIGH State
−65˚C to +150˚C
−55˚C to +125˚C
twice the rated IOL (mA)
−500 mA
10V
Recommended Operating
Conditions
−55˚C to +175˚C
Free Air Ambient Temperature
Military
Supply Voltage
Military
Minimum Input Edge Rate
Data Input
Enable Input
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
−0.5V to 5.5V
−0.5V to VCC
−55˚C to +125˚C
+4.5V to +5.5V
(∆V/∆t)
50 mV/ns
20 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
ABT16245
Units
VCC
Conditions
Min Typ Max
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VCD
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
2.0
V
Recognized HIGH Signal
0.8
V
Recognized LOW Signal
−1.2
V
Min
IIN = −18 mA (OEn, T/Rn)
IOH = −3 mA (An, Bn)
54ABT
2.5
V
Min
54ABT
2.0
V
Min
IOH = −24 mA (An, Bn)
0.55
V
Min
IOL = 48 mA (An, Bn)
5
µA
Max
VIN = 2.7V (OEn, T/Rn) (Note 3)
7
µA
Max
VIN = 7.0V (OEn, T/Rn)
100
µA
Max
VIN = 5.5V (An, Bn)
−5
µA
Max
VIN = 0.5V (OEn, T/Rn) (Note 3)
V
0.0
IID = 1.9 µA (OEn, T/Rn)
54ABT
5
IBVI
Input HIGH Current
VIN = VCC (OEn, T/Rn)
Breakdown Test
IBVIT
Input HIGH Current
Breakdown Test (I/O)
IIL
Input LOW Current
VID
Input Leakage Test
−5
4.75
VIN = 0.0V (OEn, T/Rn)
All Other Pins Grounded
IIH + I
Output Leakage Current
50
µA
0−
5.5V
VOUT = 2.7V (An, Bn); OE = 2.0V
Output Leakage Current
−50
µA
0−
5.5V
VOUT = 0.5V (An, Bn); OE = 2.0V
−275
mA
Max
VOUT = 0.0V (An, Bn)
50
µA
Max
VOUT = V
OZH
IIL + I
OZL
IOS
Output Short-Circuit Current
ICEX
Output High Leakage Current
−100
IZZ
Bus Drainage Test
100
µA
0.0
VOUT = 5.50V (An, Bn);
ICCH
Power Supply Current
100
µA
Max
All Outputs HIGH
ICCL
Power Supply Current
60
mA
Max
All Outputs LOW
ICCZ
Power Supply Current
100
µA
Max
OEn = VCC, T/Rn = GND or VCC
ICCT
Additional ICC/Input
Outputs Enabled
2.5
mA
Outputs TRI-STATE
2.5
mA
Outputs TRI-STATE
50
µA
CC
(An, Bn)
All Others GND
All others at VCC or GND
VI = V
Max
CC
− 2.1V
OEn, T/ Rn VI = VCC − 2.1V
Data Input VI = VCC − 2.1V
All others at VCC or GND
3
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54ABT16245
Absolute Maximum Ratings (Note 1)
54ABT16245
DC Electrical Characteristics
Symbol
(Continued)
Parameter
ABT16245
Units
VCC
mA/
Max
Conditions
Min Typ Max
ICCD
Dynamic ICC
No Load
0.1
MHz
Outputs Open
OEn = GND, T/Rn = GND or VCC
One Bit Toggling, 50% Duty Cycle
Note 3: Guaranteed, but not tested.
AC Electrical Characteristics
Symbol
Parameter
54ABT
Units
Fig.
No.
TA =
−55˚C to +125˚C
VCC = 4.5V–5.5V
CL = 50 pF
Min
Max
tPLH
Propagation
0.5
4.5
tPHL
Delay Data
0.5
5.2
ns
Figure 5
ns
Figure 4
ns
Figure 4
to Outputs
tPZH
Output Enable
0.8
6.4
tPZL
Time
0.9
6.9
tPHZ
Output Disable
1.3
6.9
tPLZ
Time
1.0
6.9
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
5
pF
VCC = 0.0V (OEn, T/Rn)
Conditions, TA = 25˚C
CI/O (Note 4)
Output Capacitance
11
pF
VCC = 5.0V (An, Bn)
Note 4: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
tPLH vs Temperature (TA)
CL = 50 pF, 1 Output Switching
tPHL vs Temperature (TA)
CL = 50 pF, 1 Output Switching
DS100200-13
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DS100200-14
4
54ABT16245
Capacitance
(Continued)
tPLH vs Load Capacitance
1 Output Switching, TA = 25˚C
tPHL vs Load Capacitance
1 Output Switching, TA = 25˚C
DS100200-15
DS100200-16
tPLH vs Load Capacitance
16 Outputs Switching, TA = 25˚C
tPHL vs Load Capacitance
16 Outputs Switching, TA = 25˚C
DS100200-17
DS100200-18
tPZL vs Temperature (TA)
CL = 50 pF, 1 Output Switching
tPLZ vs Temperature (TA)
CL = 50 pF, 1 Output Switching
DS100200-19
DS100200-20
tPZH vs Temperature (TA)
CL = 50 pF, 1 Output Switching
tPHZ vs Temperature (TA)
CL = 50 pF, 1 Output Switching
DS100200-21
DS100200-22
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Table.
5
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54ABT16245
Capacitance
(Continued)
tPZH vs Temperature (TA)
CL = 50 pF, 16 Outputs Switching
tPHZ vs Temperature (TA)
CL = 50 pF, 16 Outputs Switching
DS100200-23
DS100200-24
tPZL vs Temperature (TA)
CL = 50 pF, 16 Outputs Switching
tPLZ vs Temperature (TA)
CL = 50 pF, 16 Outputs Switching
DS100200-26
DS100200-25
tPZL vs Load Capacitance
16 Outputs Switching TA = 25˚C
tPZH vs Load Capacitance
16 Outputs Switching TA = 25˚C
DS100200-27
DS100200-28
tPLH vs Number Output Switching
VCC = 5.0V, TA = 25˚C, CL = 50 pF
tPHL vs Number Output Switching
VCC = 5.0V, TA = 25˚C, CL = 50 pF
DS100200-29
DS100200-30
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Table.
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6
54ABT16245
Capacitance
(Continued)
ICC vs Frequency
Average, TA = 25˚C, VCC = 5.5V
All Outputs Unloaded/Unterminated;
16 Outputs Switching In-Phase at 50% Duty Cycle
DS100200-31
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Table.
7
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54ABT16245
AC Loading
DS100200-8
FIGURE 4. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100200-5
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100200-9
FIGURE 5. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100200-7
FIGURE 2. Input Pulse Requirements
Amplitude
Rep. Rate
tw
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
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8
54ABT16245 16-Bit Transceiver with TRI-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Cerpack
NS Package Number WA48A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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