FPD03784 Low Power, Low EMI, TFT-LCD Column Driver with Dual, TTL Bus Inputs, 64 Grayshades, and 384 Outputs for XGA/SXGA Applications General Description Features The FPD03784 Column Driver is a direct drive, 64 gray level, 384 output, TFT-LCD column driver with a dual bus, TTL data interface. It provides the capability to display 262,144 colors (18-bit color) with a large dynamic output range for twisted nematic applications. When used in a bank with other FPD03784 column drivers, the FPD03784 can support both XGA (8 drivers) or SXGA (10 drivers) applications. Output voltages are gamma corrected programmably to provide a direct mapping between digital video and LCD panel brightness. The FPD03784 offers a low power, low EMI column driver solution with programmable output drive current and direct-drive dynamic range, and dot-inversion addressing. n n n n n n n n n Up to 65 MHz clock Supports both XGA and SXGA timing Supports notebook and monitor applications Charge Conservation for low power consumption 64 Gray levels per color (18-bit color) Externally programmable 2.2 gamma characteristic Supports both Dot and N-Line inversion Externally programmable gamma characteristic Programmable drivability allows optimization for small or large panel applications n Very low offsets for artifact-free images n High voltage outputs for high contrast in a large range of display panel applications System Diagram DS200152-1 © 2001 National Semiconductor Corporation DS200152 www.national.com FPD03784 Low Power, Low EMI, TFT-LCD Column Driver with Dual, TTL Bus Inputs, 64 Grayshades, and 384 Outputs for XGA/SXGA Applications November 2001 FPD03784 Absolute Maximum Ratings (Note 1) Analog Supply, (VDD2) (Note 2) Logic Supply, (VDD1) (Note 2) High Bias Supply, (VHBIAS) (Note 2) Low-Polarity RDAC Reference Voltages, (VGMA7 to VGMA12) (Note 2) High-Polarity RDAC Reference Voltages, (VGMA1 to VGMA6) (Note 2) RDAC Current (All Gamma Voltage Taps), (IGMA to IGMA12) Input Voltage (Digital Logic), (VIN) (Note 2) Output Voltage, (VOUT) (Note 2) Output Current (Analog), (IOUT) Input Current Source, (ISIN) Output Current Source, (ISOUT) IREF Current, (IREF) Storage Temperature Range, (TS) −0.3V to +10.5V −0.3V to +5.0V −0.3V to +12.0V −1mA to +0.2mA −55˚C to +125˚C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Absolute voltages referenced to VSS1 = VSS2 = 0.0V. −0.3V to 0.5VDD2 Recommended Operating Conditions 0.5VDD2 − 1.0V to VDD2 + 0.3V −2.5mA to 2.5mA Logic Supply Voltage (VDD1) (3.3V OR 2.5V) Supply Voltage (VDD2) Operating Temperature (TA) −0.3V to VDD1 + 0.3V −0.3V to VDD2 + 0.3V −7mA to +7mA −200µA to +200µA −200µA to +200µA Min 3.0 2.25 Typ 3.3 2.5 Max 3.6 2.75 Units V V 9.5 V +70 ˚C 7.5 −10 +25 DC Electrical Characteristics Digital Electrical Characteristics Symbol Parameter VIH Input High Voltage VIL Input Low Voltage Conditions Min Typ Max Units 0.7 VDD1 VOH Output High Voltage IOH = −0.5mA VOL Output Low Voltage IOL = 0.5mA V 0.3 VDD1 V 0.5 V VDD1 − 0.5 V IDD1 Logic Current (Note 3) 0.6 mA IDD1 Logic Current (Note 4) 0.36 mA IIH Input Leakage VDD1 = 3.6V, VIN = 3.6V 1 µA IIL Input Leakage VDD1 = 3.6V, VIN = 0V 1 µA CIN Input Capacitance 2 pF Note 3: CLK frequency = 32.5 MHz, VDD1 = 3.3V, VSS1 = VSS2 = 0.0V, RIREF = 220 kΩ, charge share time = 1.5µs, line time = 22µs. Note 4: CLK frequency = 32.5 MHz, VDD1 = 2.5V, VSS1 = VSS2 = 0.0V, RIREF = 220 kΩ, charge share time = 1.5µs, line time = 22µs. Analog Electrical Characteristics Symbol Parameter Conditions Min Typ Max Units IDD2 Supply Current Consumption (Note 5) 4.0 mA PD Power Dissipation (Note 5) 40 mW VGMA1 Upper RDAC High Side Input (Note 6) VDD2/2 + 0.2 VDD2 − 0.2 V VGMA6 Upper RDAC Low Side Input (Note 6) VDD2/2 + 0.2 VDD2 − 0.2 V VGMA7 Lower RDAC High Side Input VDD2 ≥ 8.5V(Note 6) 0.2 VDD2/2 − 0.2 VDD2 < 8.5V 0.2 VGMA12 Lower RDAC Low Side Input (Note 6) VHBIAS Voltage of High Bias Current Supply: VHBIAS = VDD2 VCS Separate VHBIAS Supply Charge Share Voltage VDD2/2 − 0.4 V V 0.2 VDD2/2 − 0.2 VDD2 VDD2 V ≥ VGMA1 + 1.5V and ≥ 8.5V VDD2 + 2.0 V The Greater of VDD1 or VGMA7 VGMA6 V CLOAD Output Capacitive Load 30 80 pF VOUT Output Voltage Range VSS2 + 0.2 VDD2 − 0.2 V AIREF IREF to IMAX Gain Factor www.national.com (Note 7) 8 2 10 12 Symbol Parameter AIHBIAS ISIN to IHBIAS Gain Factor (Continued) Conditions Min RCSTIME CSTIME resistance CCSTIME CSTIME capacitance ISIN Input Current Source 16 IREF Amplifier Reference Current 10 RDAC RDAC References (VGMA1 to VGMA6 and VGMA7 to VGMA12) each Vpperr Output Peak to Peak Error (gray levels 0 through 58) VGMA1 = VDD2 − 0.2V VGMA12 = VSS2 + 0.2V (Note 8) Output Peak to Peak Error (gray levels 59 through 63) Typ Max Units 22.5 5 12 12.0 kΩ 100 150 pF 40 100 µA 75 µA 15.0 18.0 kΩ ±3 ± 12 mV ±5 ± 25 mV Note 5: VDD2 = 9.5V, VHBIAS = 9.5V, RIREF = 220 kΩ, RISIN = 470 kΩ, VDD1 = 3.3V, DCLK = 65 MHz, RLOAD = 5 kΩ, CLOAD = 50 pF, charge share time = 1.5 µs, all other swinging between VGMA1 (= 8.0V) and VGMA12 (= 0.5V) with a line time = 22 µs. Note 6: The following relationship must be maintained between the reference voltages: VDD2 > VGMA8 > VGMA9 > VGMA10 > VGMA11 > VGMA12 > VSS2 > VGMA1 > VGMA2 > VGMA3 > VGMA4 > VGMA5 > VGMA6 > VGMA7 Note 7: IMAX is the current delivered into a potential of 0.2V when the output is commanded to a potential of VDD2 − 0.2V or the current into the output from a potential of VDD2 − 0.2V when the output is commanded to 0.2V (VSS2 = 0V). Note 8: This parameter reflects the error in peak-to-peak output voltage for each gray-level when the output swings from the gray-level high value, VHxx, to its low value, VLxx. This parameter applies to every output on the die. The Typical value represents one standard deviation from ideal based on tester data. The Maximum value is a constraint of the test environment, not the performance of the part. Note 9: Current into device pins is defined as positive. Current out of device pins is defined as negative. AC Electrical Characteristics Digital AC Characteristics (3.3V Logic) Symbol CLK Parameter Data Clock Frequency tWDCP CLK Clock Pulse Width tDSU Data Setup DX[5:0], POL, INVTxxx Conditions Min Typ Max Units SINGLE = 1 (Note 10) 65.0 MHz SINGLE = 0 (Note 10) 27.5 MHz SINGLE = 1 (Note 10) 5 ns SINGLE = 0 (Note 10) 10 ns 4 ns tDHLD Data Hold DX[5:0], POL, INVTxxx 4 ns tTWP LOAD Pulse Width 50 ns 200 ns tLDENSU LOAD to First ENIO Setup tENDCSU ENIOx Input to CLK Setup 2.5 ns tWEN ENIOx Input Pulse Width 10 ns tENPR ENIOx Output Prop Delay tLDLY Delay to LOAD Pulse (Note 11) Load = 20pF 12 3 ns CLKs Digital AC Characteristics (2.5V Logic) Symbol Parameter CLK Data Clock Frequency tWDCP CLK Clock Pulse Width Conditions Min SINGLE = 1 (Note 10) SINGLE = 0 (Note 10) tDSU Data Setup DX[5:0], POL, INVTxxx Typ Max Units 40.0 MHz 17.5 MHz SINGLE = 1 (Note 10) 10 ns SINGLE = 0(Note 10) 25 ns 4 ns tDHLD Data Hold DX[5:0], POL, INVTxxx 6 ns tTWP LOAD Pulse Width 50 ns tLDENSU LOAD to First ENIO Setup 200 ns tENDCSU ENIOx Input to CLK Setup 4 ns (Note 11) 3 www.national.com FPD03784 Analog Electrical Characteristics FPD03784 Digital AC Characteristics (2.5V Logic) Symbol Parameter tWEN ENIOx Input Pulse Width tENPR ENIOx Output Prop Delay tLDLY Delay to LOAD Pulse (Continued) Conditions Min Typ Max Units 19 ns 12 ns Load = 20pF 3 CLKs Note 10: Rise/Fall = 2.0ns max (10% to 90%) Note 11: Does not need to be synchronous to clock. Analog AC Characteristics Supplies: VSS1 = VSS2 = 0.0V, VDD1 = 3.3V, VDD2 = +9.5V, VHBIAS = 11.0V. Symbol Parameter Conditions Min Typ Max Units tsettle 90% Output Settling Time to 90% of Final Value RLOAD = 5kΩ, CLOAD = 40 pF (Note 12) 2.4 µs tsettle 99% Output Settling Time to 99% of Final Value RLOAD = 5kΩ, CLOAD = 40 pF (Note 12) 2.8 µs Note 12: ISIN = 40µA, IREF = 45µA, Charge Share Time = 400ns, VGMA1 = 9.3V, VGMA10 = 0.2V, VGMA5 = 5.2V, VGMA6 = 4.8V. www.national.com 4 FPD03784 Timing Diagrams DS200152-11 Note 13: LOAD pulse is asynchronous to CLK. It must meet minimum pulse-width, tLDENSU and tLDLY. Note 14: A minimum of 3 CLK cycles are required from the falling edge of CLK (on last data input to last chip) to the falling edge of the LOAD pulse. After these 3 CLK cycles, CLK may be disabled. 5 www.national.com FPD03784 Block Diagram DS200152-6 GAMMA CORRECTION The FPD03784 is designed to offer compatibility with a wide range of panel gamma characteristics. The output voltage levels corresponding to each of the 64 gray level commands can be externally adjusted to match the desired gamma characteristics of the display by means of two internal resistor-string DACs (RDACs). One RDAC provides the high-polarity output voltages (voltages higher than Vcom) and the other provides the low-polarity output voltages (voltages lower than Vcom). The default RDAC resistance values have been carefully designed to provide a smooth 2.2 gamma characteristic in a twisted nematic (TN) display. This is especially useful for monitor applications. Consequently, most application designs will only need to provide references for each of the two ends of the two RDACs (four gamma references). Additional, intermediate taps to the RDAC are also provided for optional customization of the display gamma for contrast control as an example. Functional Description GENERAL OVERVIEW The FPD03784 is a low power, low EMI, 384 output column driver with 64 gray level capability (6-bit). It provides direct drive for TFT-LCD displays, eliminating the need for Vcom modulation. Direct drive significantly reduces system power consumption and also reduces component count while providing superior image quality and cross-talk margin. The FPD03784 utilizes National’s Charge Conservation Technology that recovers energy stored in the capacitance of the column lines to reduce power consumption further. The FPD03784 is designed for use in systems using dot inversion as the method of polarity inversion. Column inversion and N-line inversion are also supported. Other modes of polarity inversion including line inversion and frame inversion are not supported. Digital video data inputs to the FPD03784 are received on six, six bit wide busses (dual bank, RGB busses) using TTL signaling. The digital video commands one of 64 gray level voltages on each output. Output voltages are driven with individual high drive, low offset, programmable-slew-rate, operational amplifiers. Data loading and line buffering is accomplished by means of an internal, bi-directional shift register. www.national.com CHARGE CONSERVATION TECHNOLOGY National Semiconductor’s proprietary charge conservation technology significantly reduces power consumption. Charge conservation works by briefly switching all of the columns at the start of each line to a common node. This has 6 sistor (RIREF) tied between the IREF pin (held by the FPD03784 at VDD1) and VSS1. Each driver IC must have a separate RIREF resistor (see Figure 1). (Continued) the effect of redistributing the charge stored in the capacitance of the panel columns. Since half the columns are at voltages more positive than Vcom and half are more negative, this redistribution of charge or “charge-sharing” has the effect of pulling all of the columns to a neutral voltage near the middle of the driver’s dynamic range. Thus, the voltages on all the columns are driven approximately halfway toward their next value with no power expended. This dramatically reduces panel power dissipation (up to a theoretical limit of 50%) compared to conventional drivers which must drive each column through the entire voltage swing every time polarity is reversed. ISIN — CURRENT SOURCE INPUT (INPUT) The ISIN current controls the bandwidth and settling performance of the FPD03784 output-stage amplifiers. Increasing ISIN increases the amplifier bandwidth and reduces settling time but also increases power consumption. Normally, ISIN is set to 40µA, which provides a good balance between power consumption and amplifier bandwidth. The flexibility to adjust ISIN accommodates very fast rise times (ISIN > 40µA) or applications where low power is of extreme interest (ISIN < 40µA). The ISIN current is supplied through an external resistor (RISIN) connected between the ISIN pin and VDD2. RISIN can be computed as follows: PIN DESCRIPTIONS The pin order configuration for the FPD03784 is shown in fig. 3. Optional pins do not need to be carried off a custom TCP or COP package but may require a connection to a neighboring pad on the die by a tie on the tape. The following paragraphs describe the function of the FPD03784 pins. CSTIME — CHARGE SHARE TIME (INPUT) (ISIN normally = 40µA) One resistor (RISIN) is needed for the entire display. This resistor is connected to the ISIN input of the first driver, and the current going into this pin is copied to the ISOUT output pin for cascading to the next driver. See Figure 1. Note that IHBIAS varies linearly with ISIN. ISOUT — CURRENT SOURCE OUTPUT (OUTPUT) The input controls how long the outputs are in charge share mode following each LOAD signal. The CSTIME input from all of the column drivers should be tied together and connected to VSS1 through a parallel combination of RC. The charge time is determined by the equation: Tcharge share = 0.69 RC This output pin supplies the ISIN current to the ISIN input pin of the next driver in the row (see Figure 1). The ISOUT pin of the last driver should be left floating. Optionally, this pin can be left floating on each driver if the designer wishes to provide a separate ISIN source to each driver. While this adds resistor component count, it reduces input lead count. LOAD — DATA LOAD (INPUT) A typical capacitance of 100pF should be chosen to swamp parasitic board and I/O pin effects. See Figure 1. CLK — DATA CLOCK (INPUT) Clock input for data on Dx[0:5]. DX[5:0] — DATA BUS (INPUT) DA[5:0] — Data Input Pins for OUTPUTS 1, 7...379 DB[5:0] — Data Input Pins for OUTPUTS 2, 8...380 DC[5:0] — Data Input Pins for OUTPUTS 3, 9...381 DD[5:0] — Data Input Pins for OUTPUTS 4, 10...382 DE[5:0] — Data Input Pins for OUTPUTS 5, 11...383 DF[5:0] — Data Input Pins for OUTPUTS 6, 12...384 ENIO1/ENIO2 — DATA LOADING ENABLE 1 AND 2 (I/O) The falling edge of LOAD copies the digital video buffered by the shift register into a second latch beginning the D to A conversion. Immediately following the fall of LOAD, the outputs are forced into charge share mode for the time set by the CSTIME input. The outputs then drive the D to A converted voltages following the CSTIME. POL — POLARITY (INPUT) When POL = L, odd numbered outputs (1, 3, 5, ...383) are controlled by VGMA7 through VGMA12 and even numbered outputs are controlled by VGMA1 through VGMA6. When POL = H, odd numbered outputs are controlled by VGMA1 through VGMA6 and even numbered outputs are controlled by VGMA7 through VGMA12. SINGLE — SINGLE/DUAL-EDGE CLOCK ENABLE (INPUT) If UP = H, then the ENIO1 pin is configured as an input and the ENIO2 pin is configured as an output. If UP = L, then the ENIO2 pin is configured as an input and the ENIO1 pin is configured as an output. INVTABC — DIGITAL DATA INVERT (INPUT) When INVERT = L, input data from DA[0:5], DB[0:5] and DC[0:5] is inverted. The INVTABC pin can be tied to INVTDEF on the TCP to form a single INVERT pin, or operated independently from each other. INVTDEF — DIGITAL DATA INVERT (INPUT) This pin controls single/dual-edge clocking. When SINGLE is high, single-edge clocking is enabled, and input data is latched only on the falling edge of CLK. When SINGLE is low, dual-edge clocking is enabled, and input data is latched on both the rising and falling edges of CLK. When INVERT = H, input data from DD[0:5], DE[0:5] and DF[0:5] is inverted. The INVTABC pin can be tied to INVTDEF on the TCP to form a single INVERT pin, or operated independently from each other. IREF — REFERENCE CURRENT FOR OUTPUT DRIVE (INPUT) Optional — The SINGLE die pad is bounded on each side by a logic High and a logic Low pad. This allows the state of SINGLE to be chosen on the TCP to eliminate an input pin. UP — DATA SHIFT DIRECTION — UP OR DOWN (INPUT) The UP pin controls the data shift direction. If UP is high then data is shifted “up” from output 1 to output 384, ENIO1 is configured as an input, and ENIO2 is an output. If UP is low then data is shifted “down” from output 384 to output 1, ENIO2 is an input, and ENIO1 is an output. The IREF input allows the designer to set the maximum output drive current (IMAX) of the FPD03784 suitable for the column line, RC network load. Current flow out of the IREF pin is used to set the rise and fall slew rate of the output waveform. This current is supplied through an external re- 7 www.national.com FPD03784 Functional Description FPD03784 Functional Description Option – Any or all of the inputs VGMA2 through VGMA5 and VGMA8 through VGMA11 can be left undriven (floating) at the designer’s option to eliminate input pins and/or external reference circuitry. VHBIAS — HIGH BIAS CURRENT VOLTAGE SUPPLY Optional positive supply voltage that provides a constant bias current to the output amplifiers to extend dynamic range. When separately provided, VHBIAS must be 1.5V greater than VGMA1 (see Table iii for limits). When not separately provided, VHBIAS must be supplied by VDD2. In this configuration, VGMA1 must be held at or below VDD2 − 1.5V (see table iii for limits). VSS1 — DIGITAL GROUND Digital ground reference voltage. VSS2 — ANALOG GROUND Analog ground reference voltage. (Continued) Optional — The UP die pad is bounded on each side by a logic High and a logic Low pad. This allows the state of UP to be chosen on the TCP to eliminate an input pin. VCS — CHARGE SHARE VOLTAGE REFERENCE This input provides the reference for the common node voltage during charge share time. VDD1 — DIGITAL VOLTAGE SUPPLY Positive supply voltage for the digital logic functions of the driver. VDD2 — ANALOG VOLTAGE SUPPLY Positive supply voltage for the analog functions of the driver. VGMA1–VGMA12 — RDAC REFERENCES (INPUTS) The reference voltages to the upper and lower RDACs used to control the inverse gamma transfer function of the driver. DS200152-8 FIGURE 1. External Components and Connections for the IREF, ISIN and ISOUTPins www.national.com 8 FPD03784 Functional Description (Continued) RH1 RDAC x 46/1008 RH32 RDAC x 7/1008 RH2 RDAC x 40/1008 RH33 RDAC x 7/1008 RH3 RDAC x 39/1008 RH34 RDAC x 7/1008 RH4 RDAC x 38/1008 RH35 RDAC x 6/1008 RH5 RDAC x 37/1008 RH36 RDAC x 6/1008 RH6 RDAC x 32/1008 RH37 RDAC x 6/1008 RH7 RDAC x 30/1008 RH38 RDAC x 7/1008 RH8 RDAC x 29/1008 RH39 RDAC x 7/1008 RH9 RDAC x 29/1008 RH40 RDAC x 6/1008 RH10 RDAC x 26/1008 RH41 RDAC x 7/1008 RH11 RDAC x 21/1008 RH42 RDAC x 6/1008 RH12 RDAC x 19/1008 RH43 RDAC x 7/1008 RH13 RDAC x 17/1008 RH44 RDAC x 6/1008 RH14 RDAC x 17/1008 RH45 RDAC x 7/1008 RH15 RDAC x 15/1008 RH46 RDAC x 8/1008 RH16 RDAC x 14/1008 RH47 RDAC x 7/1008 RH17 RDAC x 13/1008 RH48 RDAC x 7/1008 RH18 RDAC x 13/1008 RH49 RDAC x 7/1008 RH19 RDAC x 11/1008 RH50 RDAC x 8/1008 RH20 RDAC x 10/1008 RH51 RDAC x 8/1008 RH21 RDAC x 10/1008 RH52 RDAC x 8/1008 RH22 RDAC x 9/1008 RH53 RDAC x 9/1008 RH23 RDAC x 9/1008 RH54 RDAC x 9/1008 RH24 RDAC x 9/1008 RH55 RDAC x 8/1008 RH25 RDAC x 9/1008 RH56 RDAC x 10/1008 RH26 RDAC x 8/1008 RH57 RDAC x 12/1008 RH27 RDAC x 8/1008 RH58 RDAC x 13/1008 RH28 RDAC x 7/1008 RH59 RDAC x 14/1008 RH29 RDAC x 7/1008 RH60 RDAC x 15/1008 RH30 RDAC x 7/1008 RH61 RDAC x 23/1008 RH31 RDAC x 7/1008 RH62 RDAC x 36/1008 RH63 RDAC x 128/1008 DS200152-9 FIGURE 2. FPD03784 R-DAC Transfer Characteristic 9 www.national.com FPD03784 Functional Description (Continued) RL1 RDAC x 46/1008 RL32 RDAC x 7/1008 RL2 RDAC x 40/1008 RL33 RDAC x 7/1008 RL3 RDAC x 39/1008 RL34 RDAC x 7/1008 RL4 RDAC x 38/1008 RL35 RDAC x 6/1008 RL5 RDAC x 37/1008 RL36 RDAC x 6/1008 RL6 RDAC x 32/1008 RL37 RDAC x 6/1008 RL7 RDAC x 30/1008 RL38 RDAC x 7/1008 RL8 RDAC x 29/1008 RL39 RDAC x 7/1008 RL9 RDAC x 29/1008 RL40 RDAC x 6/1008 RL10 RDAC x 26/1008 RL41 RDAC x 7/1008 RL11 RDAC x 21/1008 RL42 RDAC x 6/1008 RL12 RDAC x 19/1008 RL43 RDAC x 7/1008 RL13 RDAC x 17/1008 RL44 RDAC x 6/1008 RL14 RDAC x 17/1008 RL45 RDAC x 7/1008 RL15 RDAC x 15/1008 RL46 RDAC x 8/1008 RL16 RDAC x 14/1008 RL47 RDAC x 7/1008 RL17 RDAC x 13/1008 RL48 RDAC x 7/1008 RL18 RDAC x 13/1008 RL49 RDAC x 7/1008 RL19 RDAC x 11/1008 RL50 RDAC x 8/1008 RL20 RDAC x 10/1008 RL51 RDAC x 8/1008 RL21 RDAC x 10/1008 RL52 RDAC x 8/1008 RL22 RDAC x 9/1008 RL53 RDAC x 9/1008 RL23 RDAC x 9/1008 RL54 RDAC x 9/1008 RL24 RDAC x 9/1008 RL55 RDAC x 8/1008 RL25 RDAC x 9/1008 RL56 RDAC x 10/1008 RL26 RDAC x 8/1008 RL57 RDAC x 12/1008 RL27 RDAC x 8/1008 RL58 RDAC x 13/1008 RL28 RDAC x 7/1008 RL59 RDAC x 14/1008 RL29 RDAC x 7/1008 RL60 RDAC x 15/1008 RL30 RDAC x 7/1008 RL61 RDAC x 23/1008 RL31 RDAC x 7/1008 RL62 RDAC x 36/1008 RL63 RDAC x 128/1008 DS200152-10 FIGURE 3. FPD03784 R-DAC Transfer Characteristic (continued) www.national.com 10 FPD03784 FPD03784 I/O Configuration optional OUTPUTS POL 384 VCS 383 SINGLE 382 optional UP 381 DF[5] 380 DF[4] . DF[2] . DF[1] . DF[0] . VSS1/2 . . DE[0] . DE[1] . DE[3] DE[4] FPD03784 VDD2 DE[5] DD[5] DD[4] DD[3] . VGMA1 . VGMA6 . VGMA7 . optional VGMA2 . optional VGMA3 . optional VGMA4 . optional VGMA5 . optional VGMA8 . optional VGMA9 . optional VGMA10 . optional VGMA11 . DB[5] . DB[4] . DB[3] . DB[2] . . . . . . DD[0] . . . DC[2] . DC[3] . DC[4] . DC[5] . CLK VDD1 DA[0] . . DC[1] DB[0] . DD[1] DC[0] DB[1] . DD[2] OUTPUTS VGMA12 379 DF[3] DE[2] (Continued) INPUTS . . (Continued top of next column) optional optional FPD03784 INPUTS . . . DA[1] . DA[2] . DA[3] . DA[4] . DA[5] . VDD2 . VSS1/2 . VHBIAS . ENIO2 . ENIO1 . LOAD . CSTIME 6 IREF 5 ISIN 4 ISOUT 3 INVTABC 2 INVTDEF 1 Note:This figure represents an FPD03784 die oriented pad side up. Packaging The FPD03784 is available as singulated die. 11 www.national.com FPD03784 Low Power, Low EMI, TFT-LCD Column Driver with Dual, TTL Bus Inputs, 64 Grayshades, and 384 Outputs for XGA/SXGA Applications LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.