TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 • • • • • • • • LinEPIC 1-µm CMOS Process 125-MHz Pipelined Architecture Available Clock Rates . . . 80, 110, 125, 135 MHz Dual-Port Color RAM 256 Words x 24 Bits Bit Plane Read and Blink Masks EIA RS-343-A Compatible Outputs Functionally Interchangeable With Brooktree Bt458 • • • • • Direct Interface to TMS340XX Graphics Processors Standard Microprocessor Unit (MPU) Palette Interface Multiplexed TTL Pixel Ports Triple Digital-to-Analog Converters (DACs) Dual-Port Overlay Registers . . . 4 × 24 Bits 5-V Power Supply description The TLC34058 color-palette integrated circuit is specifically developed for high-resolution color graphics in such applications as CAE/CAD/CAM, image processing, and video reconstruction. The architecture provides for the display of 1280 × 1024 bit-mapped color graphics (up to 8 bits per pixel resolution) with 2 bits of overlay information. The TLC34058 has a 256-word × 24-bit RAM used as a lookup table with three 8-bit video D/A converters. On-chip features such as high-speed pixel clock logic minimize costly ECL interface. Multiple pixel ports and internal multiplexing provide TTL-compatible interface (up to 32 MHz) to the frame buffer while maintaining sophisticated color graphic data rates (up to 135 MHz). Programmable blink rates, bit plane masking and blinking, color overlay capability, and a dual-port palette RAM are other key features. The TLC34058 generates red, green, and blue signals compatible with EIA RS-343-A and can drive, without external buffering, 75-Ω coaxial cables terminated at each end. AVAILABLE OPTIONS TA 0°C To 70°C 70 C SPEED DAC RESOLUTION Ceramic Grid Array (GA) 80 MHz 8 Bits TLC34058-80GA TLC34058-80FN 110 MHz 8 Bits TLC34058-110GA TLC34058-110FN 125 MHz 8 Bits TLC34058-125GA TLC34058-125FN 135 MHz 8 Bits TLC34058-135GA TLC34058-135FN PACKAGE Plastic Chip Carrier (FN) LinEPIC is a trademark of Texas Instruments Incorporated. Brooktree is a registered trademark of Brooktree Corporation. Copyright 1991, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 84ĆPIN GA PACKAGE (TOP VIEW) 84ĆPIN GA PACKAGE (BOTTOM VIEW) P5C P5E P6B P6C P6E P7B P7D VDD GND COMP P4C P5A P5D P6A P6D P7A P7C P7E VDD GND P4B P4D VDD P7D P7B P6E P6C P6B P5E P5C P5B P4E 12 11 IOB VDD P7E P7C P7A P6D P6A P5D P5A P4C P4A 11 10 IOG P4D P4B SYNC 9 VDD BLK LD 9 LD BLK IOR VDD 8 C1 R/W CLK CLK 8 CLK CLK R/W C1 7 VDD C0 VDD VDD 7 VDD VDD C0 VDD 6 GND GND P3E GND 6 GND P3E GND GND 5 CE D7 P3C P3D 5 P3D P3C D7 4 D6 D5 P3A P3B 4 P3B P3A GND FS ADJ REF IOR (ESD SYMBOL OR ALIGNMENT P4E P5B 12 COMP GND P4A 10 SYNC REF (ESD SYMBOL OR ALIGNMENT DOT - ON TOP) P2A D0 P2C P2E D4 D2 2 D3 D1 OL0B OL0E OL1B OL1E P0B P0D P1A P1D P1E 1 OL0A OL0C OL0D OL1A OL1C OL1D P0A P0C P0E P1B P1C C D G H B E F J K L 3 P2E P2C P2A P2D 2 P2D P1E P1D P2B 1 P2B P1C M M L P1B K D0 P1A D6 D2 D4 OL1E OL1B OL0E OL0B D1 D3 P0E P0C P0A OL1D OL1C OL1A OL0D OL0C OL0A J H G D C B A F 8 7 6 5 4 3 2 E 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 72 15 71 16 70 17 69 18 68 19 67 20 66 21 65 22 64 23 63 24 62 25 61 26 60 27 59 28 58 29 57 30 56 31 55 32 54 P7E P7D P7C P7B P7A P6E P6D P6C P6B P6A P5E P5D P5C P5B P5A P4E REF GND VDD GND VDD 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 2 D5 P0B P1C P1D P1E P2A OL0A OL0B OL0C OL0D OL0E OL1A OL1B OL1C OL1D OL1E P0A P0B P0C P0D P0E P1A P1B 11 10 9 CE P0D FN PACKAGE (TOP VIEW) D0 D1 D2 D3 D4 D5 D6 D7 CE GND GND VDD C0 C1 R/W VDD IOR IOG IOB FS ADJ COMP IOG DOT - ON TOP) 3 A FS ADJ IOB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P2B P2C P2D P2E P3A P3B P3C P3D P3E GND VDD VDD CLK CLK LD BLK SYNC P4A P4B P4C P4D TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 84-pin GA package pin assignments SIGNAL BLK SYNC PIN NO. L9 SIGNAL PIN NO. PORT 5 PIN NO. POWER, REFERENCE M10 P5A LD M9 P5B L12 CLK L8 P5C K12 CLK M8 P5D J11 P5E PORT 0 SIGNAL K11 AND MPU INTERFACE VDD VDD C12 A9 J12 VDD VDD M7 PORT 6 C11 L7 P0A G1 P6A H11 VDD VDD P0B G2 P6B H12 GND B12 P0C H1 P6C G12 GND B11 P0D H2 P6D G11 GND M6 P0E J P6E F12 GND B6 PORT 1 PORT 7 GND A7 A6 P1A J2 P7A F11 COMP A12 P1B K1 P7B E12 FS ADJ B10 P1C L1 P7C E11 REF C10 P1D K2 P7D D12 CE A5 P1E L2 P7E D11 R/W B8 C1 A8 C0 B7 PORT 2 OVERLAY SELECT 0 P2A K3 OL0A A1 P2B M1 OL0B C2 P2C L3 OL0C B1 D0 C3 P2D M2 OL0D C1 D1 B2 P2E M3 OL0E D2 D2 B3 D3 A2 PORT 3 OVERLAY SELECT 1 DATA BUS P3A L4 OL1A D1 D4 A3 P3B M4 OL1B E2 D5 B4 P3C L5 OL1C E1 D6 A4 P3D M5 OL1D F1 D7 B5 P3E L6 OL1E F2 PORT 4 DAC CURRENT OUTPUTS P4A M11 IOG A10 P4B L10 IOB A11 P4C L11 IOR B9 P4D K10 P4E M12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 functional block diagram REF FS ADJ CLK CLK Load Control Mux Control Reference Amplifier Blink Control COMP LD P0 – P7 (A – E) 40 10 OL0 – OL1 (A – E) 40 Input Latch 10 40 Latch 10 8 8 Mux 2 Read Mask Blink Mask 8 256 Words × 24 Bits Palette 2 Ram 4 × 24 Overlay Palette Registers SYNC BLK CE R/W Bus Control C0 To Control Functions C1 D0 – D7 8 8 8 4 Address Register To Address Control Functions Red Value Green Value Blue Value POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 8 8 8-Bit D/A Converter IOR 8-Bit D/A Converter IOG 8-Bit D/A Converter IOB TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 Terminal Functions PIN NAME I/O DESCRIPTION BLK I Composite blank control. This TTL-compatible blanking g input is stored in the input latch on the rising g edge g of LD. When low, BLK drives the DAC outputs to the blanking g level, as shown in Table 6. This causes the P0 – P7 [A – E] and OL0 – OL1 [A – E] inputs to be ignored. When high, BLK allows the device to perform in the standard manner. C0, C1 I Command control inputs. The inputs specify y the type y of write or read operation ((see Tables 1, 2, 3, and 4). ) These TTL-compatible inputs are latched on the falling edge of CE. CE I Chip enable. This TTL-compatible input control allows data to be stored and enables data to be written or read (see ( Figure 1). When low, CE enables data to be written or read. When high, g g CE allows data to be internally latched on the rising edge during write operations. Care should be taken to avoid transients on this input. CLK I Clock. This input provides the pixel clock rate. CLK and CLK inputs are designed g to be driven by y ECL logic g using g a 5-V single supply. CLK I Clock. This input is the complement of CLK and also provides the pixel clock rate. COMP I Compensation. This input is used to compensate the internal reference amplifier (see ( the video generation g section). ) A 0.1-µF µ ceramic capacitor is connected between this pin and VDD (see Figure g 4). The highest g possible supply voltage g rejection ratio is attained by connecting the capacitor to VDD rather than to GND. D0 – D7 I Data input bus. This TTL-compatible bus transfers data into or out of the device. The data bus is an 8-bit bidirectional bus where D0 is the least significant bit. FS ADJ I Full-scale adjust j control. A resistor Rset, (see ( Figure g 4)) which is connected between this pin and GND,, controls the magnitude of the full-scale video signal. Note that the proportional current and voltage 3 are g g g relationships in Figure g maintained independent of the full-scale output current. The relationships between Rset and the IOR, IOG, and IOB full-scale output currents are: Rset(Ω) = 11294 × Vref(V) / IOG(mA) IOG( A) IOR IOB (mA) = 8067 × Vref(V) / Rset(Ω) IOR, GND Ground. All GND pins must be connected together. IOR, IOG IOB O Current outputs, red, green, g and blue. High-impedance g red, green, g and blue video analog g current outputs can directlyy drive a 75-Ω coaxial terminated at each end (see Figure 4). LD I Load control. This TTL-compatible load control input latches the P0 – P7 [[A – E], ], OL0 – OL1 [[A – E], ], BLK,, and SYNC inputs on its rising edge. The LD strobe occurs at 1/4 or 1/5 the clock rate and may be phase independent of the CLK and CLK inputs. The LD duty cycle limits are specified in the timing requirements table. OL0A – OL1A OL0B – OL1B O 0C – OL1C O C OL0C OL0D – OL1D OL0E – OL1E l P0A – P7A P0B – P7B P0C – P7C P0D – P7D P0E – P7E l inputs. TTL-compatible inputs input Overlay selection in uts. These TTL com atible selection in uts for the Palette overlay registers are stored in the in ut latch on the rising edge of LD. These in inputs uts (u (up to 2 bits per er pixel), ixel), along with bit CR6 of the command register (refer to tthe e co a d register eg ste sect o a d Table ab e 5), sspecify ec y whether et e tthe e co o information o at o is s se ected from o tthe e palette a ette RAM command section and color selected or the overlayy registers. If the color information is selected from the overlay g y registers, g , the OL0 – OL1 [A [ – E]] inputs g y input to the address a particular overlayy register. The OL0 – OL1 [[A – D]] or OL0 – OL1 [[A – E]] inputs are simultaneously device ((see the description of bit CR7 in the command register section). g ) The OL0 – OL1 [[A]] inputs are processed first,, then the OL0 – OL1 [[B]] inputs,, and so on. When obtaining g the color information from the overlay y registers, g , the P0 – P7 [A – E] inputs are ignored. Unused inputs should be connected to GND. Address inputs. These TTL-compatible address inputs for the Palette RAM are stored in the input latch on the rising g edge g of LD. These address inputs (up to 8-bits per pixel) select one of 256 24-bit words in the palette RAM, which is subsequently input to the red, green, and blue D/A converters as three 8-bit or 4-bit bytes. Four or five addresses are simultaneously input to the P0 – P7 [A – D] or P0 – P7 [A – E] ports, respectively (see the description of bit CR7 in the d register i t section). ti ) Th d addressed dd db d addressed dd db command The word by P0A – P7A iis fifirstt sentt tto th the DAC DACs, th then th the word by P0B – P7B, P7B and so on on. Unused inputs should be connected to GND GND. REF I Reference voltage. 4,, is sugg 1.235-V is supplied at this input. An external voltage g reference circuit,, shown in Figure g g gested. Generating g g the reference voltage g with a resistor network is not recommended since low-frequency power supply noisewill directly couple into the DAC output signals. This input must be decoupled by connecting a 0.1-µF ceramic capacitorbetween VREF and GND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 Terminal Functions (continued) PIN NAME I/O DESCRIPTION R/W I Read/write in input ut. This TTL-compatible TTL-com atible control input in ut is latched on the falling edge of CE (see Figure 1). 1) When low, low writes data to the device. high reads data from the device. device device Data is internally latched on the rising edge of CE. CE When high, SYNC I Composite input Com osite sync control. This TTL-compatible TTL com atible sync control input in ut is stored in the in ut latch on the rising edge of LD. When low, ut, as shown in Figure 3. ut does not override any output 3 This in input low SYNC turns off a 40 IRE current source on the IOG out control data in ut, as shown in Table 6. 6 It should be brought low during the blanking interval only, only as shown in Figure 3. 3 input manner When high high, SYNC allows the device to perform in the standard manner. VDD Supply voltage. All VDD pins must be connected together. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage range on any digital input (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 5 V to VDD + 0.5 V Analog output short circuit duration to any power supply or common, IOS . . . . . . . . . . . . . . . . . . . . . unlimited Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: GA package . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND terminal. recommended operating conditions Supply voltage, VDD CLK, CLK High level Input voltage, High-level voltage VIH NOM 4.75 5 MAX UNIT 5.25 V VDD – 1 2 VDD + 0.5 VDD + 0.5 V CLK, CLK – 0.5 V Other inputs – 0.5 VDD – 1.6 0.8 Other inputs Low level Input voltage, Low-level voltage VIL MIN Reference voltage, Vref 1.2 1.235 1.26 V V V Output load resistance, RL 37.5 Ω FS ADJ resistor, Rset 523 Ω Operating free-air temperature, TA 6 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 70 °C TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature, Rset = 523 Ω, Vref = 1.235 V (unless otherwise noted) PARAMETER Iref Input reference current kSVR Supply voltage rejection ratio IDD IIH TEST CONDITIONS MIN f = 1 kHZ,, C8 = 0.1 µF (see Figure 4) % %∆VDD 175 110 MHz VDD = 5 V, VDD = 5.25 V, TA = 20°C TA = 0°C 195 125 MHz VDD = 5 V, VDD = 5.25 V, TA = 20°C TA = 0°C 205 135 MHz VDD = 5 V, VDD = 5.25 V, TA = 20°C TA = 0°C 200 CLK, CLK 420 mA 435 435 1 µA 1 µA VI = 0.4 V VI = 0.4 V –1 µA Low level input current Low-level Ci Input capacitance, digital f = 1 MHz, Ci(CLK) Input capacitance, CLK, CLK f = 1 MHz, VOH VOL High-level output voltage, D0 – D7 IOH = – 800 µA IOL = 6.4 mA IOZ zo High-impedance-state output current Other inputs 400 VI = 4 V VI = 2.4 V IIL Low-level output voltage, D0 – D7 05 0.5 TA = 20°C TA = 0°C Other inputs UNIT µA VDD = 5 V, VDD = 5.25 V, CLK, CLK MAX 10 80 MHz Supply current High level input current High-level TYP† VI = 2.4 V VI = 4 V –1 µA 4 10 pF 4 10 pF 2.4 V 0.4 10 Output impedance 50 Co Output capacitance (f = 1 MHz, IO = 0) † All typical values are at TA = 25°C. POST OFFICE BOX 655303 13 • DALLAS, TEXAS 75265 V µA kΩ 20 pF 7 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 timing requirements over recommended ranges of supply voltage and operating free-air temperature, Rset = 523 Ω, Vref = 1.235 V (see Note 2) TIMING† REFERENCE LIMIT Clock frequency – MAX 135 125 110 80 MHz LD frequency – MAX 33.75 31.25 27.5 20 MHz Setup time, R/W, C0, C1 high before CE ↓ 1 MIN 0 0 0 0 ns Hold time, R/W, C0, C1 high after CE ↓ 2 MIN 15 15 15 15 ns Pulse duration, CE low 3 MIN 50 50 50 50 ns Pulse duration, CE high 4 MIN 25 25 25 25 ns Setup time, write data before CE ↑ 8 MIN 35 35 35 50 ns Hold time, write data after CE ↓ 9 MIN 0 0 0 0 ns Pixel and control setup time 10 MIN 3 3 3 4 ns Pixel and control hold time 11 MIN 2 2 2 2 ns Clock cycle time 12 MIN 7.4 8 9.09 12.5 ns Pulse duration, CLK high 13 MIN 3 3.2 4 5 ns Pulse duration, CLK low 14 MIN 3 3.2 4 5 ns LD cycle time 15 MIN 29.6 32 36.36 50 ns LD pulse duration high time 16 MIN 12 13 15 20 ns PARAMETER VERSION 135 MHz 125 MHz 110 MHz 80 MHz UNITS LD pulse duration low time 17 MIN 12 13 15 20 ns † See Figures 1 and 2. NOTE 2. TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECL input signals are VDD – 1.8 V to VDD – 0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference points are at the 50% signal level. Analog output loads are less than 10 pF. D0 – D7 output loads are less than 40 pF. operating characteristics over recommended ranges of supply voltage and operating free-air temperature, Rset = 523 Ω, Vref = 1.235 V (unless otherwise noted) analog outputs PARAMETER EL ED IO MAX UNIT ±1 LSB Differential linearity error ±1 LSB Gray scale error ±5 Output current MIN White level relative to blank 17.69 19.05 20.4 White level relative to black 16.74 17.62 18.5 Black level relative to blank 0.95 1.44 1.9 mA 0 5 50 µA Blank level on IOG 6.29 7.6 8.96 mA Sync level on IOG 0 5 50 µA Blank level on IOR, IOB LSB size µA 69.1 DAC to DAC matching 2% Output compliance voltage † All typical values are at TA = 25°C 8 TYP† Integral linearity error (each DAC) –1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5% 1.2 V TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, Rset = 523 Ω, Vref = 1.235 V (see Note 2) PARAMETER TIMING† REFERENCE LIMIT VERSION 135 MHz 125 MHz 110 MHz 80 MHz UNITS CE low to data bus enabled 5 MIN 10 10 10 10 ns CE low to data valid 6 MAX 75 75 75 100 ns CE high to data bus disabled 7 MAX 15 15 15 15 ns Analog output delay time (see Note 3) 18 TYP 20 20 20 20 ns Analog output rise or fall time (see Note 4) 19 TYP 2 2 2 3 ns Analog output setting time (see Note 5) 20 MAX 8 8 9 12 ns TYP 50 50 50 50 pV-s TYP 0 0 0 0 ns MAX 2 2 2 2 ns MIN 6 6 6 6 clock Glitch impulse (see Note 6) Analog output skew Pipeline delay MAX 10 10 10 10 cycles † See Figures 1 and 2. NOTES: 2. TTL input signals are 0 to 3 V with less than 3 ns rise/fall times between 10% and 90% levels. ECL input signals are VDD – 1.8 to VDD – 0.8 V with less than 2 ns rise/fall times between 20% and 80% levels. For input and output signals, timing reference points are at the 50% signal level. Analog output loads are less than 10 pF. D0 – D7 output loads are less than 40 pF. 3. Measured from 50% point of rising clock edge to 50% point of full-scale transition. 4. Measured between 10% and 90% of full-scale transition. 5. Measured from 50% point of full-scale transition to output settling within ± 1 LSB. Settling time does not include clock and data feedthrough. 6. Glitch impulse includes clock and data feedthrough. The – 3-dB test bandwidth is twice the clock rate. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 PARAMETER MEASUREMENT INFORMATION ÉÉÉ ÉÉÉ R/W, C0, C1 th1 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ tsu1 tw1 CE ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ tw2 ten2 tdis ten1 D0 – D7 (Read) D0 – D7 (Write) tsu2 ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉ th2 Figure 1. Read/Write Timing Waveform tc2 tw5 ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ tw6 LD P0 – P7 (A – B), OL0 – OL1 (A – B), SYNC, BLK Data tsu3 ÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ td th3 ts IOR, IOG, IOB tt tc1 tw3 CLK tw4 Figure 2. Video Input/Output Timing Waveform 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 PARAMETER MEASUREMENT INFORMATION RED, BLUE mA 19.05 V GREEN mA V White Level 0.714 26.67 1.000 92.5 IRE 1.44 0.054 Black Level 9.05 0.340 7.5 IRE 0.00 0.000 Blank Level 7.62 0.286 40 IRE 0.00 Sync Level 0.00 NOTE A: The IRE (Institute of Radio Engineers – now IEEE) scale is used for defining the relative voltage levels of the sync, white, black, and blank levels in a monitor circuit. The reference white level is set at 100 IRE units. The blanking level is set at φ IRE units. One IRE unit is equivalent to 1/100 of the difference between the reference white level and the blanking level. Figure 3. Composite Video Output Waveforms COMP C8 L1 VDD 5 V (VDD) C5–C7 C2–C4 R4 REF C10 TLC34058 C9 GND GND RSET R1 R2 R3 FS ADJ IOR IOG IOB LOCATION C1 Z1 To Video Connector DESCRIPTION VENDOR PART NUMBER C1 – C4, C8, C9 0.1-µF ceramic capacitor Erie RPE112Z5U104M50V C5 – C7 0.01-µF ceramic chip capacitor AVX 12102T903QA1018 C10 33-µF tantalum capacitor Mallory CSR13-K336KM L1 ferrite bead Fair-Rite 2743001111 R1, R2, R3 75-Ω 1% metal film resistor Dale CMF-55C R4 1000-Ω 1% metal film resistor Dale CMF-55C Rset 523-Ω 1% metal film resistor Dale CMF-55C Z1 1.2-V diode National Semiconductor LM385Z-1.2 NOTE A: The above listed vendor numbers are listed only as a guide. Substitution of devices with similar characteristics does not degrade the performance of the TLC34058. Figure 4. Circuit Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 PARAMETER MEASUREMENT INFORMATION 5V 220 Ω 5V CLK CLK 14 Monitor Products 970E 5V 330 Ω 220 Ω CLK CLK Clock Generator 330 Ω TLC34058 7 LDA LD 5V 0.1 µF Vref REF 1 kΩ Figure 5. Generating the Clock, Load, and Voltage Reference Signals VDD G0 – G7 ∼ 15 PF SYNC (IOG Only) BLK RL Figure 6. Equivalent Circuit of the Current Output (IOG) 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 C (stray + load) TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 PRINCIPLES OF OPERATION microprocessor unit (MPU) interface As shown in the functional block diagram, the MPU has direct access to the internal control registers and color overlay palettes via a standard MPU interface. Since the palette RAM and overlay registers have dual ports, they can be updated without affecting the display refresh process. One port is allocated for updating or reading data and the other for display. palette RAM write or read The palette RAM location is addressed by the internal 8-bit address register (ADDR0 – 7). The MPU can either write to or read from this register. The register eliminates the need for external address multiplexers. ADDR0– ADDR7 are updated via D0 – D7. To address the red, green, and blue part of a particular RAM location, the internal address register is provided with two additional bits, ADDRa and ADDRb. These address bits count modulo 3 and are reset to 0 when the MPU accesses the internal address register. After writing to or reading from the internal address register, the MPU executes three write or read cycles (red, green and blue). The register ADDRab is incremented after each of these cycles so that the red, green, and blue information is addressed from the correct part of the particular RAM location. During the blue write cycle, the red, green, and blue color information is adjoined to form a 24-bit word, which is then written to the particular RAM location. After the blue write/read cycle, the internal address register bits ADDR0 – 7 are incremented to access the next RAM location. For an entire palette RAM write or read, the bits ADDR0 – 7 are reset to 00 after accessing the FF (256) palette RAM location. Two additional control bits, C0 and C1, are used to differentiate the palette RAM read/write function from other operations that utilize the internal address register. C0 and C1 are respectively set high and low for writing to or reading from the palette RAM. Table 1 summarizes this differentiation, along with other internal address register operations. Note that C0 and C1 are each set low for writing to or reading from the internal address register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 PRINCIPLES OF OPERATION Table 1. Writing to or Reading from Palette RAM R/W C1 C0 ADDRb ADDRa L L L X X write ADDR0–7: D0 – D7 → ADDR0 – 7; 0 → ADDRa,b L L H L L write red color: D0 – D7 → RREG; increment ADDRa,b L L H L H write green color: D0 – D7 → GREG; increment ADDRa,b L L H H L write blue color: D0 – D7 → BREG; increment ADDRa,b; increment ADDR0 – 7; write palette RAM H L L X X read ADDR0 – 7: ADDR0 – 7 → D0 – D7; 0 → ADDRa,b H L H L L read red color: R0 – R7 → D0 – D7; increment ADDRa,b H L H L H read green color: G0 – G7 → D0 – D7; increment ADDRa,b H L H H L read blue color: B0 – B7 → D0 – D7; increment ADDRa b; increment ADDR0 – 7 ADDRa,b; FUNCTION X = irrelevant overlay register write/read With a few exceptions, the overlay register operation is identical to the palette RAM write/read operation (refer to the palette RAM write/read section). Upon writing to or reading from the internal address register, the additional address register ADDRab is automatically reset to 0. ADDRab counts modulo 3 as the red, green, and blue information is written to or read from a particular overlay register. The four overlay registers are addressed with internal address register values 00 – 03. After writing/reading blue information, the internal address register bits ADDR0 – 7 are incremented to the next overlay location. After accessing overlay register value 03, the internal address register does not reset to 00 but is advanced to 04. For writing to or reading from the internal address register, C0 and C1 are set low. When accessing the overlay registers, C0 and C1 are set high. Refer to Table 2 for quick reference. Table 2. Writing to or Reading from Overlay Registers R/W C1 C0 ADDRb ADDRa L L L X X write ADDR0 - 7: D0 – D7 → ADDR0–7; 0 → ADDRa,b L H H L L write red color: D0 – D7 → RREG; increment ADDRa,b L H H L H write green color: D0 – D7 → GREG; increment ADDRa,b L H H H L write blue color: D0 – D7 → BREG; increment ADDRa,b; increment ADDR0 – 7; write overlay register FUNCTION H L L X X read ADDR0 – 7: ADDR0 – 7 → D0 – D7; 0 → ADDRa,b H H H L L read red color: R0 – R7 → D0 – D7; increment ADDRa,b H H H L H read green color: G0 – G7 → D0 – D7; increment ADDRa,b H H H H L b; increment ADDR0 – 7 read blue color: B0 – B7 → D0 – D7; D7 increment ADDRa ADDRa,b X = irrelevant 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 PRINCIPLES OF OPERATION control register write/read The four control registers are addressed with internal address register values 04 – 07. Upon writing to or reading from the internal address register, the additional address bits ADDRab are automatically reset to 0. To facilitate read-modify-write operations, the internal address register does not increment after writing to or reading from the control registers. All control registers may be accessed at any time. When accessing the control registers, C0 and C1 are respective set low and high. Refer to Table 3 for quick reference. Table 3. Writing to or Reading from Control Registers R/W C1 C0 ADDRba ADDRab L L L X X write ADDR0 – 7: D0 – D7 → ADDR0 – 7; 0 → ADDRa,b L H L L L write control register: D0 – D7 → control register H L L X X read ADDR0 – 7: ADDR0 – 7 → D0 – D7; 0 → ADDRa,b H H L L L read control register: control register → D0 – D7 FUNCTION X = irrelevant summary of internal address register operations Table 4 provides a summary of operations that use the internal address register. Figure 1 presents the read/write timing for the device. If an invalid address is loaded into the internal address register, the device will ignore subsequent data from the MPU during a write operation and will send incorrect data to the MPU during a read operation. Table 4. Internal Address Register Operations INTERNAL ADDRESS REGISTER VALUE (ADDR0 – 7) (HEX) C1 C0 MPU ACCESS 00 – FF L H color palette RAM 00 – 03 H H over color 0 to 3 04 H L read mask register 05 H L blink mask register 06 H L command register 07 H L test register ADDRab (counts modulo 3) COLOR 00 red value 01 green value 11 blue value 00 red value 01 green value 110 blue value interruption of display refresh pixel data (via simultaneous pixel data retrieval and MPU write) If the MPU is writing to a particular palette RAM location or overlay register (during the blue cycle) and the display refresh process is accessing pixel data from the same RAM location or overlay register, one or more pixels on the display screen may be disturbed. If the MPU write data is valid during the complete chip enable period, a maximum of one pixel will be disturbed. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 PRINCIPLES OF OPERATION frame buffer interface and timing An internal latch and multiplexer enables the frame buffer to send the pixel data to the device at TTL rates. On the rising edges of LD, information for four or five consecutive pixels is latched into the device. This information includes the palette RAM address (up to 8 bits), the overlay register address (up to 2 bits), and the sync and blank information for each of the four or five consecutive pixels. The timing diagram for this pixel data input transfer is shown in Figure 2, along with the video output waveforms (IOR, IOG, and IOB). Note that with this architecture, the sync and blank timing can only be recognized with four- or five-pixel resolution. The display refresh process follows the first-in first-out format. Color data is output from the device in the same order in which palette RAM and overlay addresses are input. This process continues until all four or five pixels have been output, at which point the cycle will repeat. The overlay timing can be controlled by the pixel timing. However, this approach requires that the frame buffer emit additional bit planes to control the overlay selection on a pixel basis. Alternatively, the overlay timing can be controlled by external character or cursor generation timing (see the color selection section). No phase relationship between the LD and CLK signals is required (see Figure 2). Therefore, the LD signal can be derived by externally dividing the CLK signal by four or five. Any propagation delay in LD caused by the divider circuitry will not render the device nonfunctional. Regardless of the phase relationship between LD and CLK, the pixel, overlay, sync, and blank data are latched on the rising edge of LD. The device has an internal load signal (not brought out to a pin), which is synchronous to CLK and will follow LD by at least one and not more than four clock cycles. This internal load signal transfers the LD-latched data into a second set of latches, which are then internally multiplexed at the pixel clock or CLK signal frequency. For 4:1 or 5:1 multiplexing, a rising edge of LD should occur every four or five clock cycles. Otherwise, the internal load signal generation circuitry cannot lock onto or synchronize with LD. color selection The read mask, blink mask, and command registers process eight bits of color information (P0 – P7) and two bits of overlay information (OL0 – OL1) for each pixel every clock cycle. Control registers allow individual bit planes to be enabled/disabled for display and/or blinked at one of four blink rates and duty cycles (see the command register section, bits CR4 – CR5). By monitoring the BLK input to determine vertical retrace intervals, the device ensures that a color change due to blinking occurs only during the nonactive display time. Thus, a color change does not occur in the middle of the screen. A vertical retrace is sensed when BLK is low for at least 256 LD cycles. The color information is then selected from the palette RAM or overlay registers, in accordance with the processed input pixel data. Table 5 presents the effect of the processed input pixel data upon color selection. Note that P0 is the least significant bit (LSB) of the color palette RAM. When CR6 is high and both OL1 and OL0 are low, color information resides in the color palette RAM. When CR6 is low or either of the overlay inputs is high, the overlay registers provide the DAC inputs. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 PRINCIPLES OF OPERATION Table 5. Input Pixel Data versus Color Selection COMMAND REGISTER BIT OVERLAY SELECT INPUT COLOR ADDRESS (HEX) COLOR INFORMATION CR6 OL1 OL0 P7 – P0 H L L 00 color palette entry 00 H L L 01 color palette entry 01 • • • • • • • • • • • • • • • • • • • • • • • • H L L FF color palette entry FF L L L XX overlay register 0 X L H XX overlay register 1 X H L XX overlay register 2 X H H XX overlay register 3 X = irrelevant video generation The TLC34058 presents 8 bits of red, green, and blue information from either the palette RAM or overlay registers to the three 8-bit DACs during every clock cycle. The DAC outputs produce currents that correlate to their respective color input data. These output currents are translated to voltage levels that drive the color CRT monitor. The SYNC and BLK signals adjust the DAC analog output currents to generate specific output levels that are required in video applications. Table 6 shows the effect of SYNC and BLK upon the DAC output currents. Figure 3 presents the overall composite video output waveforms. Note that only the green output (IOG) contains sync information. The DAC architecture ensures monotonicity and reduced switching transients by using identical current sources and routing their outputs to the DAC current output or GND. Utilizing identical current sources eliminates the need for precision component ratios within the DAC ladder circuitry. An on-chip operational amplifier stabilizes the DAC full-scale output current over temperature and power supply variations. Table 6. Effects of Sync and Blank Upon DAC Output Currents (see Note 7) DESCRIPTION IOG (mA) IOR, IOB (mA) SYNC BLK DAC INPUTS WHITE 26.67 19.05 H H FF DATA data + 9.05 data + 1.44 H H data DATA w/o SYNC data + 1.44 data + 1.44 L H data BLACK 9.05 1.44 H H 00 BLACK w/o SYNC 1.44 1.44 L H 00 BLACK 7.62 0 H L xx SYNC 0 0 L L xx NOTE 7: The data in this table was measured with full-scale IOG current = 26.67 mA, Rset = 523 Ω, Vref = 1.235 V. command register The MPU can write to or read from the command register at any time. The command register is not initialized. CR0 corresponds to the D0 data bus line. Refer to Table 7 for quick reference. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 PRINCIPLES OF OPERATION Table 7. Command Register COMMAND REGISTER BIT COMMAND REGISTER BIT FUNCTION COMMAND REGISTER BIT DESCRIPTION CR7 Multiplex Select Bit low: selects 4:1 multiplexing g g selects 5:1 multiplexing g high: CR6 RAM Enable Bit low: use overlay register 0 high: use palette RAM CR5,, CR4 Blink Rate Select Bits 00: 16 on,, 48 off ((25/75)) 01: 16 on,, 16 off ((50/50)) 10: 32 on, 32 off ((50/50)) 11: 64 on, 64 off (50/50) OL1 Blink Enable Bit low: disable blinking high: enable blinking These two bits select the blink rate cycle y time and dutyy cycle. y The on and off numbers specifyy the blink rate cycle time as the number of vertical periods. y y ( ) percent. The numbers in parentheses specifyy the dutyy cycle in (on/off) CR2 OL0 Blink Enable Bit low: disable blinking high: enable blinking If this bit is high, g the OL0 [A – E] inputs will toggle gg between a logic g 0 and their input value at the selected blink rate before latching the incoming pixel data. Simultaneously, command register CR0 must be set high. If the CR2 bit is low, the OL0 [A – E] inputs will be unaffected. CR1 OL1 Displayy Enable Bit low: disable high: enable If this bit is low, the OL1 [A – E] inputs are forced to a logic g 0 before latching g the incoming g pixel data. If the CR1 bit is high, the OL1 [A – E] inputs will be affected. CR0 OL0 Displayy Enable Bit low: disable high: enable If this bit is low, the OL0 [A – E] inputs are forced to a logic g 0 before latching g the incoming g pixel data. If the CR0 bit is high, the OL0 [A – E] inputs will be affected. CR3 This bit selects either 4:1 or 5:1 multiplexing g for the palette RAM and overlay y register g address,, SYNC,, and BLK inputs. If 4:1 multiplexing the ‘E’ palette RAM g is selected,, the device ignores g y register g and overlay address inputs. These inputs should be connected to GND,, and the LD signal g frequency q y should be 1/4 of the clock frequency. q y If 5:1 is specified, all of the palette RAM and overlayy register address inputs are used and the LD signal should be 1/5 of the g g clock frequency. When the overlay y select bits, OL0 and OL1, are both low, this bit causes the DACs color information to be selected from overlay register 0 or the palette RAM. If this bit is a high, g the OL1 [A – E] inputs will toggle gg between a logic g 0 and their input value at the selected blink rate before latching the incoming pixel data. Simultaneously, command register CR1 must be set high. If the CR2 bit is low, the OL0 [A – E] inputs will be unaffected. read mask register The read mask register is used to enable (high) or disable (low) the eight bit planes (P0 – P7) within the palette RAM addresses. The enabling or disabling is accomplished by logic ANDing the read mask register with the palette RAM address before addressing the palette RAM. Note that read mask register bit 0 corresponds to data bus line D0. The MPU can write to or read from this register at any time. This register is not initialized. blink mask register The blink mask register is used to enable (high) or disable (low) the blinking of bit planes within the palette RAM addresses. For example, if blink mask register bit n is set high, the true Pn value will address the palette RAM during the on portion of the blink cycle. During the off part of the blink cycle, the Pn value will be replaced with a 0 before the palette RAM is addressed. The blink rate cycle time and duty cycle is specified by command register bits CR4 and CR5. If blink mask register bit n is set low, the true Pn value will always address the palette RAM. Note that blink mask register bit 0 corresponds to data bus line D0. This register is not initialized. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 PRINCIPLES OF OPERATION test register The test register allows the MPU to read the inputs to the DAC for diagnostic purposes. The MPU can write to or read from this register at any time. This register is not initialized. Only the four least significant bits can be written to, while all 8 bits can be read. Note that test register bit 0 corresponds to data bus line D0. A function description of this register is presented in Table 8. Table 8. Functional Description of Test Register TR3–TR0 D4–D7 0100 0010 4 MSBs of blue data input 4 MSBs of green data input FUNCTION 0001 4 MSBs of red data input 1100 4 LSBs of blue data input 1010 4 LSBs of green data input 1001 4 LSBs of red data input MPU read or write D0 – D3 MPU read D0 – D7 To read the DAC inputs, the MPU must first load the test register’s four least significant bits. One of the test register bits, b0 (red DAC), b1 (green DAC) or b2 (blue DAC), must be set high and the other two bits low. This process determines whether the inputs to the red, green, or blue DAC will be read. The test register bit b3 must be set high for reading the four most significant DAC inputs or low for reading the four least significant inputs. The MPU then reads the test register while the test register’s four least significant bits contain the previously written information. Note that either the device clock must be slowed down to the MPU cycle time or the same pixel and overlay data must be continuously presented to the device during the entire MPU read cycle. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 APPLICATION INFORMATION device ground plane Use of a four-layer PC board is recommended. All of the ground pins, voltage reference circuitry, power supply bypass circuitry, analog output signals, and digital signals, as well as any output amplifiers, should have a common ground plane. device analog power plane (APP) The device plus associated analog circuitry should have a separate analog power plane (APP) for VDD. The APP powers the device, voltage reference circuitry, and any output amplifiers. It should be connected to the overall PCB power plane (VDD) at a single point through a ferrite bead, which should be within 3 inches of the device. This connection is shown in Figure 4. PCB power plane and PCB ground plane The PCB power plane powers the digital circuitry. The PCB power plane and PCB ground planes should not overlay the APP unless the plane-to-plane noise is common-mode. supply decoupling Bypass capacitors should have the shortest possible lead lengths to reduce lead inductance. For best results, a parallel combination of 0.1-µF ceramic and 0.01-µF chip capacitors should be connected from each VDD pin to GND. If chip capacitors are not feasible, radial-lead ceramic capacitors may be substituted. These capacitors should be located as close to the device as possible. The performance of the internal power supply noise rejection circuitry decreases with noise frequency. If a switching power supply is used for VDD, close attention must be paid to reducing power supply noise. To reduce such noise, the APP could be powered with a three-terminal voltage regulator. digital interconnect The digital inputs should be isolated from the analog outputs and other analog circuitry as much as possible. Shielding the digital inputs will reduce noise on the power and ground lines. The lengths of clock and data lines should be minimized to prevent high-frequency clock and data information from inducing noise into the analog part of the video system. Active termination resistors for the digital inputs should be connected to the PCB power plane, not the APP. These digital inputs should not overlay the device ground plane. analog signal interconnect Minimizing the lead lengths between groups of VDD and GND minimizes inductive ringing. To minimize noise pickup due to reflections and impedance mismatch, the device should be located as close to the output connectors as possible. The external voltage reference should also be as close to the device as possible, to minimize noise pickup. To maximize high-frequency supply voltage rejection, the video output signals should overlay the device ground plane and not the APP. Each analog output should have a 75-Ω load resistor connected to GND for maximum performance. To minimize reflections, the resistor connections between current output and ground should be as close to the device as possible. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC34058 256 × 24 COLOR PALETTE SLAS050 – D3961, NOVEMBER 1991 APPLICATION INFORMATION clock interfacing To facilitate the generation of high-frequency clock signals, the CLK and CLK pins are designed to accept differential signals that can be generated with 5-V (single supply) ECL logic. Due to noise margins of the CMOS process, the CLK and CLK inputs must be differential signals. Connecting a single-ended clock signal to CLK and connecting CLK to GND will not work. The CLK and CLK pins require termination resistors (220-Ω to VDD and 330-Ω to GND) that should be as close to the device as possible. LD is typically generated by dividing the clock frequency by four (4:1 multiplexing) or five (5:1 multiplexing) and translating the resulting signal to TTL levels. Since no phase relationship between the LD and CLK signals is required, any propagation delay in LD caused by the divider circuitry will not affect device performance. The pixel, overlay, sync and blank data are latched on the rising edge of LD. LD may also be used as the shift clock for the video DRAMs. In short, LD provides the fundamental timing for the video system. The Bt438 Clock Generator (from Brooktree) is recommended for generating the CLK, CLK, LD, and REF signals. It supports both 4:1 and 5:1 multiplexing. Alternatively, the Bt438 can interface the device to a TTL clock. Figure 5 illustrates the interconnection between the Bt438 and the device. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 5962-8992801XA OBSOLETE CPGA GA 84 TBD Call TI Call TI 5962-8992801XC OBSOLETE CPGA GA 84 TBD Call TI Call TI TLC34058-110FN OBSOLETE PLCC FN 84 TBD Call TI Call TI TLC34058-110FNR OBSOLETE PLCC FN 84 TBD Call TI Call TI TLC34058-110MGA OBSOLETE CPGA GA 84 TBD Call TI Call TI TLC34058-110MGAB OBSOLETE CPGA GA 84 TBD Call TI Call TI TLC34058-110MHFG OBSOLETE CFP HFG 84 TBD Call TI Call TI TLC34058-135FN OBSOLETE PLCC FN 84 TBD Call TI Call TI TLC34058-80FN OBSOLETE PLCC FN 84 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56) 44 0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10) 52 0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37) 68 0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91) 84 1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45) 4040005 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. 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