TI SN74GTL1655DGGRE4

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SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
FEATURES
•
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•
•
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Member of the Texas Instruments Widebus™
Family
UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, or Clocked Modes
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Translates Between GTL/GTL+ Signal Level
and LVTTL Logic Levels
High-Drive (100 mA), Low-Output-Impedance
(12 Ω) Bus Transceiver (B Port)
Edge-Rate-Control Input Configures the
B-Port Output Rise and Fall Times
Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors on A
Port
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
DESCRIPTION/ORDERING INFORMATION
The SN74GTL1655 is a high-drive (100 mA),
low-output-impedance
(12 Ω)
16-bit
UBT™
transceiver that provides LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL signal-level translation. This
device is partitioned as two 8-bit transceivers and
combines D-type flip-flops and D-type latches to allow
for transparent, latched, and clocked modes of data
transfer similar to the '16501 function. This device
provides an interface between cards operating at
LVTTL logic levels and a backplane operating at
GTL/GTL+ signal levels. Higher-speed operation is a
direct result of the reduced output swing (<1 V),
reduced input threshold levels, and OEC™ circuitry.
The
high
drive
is
suitable
for
driving
double-terminated low-impedance backplanes using
incident-wave switching.
SCBS696I – JULY 1997 – REVISED APRIL 2005
DGG PACKAGE
(TOP VIEW)
1OEAB
1OEBA
VCC
1A1
GND
1A2
1A3
GND
1A4
GND
1A5
GND
1A6
1A7
VCC
1A8
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
GND
2A7
VCC
2A8
GND
2OEAB
2OEBA
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
CLK
1LEAB
1LEBA
VERC
GND
1B1
1B2
GND
1B3
1B4
1B5
GND
1B6
1B7
VCC
1B8
2B1
GND
2B2
2B3
GND
2B4
2B5
VREF
2B6
GND
2B7
2B8
BIAS VCC
2LEAB
2LEBA
OE
The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred
higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels, but are not 5-V
tolerant. VREF is the reference input voltage for the B port.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2005, Texas Instruments Incorporated
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
www.ti.com
SCBS696I – JULY 1997 – REVISED APRIL 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is partitioned uniquely as two 8-bit transceivers with individual latch timing and output signals, but
with a common clock and output enable inputs for both transceiver words.
Data flow for each word is determined by the respective latch enables (LEAB and LEBA), output enables (OEAB
and OEBA), and clock (CLK). The output enables (1OEAB, 1OEBA, 2OEAB, and 2OEBA) control byte 1 and
byte 2 data for the A-to-B and B-to-A directions, respectively.
For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB transitions
low, the A data is latched independent of CLK high or low. If LEAB is low, the A data is registered on the CLK
low-to-high transition. When OEAB is low, the outputs are active. With OEAB high, the outputs are in the
high-impedance state.
Data flow for the B-to-A direction is identical, but uses OEBA, LEBA, and CLK. Note that CLK is common to both
directions and both 8-bit words. OE also is common and is used to disable all I/O ports simultaneously.
The SN74GTL1655 has adjustable edge-rate control (VERC). Changing VERC input voltage between GND and VCC
adjusts the B-port output rise and fall times. This allows the designer to optimize for various loading conditions.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
2
TSSOP – DGG
Tape and reel
ORDERABLE PART NUMBER
SN74GTL1655DGGR
TOP-SIDE MARKING
GTL1655
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
www.ti.com
SCBS696I – JULY 1997 – REVISED APRIL 2005
FUNCTION TABLES
ABC
FUNCTION (1)
INPUTS
OEAB
LEAB
CLK
A
OUTPUT
B
MODE
H
X
X
X
Z
Isolation
L
H
X
L
L
Transparent
L
H
X
H
H
Transparent
L
L
↑
L
L
Registered
L
L
↑
H
H
Registered
(1)
(2)
(3)
(2)
Previous state
Previous state
L
L
H
X
B0
L
L
L
X
B0 (3)
A-to-B data flow is shown. B-to-A flow is similar, but uses OEBA,
LEBA, and CLK.
Output level before the indicated steady-state input conditions were
established, provided that CLK was high before LEAB went low
Output level before the indicated steady-state input conditions were
established
OUTPUT ENABLE
INPUTS
OUTPUTS
OE
OEAB
OEBA
A PORT
B PORT
L
L
L
Active
Active
L
L
H
Z
Active
L
H
L
Active
Z
L
H
H
Z
Z
H
X
X
Z
Z
B-PORT EDGE-RATE CONTROL (VERC)
input VERC
LOGIC
LEVEL
NOMINAL
VOLTAGE
OUTPUT
B-PORT
EDGE RATE
H
VCC
Slow
L
GND
Fast
3
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
www.ti.com
SCBS696I – JULY 1997 – REVISED APRIL 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
41
VREF
61
VERC
64
CLK
63
1LEAB
62
1LEBA
1OEBA
2
1
1OEAB
33
OE
1A1
4
1D
C1
CLK
1D
C1
CLK
To Seven Other Channels
4
59
1B1
www.ti.com
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
SCBS696I – JULY 1997 – REVISED APRIL 2005
LOGIC DIAGRAM (POSITIVE LOGIC) (CONTINUED)
41
VREF
61
VERC
64
CLK
35
2LEAB
34
2LEBA
2OEBA
32
31
2OEAB
33
OE
2A1
17
1D
C1
48
2B1
CLK
1D
C1
CLK
To Seven Other Channels
5
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
www.ti.com
SCBS696I – JULY 1997 – REVISED APRIL 2005
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX
VCC
Supply voltage range
BIAS VCC
VI
Input voltage range (2)
VO
Voltage range applied to any output in the high or power-off state (2)
IO
Current into any output in the low state
IO
Current into any A-port output in the high state (3)
–0.5
4.6
A-port and control inputs
–0.5
4.6
B port, VERC, and VREF
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
48
B port
200
Continuous current through each VCC or GND
UNIT
V
V
V
mA
48
mA
±100
mA
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
55
°C/W
150
°C
θJA
Package thermal
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
impedance (4)
–65
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The current flows only when the output is in the high state and VO > VCC.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1) (2) (3) (4)
BIAS VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
MIN
NOM
MAX
3
3.3
3.6
GTL
1.14
1.2
1.26
GTL+
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTL+
0.87
1
1.1
B port
0
VTT
Except B port
0
VCC
B port
VIH
High-level input voltage
VERC
Except B port and ERC
Low-level input voltage
VCC – 0.6
Input clamp current
IOH
High-level output current
VERC
VCC
GND
0.6
V
mA
A port
–24
mA
A port
24
B port
100
Power-up ramp rate
200
TA
Operating free-air temperature
–40
6
V
–18
∆t/∆VCC
(3)
(4)
V
0.8
Low-level output current
(2)
V
VREF – 50 mV
IOL
(1)
V
2
Except B port and ERC
IIK
V
VREF + 50 mV
B port
VIL
UNIT
mA
µs/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Normal connection sequence is GND first, BIAS VCC = 3.3 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last.
However, if the B-port I/O precharge is not required, the acceptable connection sequence is GND first and
VCC = 3.3 V, BIAS VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. When VCC is connected, the BIAS VCC circuitry is
disabled.
VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT.
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
www.ti.com
SCBS696I – JULY 1997 – REVISED APRIL 2005
Electrical Characteristics
over recommended operating free-air temperature range, VREF = 1 V and VTT = 1.5 V (unless otherwise noted)
PARAMETER
VIK
VOH
A port
VCC = 3 V,
II = –18 mA
VCC = 3 V to 3.6 V,
IOH = –100 µA
VCC – 0.2
IOH = –12 mA
2.4
IOH = –24 mA
2.2
VCC = 3 V
A port
VCC = 3 V
VOL
B port
VCC = 3 V
Control inputs
VCC = 3.6 V
B port
Ioff
VCC = 0,
II(hold)
VCC = 3.6
V
IOL = 12 mA
0.4
IOL = 24 mA
0.55
IOL = 40 mA
0.2
IOL = 80 mA
0.4
IOL = 100 mA
0.5
VI = VCC or GND
±10
VI = VTT or GND
±10
±100
VI = 0.8 V
VI = 2 V
V (2),
UNIT
–1.2
0.2
VI or VO = 0 to 3.6 V
VCC = 3 V
A port
MAX
V
IOL = 100 µA
VCC = 3 V to 3.6 V,
II
MIN TYP (1)
TEST CONDITIONS
V
µA
µA
75
µA
–75
VI = 0 to VCC
±500
IOZH
B port
VCC = 3.6 V,
VO = 1.5 V
10
µA
IOZL
B port
VCC = 3.6 V,
VO = 0.4 V
–10
µA
(3)
A port
VCC = 3.6 V,
VO = VCC or GND
±10
µA
IOZPU
A port
VCC = 0 to 3.6 V, VO = 0.5 V to 3 V, OE = low
±50
µA
IOZPD
A port
VCC = 3.6 V to 0, VO = 0.5 V to 3 V, OE = low
±50
µA
IOZ
ICC
VCC = 3.6 V, IO = 0,
VI = VCC or GND
A or B port
Outputs high
80
Outputs low
80
Outputs disabled
80
∆ICC (4)
Except B port
VCC = 3.6 V, A-port or control inputs at VCC or GND,
One input at VCC – 0.6 V
Ci
Control inputs
VI = VCC or 0
Cio
(1)
(2)
(3)
(4)
A port
VO = VCC or 0
B port
mA
1
mA
3
5
pF
5
6
6
8
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Live-Insertion Specifications
over recommended operating free-air temperature range
PARAMETER
ICC (BIAS VCC)
VO
IO
B port
B port
TEST CONDITIONS
VCC = 0 to 3 V
VCC = 3 V to 3.6 V
VO (B port) = 0 to 1.2 V,
MIN
VI (BIAS VCC) = 3 V to 3.6 V
1
MAX
mA
10
µA
1.2
V
µA
VCC = 0,
VI (BIAS VCC) = 3.3 V
VCC = 0,
VO (B port) = 0.4 V,
VCC = 0 to 3.6 V,
OE = 3.3 V
100
VCC = 0 to 1.5 V,
OE = 0 to 3.3 V
100
VI (BIAS VCC) = 3 V to 3.6 V
UNIT
5
–1
7
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
www.ti.com
SCBS696I – JULY 1997 – REVISED APRIL 2005
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.2 V, VREF = 0.8 V, and VERC = VCC or GND for GTL (unless otherwise noted)
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time
LE high
3
CLK high or low
3
Data before CLK↑
th
Data before LE↓
Data after LE↓
UNIT
160
MHz
ns
2.7
CLK high
2.8
CLK low
2.6
Data after CLK↑
Hold time
MAX
ns
0.4
CLK high or low
ns
0.9
A-to-B Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.2 V, VREF = 0.8 V, and VERC = VCC or GND for GTL (see Figure 1)
PARAMETER
MAX
3.1
5.2
2.6
6.2
3.4
5.5
2.4
5.8
3.5
5.8
2.6
6.4
3.3
5.4
2.7
5.9
2.3
4.3
1.9
4.3
2.7
4.8
1.8
4.3
2.8
4.9
2
4.8
2.5
4.5
2
4.2
tPLH
tPHL
ten
tdis
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
8
TYP
160
tPHL
(1)
(2)
MIN
fmax
tPLH
tf
TO
(OUTPUT)
tPLH
tPHL
tr
FROM
(INPUT)
VERC = GND
VERC = VCC
VERC = GND
VERC = VCC
A
VERC = VCC
B
CLK
VERC = VCC
B
LEAB
VERC = VCC
B
OEAB or OE
VERC = VCC
B
A
VERC = GND
B
CLK
VERC = GND
B
LEAB
VERC = GND
B
OEAB or OE
VERC = GND
B
Transition time, B outputs (0.6 V to 1 V)
Transition time, B outputs (1 V to 0.6 V)
UNIT
MHz
0.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.2
1.1
ns
1.7
tsk(o) (1)
Skew between drivers in the same package
switching in the same direction
1
ns
tsk(o) (2)
Skew between drivers
switching in any direction in the same package
1
ns
Skew values are applicable for through mode only.
Skew values are applicable for CLK mode only, with all outputs switching simultaneously.
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
www.ti.com
SCBS696I – JULY 1997 – REVISED APRIL 2005
B-to-A Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.2 V and VREF = 0.8 V for GTL (see Figure 1)
PARAMETER
TO
(OUTPUT)
MIN
MAX
fmax
160
tPLH
1.8
4.7
2.3
4.6
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
(1)
(2)
FROM
(INPUT)
B
A
CLK
A
LEBA
A
OEBA or OE
A
UNIT
MHz
1.6
4
1.5
3.4
1.7
4
1.4
3.5
1.2
4.2
1.2
6.1
ns
ns
ns
ns
tsk(o) (1)
Skew between drivers in the same package
switching in the same direction
1
ns
tsk(o) (2)
Skew between drivers
switching in any direction in the same package
1
ns
Skew values are applicable for through mode only.
Skew values are applicable for CLK mode only, with all outputs switching simultaneously.
9
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
www.ti.com
SCBS696I – JULY 1997 – REVISED APRIL 2005
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V, VREF = 1 V, and VERC = VCC or GND for GTL+ (unless otherwise noted)
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time
LE high
3
CLK high or low
3
Data before CLK↑
th
Data before LE↓
Data after LE↓
UNIT
160
MHz
ns
2.7
CLK high
2.8
CLK low
2.6
Data after CLK↑
Hold time
MAX
ns
0.4
CLK high or low
ns
0.9
A-to-B Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V, VREF = 1 V, and VERC = VCC or GND for GTL+ (see Figure 1)
PARAMETER
MAX
3
5.1
2.9
6.5
3.4
5.4
2.7
6.2
3.5
5.7
2.8
6.7
3.3
5.4
3
6.3
tPLH
tPHL
ten
tdis
ten
tdis
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
ten
tdis
10
TYP
160
tPHL
(1)
(2)
MIN
fmax
tPLH
tf
TO
(OUTPUT)
tPLH
tPHL
tr
FROM
(INPUT)
VERC = GND
VERC = VCC
VERC = GND
VERC = VCC
A
VERC = VCC
B
CLK
VERC = VCC
B
LEAB
VERC = VCC
B
OEAB
VERC = VCC
B
OE
VERC = VCC
B
A
VERC = GND
B
CLK
VERC = GND
B
LEAB
VERC = GND
B
OEAB
VERC = GND
B
OE
VERC = GND
B
Transition time, B outputs (0.6 V to 1.3 V)
Transition time, B outputs (1.3 V to 0.6 V)
UNIT
MHz
3
5.5
3.6
5.8
2.3
4.3
2
4.4
2.7
4.8
1.9
4.5
2.8
4.9
2.1
4.9
2.5
4.5
2.1
4.4
2.5
4.6
2.9
4.9
0.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.7
1.6
ns
2.4
tsk(o) (1)
Skew between drivers in the same package
switching in the same direction
1
ns
tsk(o) (2)
Skew between drivers
switching in any direction in the same package
1
ns
Skew values are applicable for through mode only.
Skew values are applicable for CLK mode only, with all outputs switching simultaneously.
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
www.ti.com
SCBS696I – JULY 1997 – REVISED APRIL 2005
B-to-A Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1)
PARAMETER
TO
(OUTPUT)
MIN
MAX
fmax
160
tPLH
2
4.8
2.4
4.7
1.6
4.4
1.5
3.4
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
ten
tdis
(1)
(2)
FROM
(INPUT)
B
A
CLK
A
LEBA
A
OEBA
A
OE
A
UNIT
MHz
1.7
4
1.4
3.5
1.2
4.2
1.2
6.1
1.2
4.7
1.2
6.3
ns
ns
ns
ns
ns
tsk(o) (1)
Skew between drivers in the same package
switching in the same direction
1
ns
tsk(o) (2)
Skew between drivers
switching in any direction in the same package
1
ns
Skew values are applicable for through mode only.
Skew values are applicable for CLK mode only, with all outputs switching simultaneously.
11
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
www.ti.com
SCBS696I – JULY 1997 – REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VTT
6V
500 Ω
From Output
Under Test
S1
Open
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 50 pF
(see Note A)
500 Ω
12.5 Ω
From Output
Under Test
CL = 30 pF
(see Note A)
S1
Open
6V
GND
LOAD CIRCUIT FOR B OUTPUTS
LOAD CIRCUIT FOR A OUTPUTS
tw
3V
3V
Timing
Input
1.5 V
0V
1.5 V
1.5 V
Input
tsu
0V
VOLTAGE WAVEFORMS
PULSE DURATION
3V
Input
Test
Point
1.5 V
1.5 V
th
3V
Data Input
A Port
1.5 V
Data Input
B Port
VREF
1.5 V
0V
VTT
VREF
0V
0V
tPLH
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
tPHL
VTT
Output
VREF
VREF
3V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(CLK to B port)
1.5 V
tPZL
1.5 V
0V
tPLH
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(CLK to A port)
1.5 V
tPLZ
3V
1.5 V
tPZH
tPHL
VOH
Output
1.5 V
0V
3V
Input
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VOH
1.5 V
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
Figure 1. Load Circuits and Voltage Waveforms
12
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
SN74GTL1655DGGR
ACTIVE
TSSOP
DGG
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74GTL1655DGGRE4
ACTIVE
TSSOP
DGG
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74GTL1655DGGRG4
ACTIVE
TSSOP
DGG
64
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74GTL1655DGGR
Package Package Pins
Type Drawing
TSSOP
DGG
64
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
8.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
17.3
1.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74GTL1655DGGR
TSSOP
DGG
64
2000
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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