TI SN74GTL2003PWR

SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
8-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
Check for Samples: SN74GTL2003
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
QFN PACKAGE
(TOP VIEW)
terminal 1
index area
1 GND
•
•
PW PACKAGE
(TOP VIEW)
20 GREF
•
•
Bidirectional or Unidirectional Applications
Requiring Voltage-Level Translation From Any
Voltage (1 V to 5 V) to Any Voltage (1 V to 5 V)
Low Voltage Processor I2C Port Translation to
3.3-V and/or 5-V I2C Bus Signal Levels
GTL/GTL+ Translation to LVTTL/TTL Signal
Levels
GND 1
20 GREF
SREF 2
19 DREF
19 DREF
S1 3
18 D1
S1 3
18 D1
S2 4
17 D2
S2 4
17 D2
S3 5
16 D3
S3 5
16 D3
S4 6
15 D4
S5 7
S4 6
14 D5
15 D4
S6 8
13 D6
SREF 2
S5 7
14 D5
S6 8
13 D6
S7 9
12 D7
S7 9
12 D7
S8 10
11 D8
D8 11
•
Provides Bidirectional Voltage Translation
With No Direction Control Required
Allows Voltage Level Translation From 1 V up
to 5 V
Provides Direct Interface With GTL, GTL+,
LVTTL/TTL, and 5-V CMOS Levels
Low On-State Resistance Between Input and
Output Pins (Sn/Dn)
Supports Hot Insertion
No Power Supply Required – Will Not Latch Up
5-V-Tolerant Inputs
Low Standby Current
Flow-Through Pinout for Ease of Printed
Circuit Board Trace Routing
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
S8 10
1
DESCRIPTION/ORDERING INFORMATION
The SN74GTL2003 provides eight NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a
reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made
with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage
translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).
When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between
the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on
the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port
is pulled to VCC by the pullup resistors.
All transistors in the SN74GTL2003 have the same electrical characteristics, and there is minimal deviation from
one output to another in voltage or propagation delay. This offers superior matching over discrete transistor
voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being
identical, the reference transistor (SREF/DREF) can be located on any of the other eight matched Sn/Dn
transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides
excellent ESD protection.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
© 2011, Texas Instruments Incorporated
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
ORDERING INFORMATION
VQFN – RKS
–40°C to 85°C
(1)
ORDERABLE PART
NUMBER
PACKAGE (1)
TA
TSSOP – PW
TOP-SIDE MARKING
Tape and reel
SN74GTL2003RKSR
GK2003
Tube
SN74GTL2003PW
GK2003
Tape and reel
SN74GTL2003PWR
GK2003
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DESCRIPTION
Table 1.
PIN DESCRIPTION
2
PIN NO.
NAME
DESCRIPTION
1
GND
Ground (0 V)
2
SREF
Source of reference
transistor
3 – 10
Sn
Ports S1–S8
11 – 18
Dn
Ports D1–D8
19
DREF
Drain of reference
transistor
20
GREF
Gate of reference
transistor
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
FUNCTION TABLES
Table 2. HIGH-to-LOW Translation
(Assuming Dn is at the Higher Voltage Level) (1)
(1)
(2)
(3)
(4)
(5)
GREF (2)
DREF
H
H
0V
H
H
VTT (3)
H
H
VTT
L
L
0 – VTT
INPUTS
D8–D1
SREF
OUTPUT
S8–S1
TRANSISTOR
X
X
Off
H
VTT (4)
On
L
L (5)
On
X
X
Off
H = HIGH voltage level, L = LOW voltage level, X = don't care.
GREF should be at least 1.5 V higher than SREF for best translator operation.
VTT is equal to the SREF voltage.
Sn is not pulled up or pulled down.
Sn follows the Dn input LOW.
Table 3. LOW-to-HIGH Translation
(Assuming Dn is at the Higher Voltage Level) (1)
(1)
(2)
(3)
(4)
(5)
GREF (2)
DREF
SREF
INPUTS
D8–D1
OUTPUT
S8–S1
TRANSISTOR
H
H
0V
X
X
Off
VTT
(3)
VTT
H
(4)
H
H
H
H
VTT
L
L (5)
Nearly Off
On
L
L
0 – VTT
X
X
Off
H = HIGH voltage level, L = LOW voltage level, X = don't care.
GREF should be at least 1.5 V higher than SREF for best translator operation.
VTT is equal to the SREF voltage.
Dn is pulled up to VCC through an external resistor.
Dn follows the Sn input LOW.
CLAMP SCHEMATIC
DREF
SREF
GREF
D1
D8
S1
S8
SA00647
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
3
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
Absolute Maximum Ratings (1) (2) (3)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VSREF
DC source reference voltage
–0.5
7
V
VDREF
DC drain reference voltage
–0.5
7
V
VGREF
DC gate reference voltage
–0.5
7
V
VSn
DC voltage port Sn
–0.5
7
V
VDn
DC voltage port Dn
IREFK
DC diode current on reference pins
VI < 0 V
–50
mA
ISK
DC diode current port Sn
VI < 0V
–50
mA
IDK
DC diode current port Dn
VI < 0 V
–50
mA
IMAX
DC clamp current per channel
Channel is ON state
θJA
Package thermal impedance
Tstg
Storage temperature range
(1)
(2)
(3)
–0.5
7
±128
–65
V
mA
88
ºC/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Recommended Operating Conditions (1)
VI/O
Input/output voltage (Sn, Dn)
(1)
MIN
MAX
0
5.5
UNIT
V
VSREF
DC source reference voltage
0
5.5
V
VDREF
DC drain reference voltage
0
5.5
V
VGREF
DC gate reference voltage
0
5.5
V
IPASS
Pass transistor current
64
mA
TAMB
Operating ambient temperature range (in free air)
85
ºC
(1)
4
–40
VSREF = VDREF – 1.5 V for best results in level-shifting applications.
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN TYP (1)
MAX
UNIT
260
350
mV
VOL
Low-level output voltage
VDD = 3 V, VSREF = 1.365 V, VSn or VDn = 0.175 V,
Iclamp = 15.2 mA
VIK
Input clamp voltage
II = –18 mA
VGREF = 0 V
–1.2
V
IIH
Gate input leakage
VI = 5 V
VGREF = 0 V
5
µA
CI(GREF)
Gate capacitance
VI = 3 V or 0 V
56
pF
CIO(OFF)
OFF capacitance
VO = 3 V or 0 V
VGREF = 0 V
7.4
pF
CIO(ON)
ON capacitance
VO = 3 V or 0 V
VGREF = 3 V
18.6
pF
VI = 0 V
ron (2)
3.5
5
VGREF = 3 V
4.4
7
VGREF = 2.3 V
IO = 64 mA
5.5
9
67
105
IO = 30 mA
9
15
7
10
IO = 15 mA
58
80
50
70
VGREF = 1.5 V
ON-state resistance
VGREF = 1.5 V,
VI = 2.4 V
VI = 1.7 V
(1)
(2)
VGREF = 4.5 V
VGREF = 4.5 V
VGREF = 3 V
VGREF = 2.3 V
Ω
All typical values are measured at Tamb = 25°C.
Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (Sn or Dn) terminals. Submit Documentation Feedback 5
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
5
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
AC Characteristics for Translator-Type Applications (1)
VREF = 1.365 V to 1.635 V, VDD1 = 3 V to 3.6 V, VDD2 = 2.36 V to 2.64 V, GND = 0 V, tr = tf ≤ 3 ns, Tamb = –40°C to 85°C
(see Figure 5)
PARAMETER
tPLH
(1)
(2)
(3)
(3)
Propagation delay (Sn to Dn, Dn to Sn)
MIN
TYP (2)
MAX
0.5
1.5
5.5
UNIT
ns
CON(max) of 30 pF and a COFF(max) of 15 pF is specified by design.
All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.5 V, VREF = 1.5 V and Tamb = 25°C.
Propagation delay specified by characterization.
AC Waveforms
Vm = 1.5 V, VIN = GND to 3 V
VI
Input
VM
VM
tPHL0
tPLH0
GND
VDD2
VM
Low-to-High
VOL
VM
tPHL
tPLH
tPHL1
VDD2
tPLH1
VM
Low-to-High
VOL
VM
Figure 1. Input (Sn) to Output (Dn) Propagation Delays
VDD2
VDD2
200
150
VDD2
VDD2
150
150
DUT
DREF GREF
D1 . . . D8
SREF
S1 . . . S8
Test
Jig
VREF
Pulse
Generator
Figure 2. Load Circuit
6
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
AC Characteristics for Translator-Type Applications
GND = 0 V, tR, CL = 50 pF, GREF = 5 V ± 0.5 V, Tamb = –40°C to 85°C
PARAMETER
tpd
(1)
Propagation delay
MIN
(1)
MAX
UNIT
250
ps
This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC Waveforms
3V
Input
1.5 V
1.5 V
tPLH
tPHL
0V
VOH
1.5 V
Output
1.5 V
VOL
Figure 3. Input (Sn) to Output (Dn) Propagation Delays
From Ouput
Under Test
CL = 50 pF
500
S1
7V
500
Figure 4. Load Circuit
Test
S1
tpd
Open
tPLZ/tPZL
7V
TPHZ/TPZH
Open
CL = Load Capacitance, includes jig and probe capacitance (See AC Characteristics for value)
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
7
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
APPLICATION INFORMATION
Bidirectional Translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the GREF input must be connected to DREF and both pins pulled to HIGH-side VCC through a pullup resistor
(typically 200 kW). A filter capacitor on DREF is recommended. The processor output can be totem pole or open
drain (pullup resistors) and the chipset output can be totem pole or open drain (pullup resistors are required to
pull the Dn outputs to VCC). However, if either output is totem pole, data must be unidirectional or the outputs
must be 3-statable, and the outputs must be controlled by some direction-control mechanism to prevent
HIGH-to-LOW contentions in either direction. If both outputs are open drain, no direction control is needed. The
opposite side of the reference transistor (SREF) is connected to the processor core power-supply voltage. When
DREF is connected through a 200-kW resistor to a 3.3-V to 5.5-V VCC supply and SREF is set between 1 V to VCC
1.5 V, the output of each Sn has a maximum output voltage equal to SREF, and the output of each Dn has a
maximum output voltage equal to VCC.
8
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
VDPU = 5 V
200K Ω
VREF = 1.8V
GTL2003
GREF
RPU
RPU
RPU
DREF
SREF
RPU
S1
D1
SW
CPU I/O
Chipset
I/O
S2
D2
SW
VDPU = 3.3V
RPU
S7
RPU
D7
Chipset
I/O
S8
D8
GND
Figure 5. Bidirectional Translation to Multiple Higher Voltage Levels (Such as an I2C or SMBus
Applications)
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
9
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
Unidirectional Down Translation
For unidirectional clamping (higher voltage to lower voltage), the GREF input must be connected to DREF and both
pins pulled to the higher-side VCC through a pullup resistor (typically 200 kW). A filter capacitor on DREF is
recommended. Pullup resistors are required if the chipset I/Os are open drain. The opposite side of the reference
transistor (SREF) is connected to the processor core power-supply voltage. When DREF is connected through a
200-kW resistor to a 3.3-V to 5.5-V VCC supply and SREF is set between 1 V to VCC – 1.5 V, the output of each Sn
has a maximum output voltage equal to SREF.
VDPU = 5 V
200K Ω
GTL2003
VREF = 1.8V
DREF
SREF
S1
GREF
SW
D1
CPU I/O
S2
D2
Chipset
I/O
SW
Sn
Dn
GND
Figure 6. Unidirectional Down Translation to Protect Low-Voltage Processor Pins
10
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
Unidirectional Up Translation
For unidirectional up translation (lower voltage to higher voltage), the reference transistor is connected the same
as for a down translation. A pullup resistor is required on the higher voltage side (Dn or Sn) to get the full HIGH
level, since the GTL device only passes the reference source (SREF) voltage as a HIGH when doing an up
translation. The driver on the lower voltage side only needs pullup resistors if it is open drain.
VDPU = 5 V
200K Ω
GTL2003
VREF = 1.8V
GREF
RPU
RPU
RPU
DREF
SREF
RPU
S1
SW
D1
CPU I/O
Chipset
I/O
S2
SW
Sn
D2
Dn
GND
Figure 7. Unidirectional Up Translation to Higher-Voltage Chipsets
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
11
SN74GTL2003
SCDS305 – FEBRUARY 2011
www.ti.com
Sizing Pullup Resistors
The pullup resistor value should limit the current through the pass transistor when it is in the on state to about 15
mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than
15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at 15 mA,
the pullup resistor value is calculated as:
Pullup voltage (V ) - 0.35 V
Resistor value (W ) =
0.015 A
(1)
Table 4 shows resistor values for various reference voltages and currents at 15 mA, 10 mA, and 3 mA. The
resistor value shown in the +10% column, or a larger value, should be used to ensure that the pass voltage of
the transistor would be 350 mV or less. The external driver must be able to sink the total current from the
resistors on both sides of the GTL device at 0.175 V, although the 15 mA only applies to current flowing through
the SN74GTL2003.
Table 4. Pullup Resistor Values (1) (2) (3)
PULLUP RESISTOR VALUE (Ω)
VOLTAGE
(1)
(2)
(3)
12
15 mA
10 mA
3 mA
NOMINAL
+10%
NOMINAL
+10%
NOMINAL
+10%
5.0 V
310
341
465
512
1550
1705
3.3 V
197
217
295
325
983
1082
2.5 V
143
158
215
237
717
788
1.8 V
97
106
145
160
483
532
1.5 V
77
85
115
127
383
422
1.2 V
57
63
85
94
283
312
Calculated for VOL = 0.35 V
Assumes output driver VOL = 0.175 V at stated current
+10% to compensate for VDD range and resistor tolerance
Submit Documentation Feedback
© 2011, Texas Instruments Incorporated
Product Folder Link(s): SN74GTL2003
PACKAGE OPTION ADDENDUM
www.ti.com
16-May-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
SN74GTL2003PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74GTL2003PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN74GTL2003RKSR
ACTIVE
VQFN
RKS
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74GTL2003PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74GTL2003RKSR
VQFN
RKS
20
3000
177.8
12.4
2.73
4.85
1.03
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74GTL2003PWR
SN74GTL2003RKSR
TSSOP
PW
20
2000
367.0
367.0
38.0
VQFN
RKS
20
3000
202.0
201.0
28.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated