User's Guide SLOU330 – December 2011 EVM Description The AFE722x EVM includes a great level of flexibility to enable the user to test it in a more system like environment. The individual power rails can be generated through LDOs or DC/DC converters from a 6 V power source and the EVM clock architecture allows for external clock input as well as clock generation using a low jitter PLL in combination with a VCXO. On the transmit side the EVM provides the option of connecting directly to the DAC outputs or perform up-conversion via on board IQ modulator. On the digital side the EVM provides a seamless interface to the TSW1200 capture card in order to evaluate received data directly on a PC. The TSW3100 pattern generation card can be used to provide data to the dual DAC of the AFE722x and the on board CDCE72010 generates the appropriate clock for the TSW3100 for synchronous operation. Both AFE722x and CDCE72010 can be programmed via SPI conveniently through the USB connection. IQ Modulator Output LO Input Clock Inputs DAC Outputs for ChA and ChB 6V Power Input Power Supply Jumpers for LDO/DCDC, iQ Mod and CDCE72010 TSW3100 ADC Input for ChA and ChB USB AUX ADC and DAC TSW1200 SLOU330 – December 2011 Submit Documentation Feedback EVM Description Copyright © 2011, Texas Instruments Incorporated 1 Software Installation 1 2 3 4 5 6 7 8 9 www.ti.com Contents Software Installation ........................................................................................................ 2 AFE722x.ini file for TSW1200 ............................................................................................. 3 AFE722x EVM Software - SPI Control ................................................................................... 3 Initial EVM Setup and Basic Test Procedure ............................................................................ 4 4.1 CDCE72010 Configuration ....................................................................................... 4 4.2 RX Path Using TSW1200 ......................................................................................... 5 4.3 TX Path Using TSW3100 ......................................................................................... 6 Power Supply Options ...................................................................................................... 9 Clocking Configuration ..................................................................................................... 9 6.1 Non-VCXO Option (default) ..................................................................................... 10 6.2 System Level ...................................................................................................... 11 6.3 RX Only ............................................................................................................ 11 6.4 RX and TX Independent Clocking .............................................................................. 11 6.5 Interpolation on the DAC ........................................................................................ 11 6.6 Decimation on the ADC .......................................................................................... 12 RX Setup ................................................................................................................... 12 TX Setup .................................................................................................................... 13 Trouble Shooting of the EVM Setup .................................................................................... 15 List of Figures List of Tables 1 1 Control Registers............................................................................................................ 6 2 Clock Delays for Listed DAC Sampling Rates .......................................................................... 7 3 IP Address Digit Selection Using SW2 ................................................................................. 17 Software Installation 1. 2. 3. 4. Open folder named AFE722x_Installer_vxpx (xpx represents the latest version) Run Setup.exe Follow the on-screen instructions Once installed, launch by clicking on the AFE722x_GUI_vxpx program in Start >Texas Instruments ADCs. 5. When plugging in the USB cable for the first time, the user will be prompted to install the USB drivers for ‘USB Serial Converter’ and ‘USB Serial Port’ (see ). (a) Follow the on-screen instructions to install the USB drivers. (b) If needed, you can access the drivers directly in the install directory 2 EVM Description Copyright © 2011, Texas Instruments Incorporated SLOU330 – December 2011 Submit Documentation Feedback AFE722x.ini file for TSW1200 www.ti.com 2 AFE722x.ini file for TSW1200 The AFE722x software package comes with a new ini file for the TSW1200. This AFE722x.ini file should be placed manually into the following directory in order for the TSW1200 to recognize it: C:\Program Files\Texas Instruments\TSW1200\ADC Files 3 AFE722x EVM Software - SPI Control The AFE722x EVM software controls the AFE722x and CDCE72010 on the EVM via SPI register writes through a USB connection with the PC. Below is a snapshot of the GUI front panel highlighting the various tabs to control the setup of AFE722x as well as CDCE72010. It is required to perform a USB reset after applying power to the EVM to establish proper connection with the PC. A warning sign on the bottom right will flash otherwise indicating USB communication failure. Tabs to control basic setup, RX and TX & SYNC registers as well as CDCE72010 Reset USB port on FTDI chip – required after power up of AFE722x EVM. Control to send or read all registers (AFE722x and CDCE72010) as well as load or save register files. Individual control registers Warning indication that USB communication is not established. Summary of current registers being written showing 12bit address & 8bit data in hex format as well as 8bit in binary format. The EVM software also provides the option to save all registers to a file or to load registers from a file. SLOU330 – December 2011 Submit Documentation Feedback EVM Description Copyright © 2011, Texas Instruments Incorporated 3 Initial EVM Setup and Basic Test Procedure 4 www.ti.com Initial EVM Setup and Basic Test Procedure The fastest way to get the AFE722x EVM up and running is to follow this operating procedure: • Two signal generators should be connected to the clock and data input of the EVM - preferably with band pass filter and 10MHz reference locked for coherency. • Clock input should be connected to ‘CDC AUX IN’ input for AUX clock setup and the clock generator amplitude should be set to ~10-13dBm. • TSW1200 (RX) capture card should be plugged in AFE722x EVM and connected to the PC via USB. • TSW3100 (TX) pattern generation card plugged into AFE722x EVM and connected to PC via Ethernet cable. • All appropriate power supplies should be connected – blue LED (D2) on AFE722x EVM indicating power good status. • After performing USB reset in AFE722x EVM software, the flashing USB warning sign should disappear indicating successful USB communication. 4.1 CDCE72010 Configuration The initial EVM setup is configured so that the AFE722x can be operated at any desired sampling rate. Since the TSW3100 requires an external clock at ¾ of the AFE clock rate (see clocking section) the external clock applied to the ‘CDC AUX IN’ connector needs to be 3x the AFE sampling rate (e.g. 368.64MHz for 122.88MHz operation). Loading a preconfigured register file (‘AUX IN - div3 AFE div4 TSW.txt’) to the CDCE72010, it then sets the dividers so that a /3 copy of the input clock is routed to the AFE722x clock input and a /4 copy to the TSW3100. CDCE72010 /3 CDC AUX IN AFE722x 368.64MHz /4 4 122.88MHz 92.16MHz EVM Description Copyright © 2011, Texas Instruments Incorporated TSW3100 SLOU330 – December 2011 Submit Documentation Feedback Initial EVM Setup and Basic Test Procedure www.ti.com 4.2 RX Path Using TSW1200 First the AFE722x digital interface needs to be configured to match the serial LVDS interface that the TSW1200 is expecting. The following control registers need to be set in the ‘General Setup’ tab of the AFE722x programming software. Also the USB communication warning sign should be monitored after the USB reset to ensure proper communication with the AFE722x EVM. Register Bit Setting Interface Serial LVDS Master Override Enabled Format Offset Binary Serial LVDS 2 Wire Data Orientation MSB First SDR Mode Disabled Wordwise Output Disabled Bitwise RX Disabled Halfrx in 2wire Disabled The general setup tab includes controls for the digital RX interface The section controls the setup of the digital interface as well as test modes and digital features such as decimation and loopback In the TSW1200 software, the AFE722x should be selected as the ADC. Next the sampling rate and ADC input frequency need to be entered and the TSW1200 software will calculate the coherent frequency. Performing a capture should yield: Fs=122.88Msps Fin= 9.98625MHz SLOU330 – December 2011 Submit Documentation Feedback EVM Description Copyright © 2011, Texas Instruments Incorporated 5 Initial EVM Setup and Basic Test Procedure Select AFE722x for ADC www.ti.com Perform FFT capture Enter ADC sampling rate Enter desired input frequency 4.3 TX Path Using TSW3100 First the AFE722x digital interface needs to be configured to match the serial LVDS interface from the TSW3100. The following control registers need to be set in the ‘General Setup’ tab of the AFE722x programming software. Also the USB communication warning sign should be monitored after the USB reset to ensure proper communication with the AFE722x EVM. Table 1. Control Registers Register Bit Setting Interface Serial LVDS Master Override Enabled Serial LVDS 2 Wire Data Orientation MSB first Format 2s Complement Clock Delay Enabled Clock Delay 300ps Frame Clock Delay Disabled Frame Clock Delay 0ps The data coming from the TSW3100 is edge aligned while the AFE722x expects the serial LVDS data to arrive edge centered. Here the programmable clock delay inside the AFE722x can be used to delay the edge aligned clock closer towards the center of the data. DCLK Data The table below shows clock delays for listed DAC sampling rates that showed proper operation. 6 EVM Description Copyright © 2011, Texas Instruments Incorporated SLOU330 – December 2011 Submit Documentation Feedback Initial EVM Setup and Basic Test Procedure www.ti.com Table 2. Clock Delays for Listed DAC Sampling Rates DAC Sampling Rate Suitable Clock Delay 130Msps 0ps to 900ps 122.88Msps 0ps to 900ps 100Msps 0ps to 1.2ns 80Msps 0ps to 1.8ns 65Msps 0ps to 2.1ns 40Msps 0ps to 2.1ns The general setup tab includes controls for the digital TX interface This section controls the setup of the digital interface as well as the TX interpolation For TX the output data of the TSW3100 needs to be properly configured for 6x serialization using Matlab. 1. Install Matlab runtime engine (MCRInstaller.exe) 2. Open one of the executable (.exe) TSW3100 GUIs – ‘TSW3100_MultitonePattern_v2p7.exe 3. Enter DAC sampling rate 4. Enter tone frequencies SLOU330 – December 2011 Submit Documentation Feedback EVM Description Copyright © 2011, Texas Instruments Incorporated 7 Initial EVM Setup and Basic Test Procedure www.ti.com Specify DAC sampling rate Set tone output frequency Press ‘Create and Save/Run TSW3100’ to load data into TSW3100 Specify serial LVDS as data format Ensure match on data format with AFE722x setup (e.g. 2s complement) Select ‘Load and Run’ option The DAC output should show something like this on the spectrum analyzer (example with sample rate = 122.88 MSPS, input tone = 10 MHz). 8 EVM Description Copyright © 2011, Texas Instruments Incorporated SLOU330 – December 2011 Submit Documentation Feedback Power Supply Options www.ti.com 5 Power Supply Options The AFE722x EVM is designed to operate from an external 6 V wall wart supply. A LDO generates a 5V rail for the TRF3703 IQ modulator as well as for the low noise LDOs which are generating a 3.3 V and 1.8 V rail for the AFE722x and the CDCE72010. Alternatively the 3.3 V and 1.8 V rails can be generated using DC/DC converters which operate directly from the 6 V input for maximum power efficiency. The EVM provides options to disable unused circuits by means of pin headers. These headers can also be used for accurate power measurements where external power supplies can be directly connected to them. Three pin headers allow a convenient change between powering the AFE722x and CDCE72010 either from DC/DC converter or low noise LDO. 6V Input LDO TPS7A4501 JP10 5V TRF3703 I/Q Mod JP19 LDO TPS79633 JP12 3.3V JP18 CDCE72010 JP11 DC/DC TPS62291 6V JP4 VCXO JP14 LDO TPS79518 JP13 AFE722x 1.8V JP20 DC/DC TPS62231 6 Clocking Configuration The AFE722x EVM offers 3 different options for providing the clock to the AFE722x as well as the supporting circuitry. The biggest challenge arises when using the DAC with the TSW3100 because the TSW3100 expects an input clock at 1/8 of the DAC input data rate. However since the AFE722x is designed for the serial LVDS interface, the DAC data rate is 6x the actual AFE722x clock frequency. Hence the clock to the TSW3100 needs to 6/8 = 3/4x the AFE722x clock frequency. SLOU330 – December 2011 Submit Documentation Feedback Serialized LVDS AFE7225 6x DAC Rate TSW3100 Pattern Generator Synchronous Clock @ 1/8 DAC Rate EVM Description Copyright © 2011, Texas Instruments Incorporated 9 Clocking Configuration www.ti.com The CDCE72010 clock buffer on the AFE722x is used to provide the clock to the TSW3100. Additional dividers can be added to the clock output in order to divide the clock appropriately for optional interpolation by 2x or 4x. SMA Connector CLK IN R74 0S R112 0S DNI DNI Clk In R76 0S R144 0S C70 22pF DNI BPF DNI R72 0S C71 22pF DNI SMA Connector CDC AUX IN Y1P CLK IN-N DNI Y1N PLL Lock AUX Y2P TSW3100 CDCE72010 Y2N TCXO 19.2 MHz Sec Ref Pri Ref ext ext ext ext ext 3x clock to CDC AUX IN (see 6.5) 3x clock to CDC AUX IN (see 6.1) 10MHz clock on REF IN (see 6.2) 10MHz clock on REF IN (see 6.2/6.5) 122.88MHz clock on REF IN (see 6.2) Non-VCXO Option (default) This setup is the default configuration and provides the option to operate AFE722x and TSW3100 synchronous at any arbitrary sampling rate without the use of a VCXO. This setup is useful for testing the AFE722x at clock frequencies where a VCXO is not immediately available. 10 SMA Connector R81 0S DNI R79 0S DNI Preconfigured setup files: AUX IN – INT2x – div3 AFE div8 TSW.txt AUX IN – div3 AFE div4 TSW.txt REF IN (10MHz) – div6 AFE div8 TSW.txt REF IN (10MHz) – INT2x – div6 AFE div16 TSW.txt REF IN (122.88MHz) – div6 AFE div8 TSW.txt 6.1 R161 0S DNI PLL Lock Y0P SMA Connector REF IN R86 0S AFE722x CDCE72010 Opt. BPF /3 AFE722x /4 TSW3100 x3 AUX IN EVM Description Copyright © 2011, Texas Instruments Incorporated SLOU330 – December 2011 Submit Documentation Feedback Clocking Configuration www.ti.com 6.2 System Level In this system configuration on the EVM a VCXO at 6x the desired clock frequency is required – alternatively a different VCXO frequency can be used and the internal CDCE72010 dividers adjusted accordingly. An external reference can be locked to the VCXO for coherency using the CDCE72010. In this configuration the CDCE72010 provides a /6 copy of the VCXO to the AFE722x clock input as well as a /8 copy to the TSW3100. Also the AFE722x EVM offers a placeholder for a surface mount bandpass filter between CDCE72010 and AFE722x to limit the clock phase noise. 6.3 CDCE72010 Ext Ref In /6 6x Fs /8 VCXO 92.16 MHz TSW3100 737.28MHz RX Only AFE722x VCXO CDCE72010 RX and TX Independent Clocking The AFE722x supports an option to run the dual ADCs at a different sampling rate than the dual DACs. With a few resistor changes, the clocking circuitry on the AFE722x EVM can be configured to support that feature. However in this scenario the CDCE72010 is bypassed and no clock is routed back to the TSW3100. Hence an additional clock needs to be provided and the CDCE72010 configured with the appropriate output divider to match the AFE722x DAC clock rate with the data rate from the TSW3100 (see 6.1 & 6.2). 6.5 AFE722x E.g. 10 MHZ or 122.88 MHz When testing only the ADCs for maximum performance, the EVM provides an option to connect an external clock directly to the AFE bypassing the CDCE72010. R74, R76 and R112 need to be modified from their default configuration. The DACs of the AFE can still be operated however the TSW3100 can’t be used for data generation as no feedback clock is provided to it. This option provides the lowest possible jitter option when combined with an external bandpass filter. 6.4 122.88 MHz SMA R112 R74 Connector 0S 0S CLK IN R76 DNI SMA Connector CLK IN\ R79 DNI R161 0S R78 0S CLK INP R82 50S T9 C56 DNI CLK INN AFE722x 0S 0S Interpolation on the DAC The AFE722x offers 2x and 4x interpolation of the DAC output data. In order to employ interpolation on the DAC, the clock going to the TSW3100 needs to be divided accordingly. For example interpolation by 2x in the DAC requires that the data coming from the TSW3100 arrives at ½ of the AFE722x clock frequency. SLOU330 – December 2011 Submit Documentation Feedback CDCE72010 Opt. BPF /3 AFE722x /8 TSW3100 x3 AUX IN EVM Description Copyright © 2011, Texas Instruments Incorporated 11 RX Setup 6.6 www.ti.com Decimation on the ADC On the receive channels of the AFE722x, the output can be decimated by 2x using the on-chip FIR halfband filter. This has no impact on the clock requirements to the AFE722x – it merely reduces the output data rate by a factor of 2x and settings (sampling and input frequency) on the TSW1200 capture card or other data capture tool need to adjusted accordingly. 7 RX Setup The RX section of the AFE722x is controlled on two separate tabs of the EVM software. In the ‘General Setup’ tab are the control registers for the digital interface such as CMOS or serial LVDS output for example. In order to use the TSW1200 to capture the received data the following register settings are required: Register Bit Interface Master Override Format Serial LVDS Data Orientation DSR Mode Wordwise Output Bitwise RX Halfrx in 2wire Setting Serial LVDS Enabled Offset Binary 2 Wire MSB First Disabled Disabled Disabled Disabled This tab also controls the register to set the digital interface to test pattern mode and custom patterns can be loaded as well. Furthermore RX decimation settings as well as TX RX loopback mode are controlled here as well. 12 The general setup tab includes controls for the digital RX interface The section controls the setup of the digital interface as well as test modes and digital features such as decimation and loopback EVM Description Copyright © 2011, Texas Instruments Incorporated SLOU330 – December 2011 Submit Documentation Feedback TX Setup www.ti.com The other portion of the RX setup is located on the ‘Receive Control’ tab which includes register access for the mixing stage, power meter and power options for the digital RX section. Also the auxiliary ADC registers are configured on this tab. RX controls are located on this tab Mixing section controls gain, offset, mixing mode and NCO This section controls power down options on digital RX chain The power meter indicates the input power level to the two ADCs 8 This section controls auxiliary ADC and its mux input TX Setup For the transmit output, the AFE722x EVM provides an option to directly route the DACs to SMA connectors as well as an option to connect the dual DAC to an IQ modulator (TRF3703) for direct up-conversion. The schematic below shows the two options and the relevant 0Ω resistors to switch between them. When using the IQ modulator, there is a separate SMA connector on the EVM for the LO input. Also there is a low pass filter between DAC and IQ modulator for image suppression with a default cut off frequency of 125 MHz. SLOU330 – December 2011 Submit Documentation Feedback EVM Description Copyright © 2011, Texas Instruments Incorporated 13 TX Setup www.ti.com R46 0S SMA Connector DAC A R56 0S R127 DNI R133 DNI SMA Connector LO Fc=125 MHz TRF3703 RF Out SMA Connector R114 DNI R120 DNI SMA Connector R58 0S DAC B R68 0S When using the TSW3100 as a pattern generator for the AFE722x, first the digital interface needs to be configured to match the serial LVDS interface from the TSW3100. Following control registers need to be set in the ‘General Setup’ tab of the AFE722x programming software. Also the USB communication warning sign should be monitored after the USB reset to ensure proper communication with the AFE722x EVM. Register Bit Interface Master Override Serial LVDS Data Orientation Format Clock Delay Clock Delay Frame Clock Delay Frame Clock Delay 14 Setting Serial LVDS Enabled 2 Wire MSB First 2s Complement Enabled 300ps Disabled Disabled EVM Description Copyright © 2011, Texas Instruments Incorporated SLOU330 – December 2011 Submit Documentation Feedback Trouble Shooting of the EVM Setup www.ti.com Also the data coming from the TSW3100 is edge aligned while the AFE722x expect the serial LVDS data to arrive edge centered. Here the programmable clock delay can be used to delay the edge aligned clock closer towards the center of the data. The table below shows clock delays for listed DAC sampling rates that showed proper operation:. DAC Sampling Rate 130Msps 122.88Msps 100Msps 80Msps 65Msps 40Msps DCLK Data Suitable Clock Delay 0ps to 900ps 0ps to 900ps 0ps to 1.2ns 0ps to 1.8ns 0ps to 2.1ns 0ps to 2.1ns The other portion of the TX setup is located on the ‘Transmit Control’ tab which includes register access for the mixing stage, FIFO, Loopback and power options for the digital TX section. Also the auxiliary DAC registers are configured on this tab. TX controls are located on this tab This section controls the TX FIFO Mixing section controls gain, offset, mixing mode and NCO This section controls power down options on digital TX chain RX to TX Loopback Enable This section controls auxiliary DACs 9 Trouble Shooting of the EVM Setup The two main problems engineers face are covered in this chapter. Often times a programming step is missed leading to faulty or no data either on the RX or TX side. Please refer to AFE722x Setup.pdf in the support documentation which includes more detailed instructions along with power measurements for correlation. The second issue covers unsuccessful data transfer from the TSW3100 to the AFE722x EVM. This most likely can be traced back to an IP address conflict between the PC and the TSW3100. The following steps should provide a solution for that problem. TSW3100 IP Configuration SLOU330 – December 2011 Submit Documentation Feedback EVM Description Copyright © 2011, Texas Instruments Incorporated 15 Trouble Shooting of the EVM Setup www.ti.com Step 1: Computer Configuration: 1. ensure that both Windows Firewall and Enterprise Firewall are turned off 2. determine which Ethernet port is connected to the TSW3100. 3. set the address of the Ethernet port to be the following (192.168.1.120): Step 2: TSW3100 Configuration: 1. Ensure that the SW2 dip switches are all set to open (open side down). This will set the TSW3100 to be IP address 192.168.1.123 16 EVM Description Copyright © 2011, Texas Instruments Incorporated SLOU330 – December 2011 Submit Documentation Feedback Trouble Shooting of the EVM Setup www.ti.com Table 3. IP Address Digit Selection Using SW2 DIP0 Position DIP1 Position IP Address Closed Closed 192.168.1.120 Closed Open 192.168.1.121 Open Closed 192.168.1.122 Open Open 192.168.1.123 2. To confirm, ping both 192.168.1.123 and 192.168.1.120 Open a command prompt and type in: Ping 192.168.1.120 Ping 192.168.1.123 and watch for 0% packet loss. 3. If both address response, then TSW3100 works. TSW3100 version check: telnet 192.168.1.123 cd etc more version SLOU330 – December 2011 Submit Documentation Feedback EVM Description Copyright © 2011, Texas Instruments Incorporated 17 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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