EP5348UI 400mA Synchronous Buck Regulator with Integrated Inductor RoHS Compliant; Halogen Free Description Features The EP5348UI delivers the optimal trade-off between footprint and efficiency. It is a perfect alternative to replace less efficient LDOs in space constrained applications that require improved efficiency. • Integrated Inductor Technology • 400mA continuous output current • 2.0mm x 1.75mm x 0.9mm uQFN package • Small Solution Footprint The EP5348UI is a 400mA PowerSoC which integrates MOSFET switches, control, compensation, and the magnetics in a microQFN Package. This highly integrated DCDC solution offers up to 46-points better efficiency than the comparable LDO. A significant reduction in power loss and improved thermals are achieved. It enables extended battery life and helps Meet Energy Star requirements. • Efficiency, up to 90% • VOUT Range 0.6V to VIN – VDROP_OUT • Short circuit and over current protection • UVLO and thermal protection • IC level reliability in a PowerSoC solution Applications 95 • Applications where poor LDO efficiency creates: o Thermal challenges o Battery Life challenges o Failure to meet Energy Star requirements 35 • Space-constrained applications 25 • Portable media players and USB peripherals VIN = 5.0V VOUT = 1.2V 85 EP5348UI LDO Efficiency (%) 75 65 55 Δ = 46-points 45 15 0.0 0.1 0.2 0.3 Load Current (A) VOUT PVIN VIN Integrated magnetics enables a tiny solution footprint, low output ripple, and high reliability, while maintaining high efficiency. The complete solution size is similar to an LDO and much smaller than a comparable DCDC. CIN 2.2µF 0603 VOUT AVIN 0.1µF CAVIN EP5348 ENABLE AGND CA RA VFB PGND COUT 10µF 0603 RB Figure 1: Typical Application Schematic www.enpirion.com 05721 September 12, 2012 Rev: C EP5348UI Ordering Information Part Number Package 14-pin μQFN T&R EP5348UI EP5348UI-E Pin Assignments (Top View) EP5348UI Evaluation Board Figure 2: EP5348UI Pin Out Diagram (Top View) Pin Description PIN NAME 1, 13, 14 NC(SW) 2 PGND 3, 8, 9 NC 4 VFB 5 AGND 6, 7 10 11 12 VOUT ENABLE AVIN PVIN FUNCTION NO CONNECT – These pins are internally connected to the common switching node of the internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage to the device. Power ground. Connect this pin to the ground electrode of the Input and output filter capacitors. NO CONNECT: These pins may already be connected inside the device. Therefore, they cannot be electrically connected to each other or to any external signal, voltage, or ground. They must however be soldered to the PCB. Failure to follow this guideline may result in device damage. Feedback pin for external voltage divider network. Analog ground. This is the quiet ground for the internal control circuitry, and the ground return for external feedback voltage divider Regulated Output Voltage. Refer to application section for proper layout and decoupling. Output Enable. Enable = logic high; Disable = logic low Input power supply for the controller circuitry. Connect to VIN at a quiet point. Input Voltage for the MOSFET switches. ©Enpirion 2012 all rights reserved, E&OE 05721 2 September 12, 2012 www.enpirion.com Rev: C EP5348UI Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER Absolute Maximum Electrical Ratings SYMBOL MIN MAX UNITS VIN -0.3 6.0 V Voltage on ENABLE -0.3 VIN+ 0.3 V Voltage on VFB -0.3 2.7 V 2000 V Supply Voltage – PVIN, AVIN, VOUT ESD Rating (based on Human Body Mode) ESD Rating (Charge Device Model) 500 V Absolute Maximum Thermal Ratings Maximum Operating Junction Temperature TJ-ABS Storage Temperature Range TSTG -65 Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C 150 °C 150 °C 260 °C Recommended Operating Conditions PARAMETER Input Voltage Range Output Voltage Range SYMBOL MIN MAX UNITS VIN 2.5 5.5 V † VOUT 0.6 VIN-VDO Operating Ambient Temperature TA -40 +85 °C Operating Junction Temperature TJ -40 +125 °C † V VDO (drop-out voltage) is defined as (ILOAD x Dropout Resistance). Please see the EC Table. Thermal Characteristics PARAMETER Thermal Shutdown Trip Point SYMBOL TYP UNITS TJ-TP +155 °C 15 °C 105 °C/W Thermal Shutdown Trip Point Hysteresis θJA Thermal Resistance: Junction to Ambient –0 LFM (Note 1) Note 1: Based on 2 oz. external copper layers and proper thermal design in line with EIA/JEDEC JESD51-7 standard for high effective thermal conductivity boards. ©Enpirion 2012 all rights reserved, E&OE 05721 3 September 12, 2012 www.enpirion.com Rev: C EP5348UI Electrical Characteristics NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V. CIN = 2.2µF 0603 MLCC, COUT = 10µF 0603. PARAMETER SYMBOL TEST CONDITIONS MIN TYP Operating Input Voltage Range VIN Under Voltage Lock-out – VIN Rising VUVLO_R 2.3 V Under Voltage Lock-out – VIN Falling VUVLO_F 2.2 V Shut-down Supply Current ISD Enable = Low 3 µA VFB Voltage Initial Accuracy VFB TA = 25°C, VIN = 3.6V; ILOAD = 100mA ; 0.8V ≤ VOUT ≤ 3.3V Line Regulation ΔVOUT_LINE 2.5V ≤ VIN ≤ 5.5V 0.03 %/V Load Regulation ΔVOUT_LOAD 0A ≤ ILOAD ≤ 400Ma 0.48 %/A Temperature Variation ΔVOUT_TEMPL -40°C ≤ TA ≤ +85°C 24 ppm/°C Feedback Pin Input Current IFB Note 1 <300 nA Output Current IOUT OCP Threshold ILIM 2.5V ≤ VIN ≤ 5.5V 0.6V ≤ VOUT ≤ 3.3V 1.4 Output Dropout Resistance (Note 1) Voltage (Note 1,2) RDO VDO_FL Input to Output Resistance VINMIN - VOUT at Full load 520 208 Operating Output Voltage Range VOUT VDO = IOUT * RDO Enable Pin Logic Low VENLO Enable Pin Logic High VENHI Enable Pin Current IENABLE Operating Frequency FOSC 2.5 0.588 0.600 0 MAX UNITS 5.5 V 0.612 400 mA A 0.6 780 312 mΩ mV VIN-VDO V 0.3 V 1.4 Note 1 V V <200 nA 9 MHz Soft Start Operation VOUT Rise Time TRISE From 0 to full output voltage 1.17 1.8 2.43 mSec Notes: 1 - Parameter guaranteed by design 2 - VDO_FL (full-load drop-out voltage) is defined as (Maximum IOUT x Dropout Resistance) ©Enpirion 2012 all rights reserved, E&OE 05721 4 September 12, 2012 www.enpirion.com Rev: C EP5348UI 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Typical Performance Characteristics 60 50 Top to Bottom: 40 60 50 Top to Bottom: 40 VOUT=3.3V VOUT=2.5 VIN = 3.3V 30 VOUT=2.5V VIN = 5.0V 30 VOUT=1.8 VOUT=1.8V VOUT=1.2 20 VOUT=1.2V 20 0.0 0.1 0.2 Load Current (A) 0.3 0.4 0.0 Efficiency vs. Load Current: VIN = 3.3V, VOUT (from top to bottom) = 2.5, 1.8, 1.2V 0.4 Output Ripple: VIN = 3.3V, VOUT = 1.0V, Iout = 400mA CIN = 2.2μF/0603, COUT = 10μF/0603 + 2.2uF/0603 500 MHz BW Output Ripple: VIN = 5V, VOUT = 1.0V, Iout = 400mA CIN = 2.2μF/0603, COUT = 10μF/0603 + 2.2uF/0603 Output Ripple: VIN = 5V, VOUT = 1.0V, Iout = 400mA CIN = 2.2μF/0603, COUT = 10μF/0603 + 2.2uF/0603 05721 0.3 500 MHz BW 20 MHz BW limit ©Enpirion 2012 all rights reserved, E&OE 0.2 Load Current (A) Efficiency vs. Load Current: VIN = 5.0V, VOUT (from top to bottom) = 3.3, 2.5, 1.8, 1.2V 20 MHz BW limit Output Ripple: VIN = 3.3V, VOUT = 1.0V, Iout = 400mA CIN = 2.2μF/0603, COUT = 10μF/0603 + 2.2uF/0603 0.1 5 September 12, 2012 www.enpirion.com Rev: C EP5348UI Load Transient: VIN = 3.3V, VOUT = 1.0V Ch.1: VOUT, Ch.2: ILOAD 0↔400mA CIN = 2.2μF/0603, COUT = 10μF/0603 + 2.2uF/0603 Load Transient: VIN = 5V, VOUT = 1.0V Ch.1: VOUT, Ch.2: ILOAD 0↔400mA CIN = 2.2μF/0603, COUT = 10μF/0603 + 2.2uF/0603 Power Up/Down at No Load: VIN/VOUT = 5.0V/1.2V, Cout ≈ 10µF, Ch.1: ENABLE, Ch. 2: VOUT, Ch.4: IOUT Power Up/Down into 3Ω load: VIN/VOUT = 5.5V/3.3V, Cout ≈ 10µF, Ch.1: ENABLE, Ch. 2: VOUT, Ch.4: IOUT ©Enpirion 2012 all rights reserved, E&OE 05721 6 September 12, 2012 www.enpirion.com Rev: C EP5348UI Detailed Description Functional Overview The EP5348UI requires only 2 small MLCC capacitors and a few small-signal components for a complete DC-DC converter solution. The device integrates MOSFET switches, PWM controller, Gate-drive, part of the loop compensation, and inductor into a tiny 2.0mm x 1.75mm x 0.9mm micro-QFN package. Advanced package design, along with the high level of integration, provides very low output ripple and noise. The EP5348UI uses voltage mode control for high noise immunity and load matching to advanced ≤90nm loads. An external resistor divider is used to program output setting over the 0.6V to VIN-VDROPOUT as specified in the Electrical Characteristics Table. The EP5348UI provides the industry’s highest power density of any 400mA DC-DC converter solution. The key enabler of this revolutionary integration is Enpirion’s proprietary power MOSFET technology. The advanced MOSFET switches are implemented in deep-submicron CMOS to supply very low switching loss at high switching frequencies and to allow a high level of integration. The semiconductor process allows seamless integration of all switching, control, and compensation circuitry. The proprietary magnetics design provides high-density/high-value magnetics in a very small footprint. Enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal solution with assured performance over the entire operating range. Protection features include under-voltage lockout (UVLO), over-current protection (OCP), short circuit protection, and thermal overload protection. Integrated Inductor The EP5348UI utilizes a proprietary low loss integrated inductor. The integration of the inductor greatly simplifies the power supply design process. The inherent shielding and compact construction of the integrated inductor reduces the noise that can couple into the ©Enpirion 2012 all rights reserved, E&OE 05721 traces of the printed circuit board. Further, the package layout is optimized to reduce the electrical path length for the high di/dT currents that are always present in DC-DC converters. The integrated inductor provides the optimal solution to the complexity, output ripple, and noise that plague low power DC-DC converter design. Control Matched to sub 90nm Loads The EP5348UI utilizes a type III compensation network. Voltage mode control is inherently impedance matched to the sub 90nm process technology that is used in today’s advanced ICs. Voltage mode control also provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are maintained over the entire load range. The very high switching frequency allows for a very wide control loop bandwidth and hence excellent transient performance. Soft Start Internal soft start circuits limit the rate of output voltage rise when the device starts up from a power down condition, or when the “ENABLE” pin is asserted “high”. Digital control circuitry controls the VOUT rise time to ensure a smooth turn-on ramp. The EP5348UI has a fixed VOUT turn-on time. Therefore, the ramp rate will vary with the output voltage setting. Output voltage rise time is given in the Electrical Characteristics Table. Excess bulk capacitance on the output of the device can cause an over-current condition at startup. The maximum total capacitance on the output, including the output filter capacitor, and bulk and decoupling capacitance at the load, is given as: COUT_TOTAL_MAX = 9.333 x 10-4 / VOUT The nominal value for the output filter capacitor is 10uF. See the applications section for more details. Over Current/Short Circuit Protection The current limit function is achieved by sensing the current flowing through a sense P7 September 12, 2012 www.enpirion.com Rev: C EP5348UI MOSFET which is compared to a reference current. When this level is exceeded the PFET is turned off and the N-FET is turned on, pulling VOUT low. This condition is maintained for approximately 0.5mS and then a normal soft start is initiated. If the over current condition still persists, this cycle will repeat. Enable The ENABLE pin provides a means to shut down the converter or enable normal operation. A logic low will disable the converter and cause it to shut down. A logic high will enable the converter into normal operation. Under Voltage Lockout NOTE: The ENABLE pin must not be left floating. During initial power up an under voltage lockout circuit will hold-off the switching circuitry until the input voltage reaches a sufficient level to ensure proper operation. If the voltage drops below the UVLO threshold, the lockout circuitry will disable the switching. Hysteresis is included to prevent chattering between states. Thermal Shutdown When excessive power is dissipated in the chip, the junction temperature rises. Once the junction temperature exceeds the thermal shutdown threshold, the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. When the junction temperature decreases by 15C°, the device will go through the normal startup process. Application Information A 5pF MLCC capacitor CA is also required in parallel with RA for compensation. Output Voltage Programming VOUT PVIN VIN VOUT AVIN CIN 2.2µF 0603 0.1µF CAVIN EP5348 ENABLE AGND CA RA VFB PGND COUT 10µF 0603 RB Figure 3: Typical Application Circuit The EP5348UI uses a simple resistor divider to program the output voltage. Referring to Figure 3, use 200 kΩ, 1% or better for the upper resistor (RA). The value of the bottom resistor (RB) in kΩ is given as: RB = VFB * R A (VOUT − VFB) VFB = 0.6V nominal ©Enpirion 2012 all rights reserved, E&OE 05721 Input Filter Capacitor CIN_MIN = 2.2µF 0603 case size or larger. The input capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switchmode DC-DC converter input filter applications. Output Filter Capacitor COUT_MIN = 10uF 0603 + 2.2uF 0603 MLCC when 4.5V ≤ VIN ≤ 5.5V, AND IOUT > 300mA. COUT_MIN = 10uF 0603 MLCC for all other use cases. However, ripple performance can always be improved by adding a second 2.2uF or 1uF output capacitor for any operating condition. VOUT has to be sensed at the last output filter capacitor next to the EP5348UI. Any additional bulk capacitance for load decoupling and byass has to be far enough from the VOUT 8 September 12, 2012 www.enpirion.com Rev: C EP5348UI sensing point so that it does not interfere with the control loop operation. Excess total capacitance on the output (Output Filter + Bulk) can cause an over-current condition at startup. Please see the Soft Start section under Functional Overview for the maximum allowable bulk capacitance on the output rail. The output capacitor must use a X5R or X7R or equivalent dielectric formulation. Y5V or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switchmode DC-DC converter output filter applications. LDO Replacement The Enpirion EP5348UI is a suitable replacement for inefficient LDOs and can be used to augment the LDOs in a PMU with minimum footprint impact. This integrated DCDC solution offers significantly better efficiency, and significant reduction in power loss. The resulting improved thermals and extended battery life helps meet Energy Star requirements. The total solution size is 25% smaller than a comparable LDO and half the footprint of a comparable DCDC. As the table below shows, EP5348UI provides the optimal trade-off between footprint and efficiency when compared to a traditional LDO: VIN (V) 5.0 5.0 5.0 5.0 3.3 3.3 3.3 VOUT LOAD EFF (V) (mA) DCDC 1.2 1.8 2.5 3.3 1.2 1.8 2.5 400 400 400 400 400 400 400 70.4% 76.4% 81.6% 87.7% 77.1% 83.3% 88.2% EFF LDO 24.0% 36.0% 50.0% 66.0% 36.4% 54.5% 75.8% PLOSS DCDC (mW) 202 222 225 185 143 144 134 PLOSS LDO (mW) 1520 1280 1000 680 840 600 320 Power Saved (mW) 1318 1058 775 495 697 456 186 Power-Up/Down Sequencing During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be powered down before the PVIN. Tying PVIN and AVIN or all three pins (AVIN, PVIN, ENABLE) together during power up or power down meets these requirements. Pre-Bias Start-up The EP5348UI does not support startup into a pre-biased condition. Be sure the output capacitors are not charged or the output of the EP5348UI is not pre-biased when the EP5348UI is first enabled. Layout Recommendations Figure 4: Top PCB Layer Critical Components and Copper for Minimum Footprint Figure 5: Bottom PCB Layer Critical Components (RA, RB, CA) & Copper for Minimum Footprint ©Enpirion 2012 all rights reserved, E&OE 9 05721 September 12, 2012 www.enpirion.com Rev: C EP5348UI Figures 4 and 5 show critical PCB top and bottom layer components and traces for a minimum-footpint recommended EP5348 layout with ENABLE tied to VIN. Alternate ENABLE configurations need to be connected and routed according to specific customer application. This layout consists of four layers. For the other 2 layers and the exact dimensions, please see the Gerber files at www.enpirion.com. The recommendations given below are general guidelines. Customers may need to adjust these according to their own layout and manufacturing rules. Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as close to the EP5348UI package as possible. They should be connected to the device with very short and wide traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The +V and GND traces between the capacitors and the EP5348UI should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. Recommendation 2: The system ground plane should be the first layer immediately below the surface layer. This ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. Please the Gerber files at www.enpirion.com. Recommendation 3: Multiple small vias should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. It is preferred to put these vias along the edge of the GND copper closest to the +V copper. These vias connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input and output current loops. See Figure ©Enpirion 2012 all rights reserved, E&OE 05721 4. If the two vias cannot be put under CIN or COUT, then put two vias right after the capacitors next the VIN and VOUT vias. Recommendation 4: As Figure 5 shows, RA, RB, and CA have been placed on the back side to minimize the footprint. These components also need to be close to the VFB pin (see Figures 3, 4 and 5). The VFB pin is a highimpedance, sensitive node. Keep any trace connected to this node as short and thin as possible. Whenever possible, connect RB directly to the AGND pin instead of going through the GND plane. In the layout shown above, RB goes to the via next to AGND pin using a dedicated trace on layer 3 not shown here. See Gerber files at www.enpirion.com. Recommendation 5: AVIN is the power supply for the small-signal control circuits. It should be connected to the input voltage at a quiet point. In Figure 4 this connection is made at the vias just before CIN. There is an additional decoupling capacitor CAVIN for AVIN which is connected between the device pin and the GND plane. Recommendation 6: The via to the right of pin 2 underneath the device helps to minimize the parasitic inductances in the input and output loop ground connections. Recommendation 7: The top layer 1 metal under the device must not be more than shown in Figure 4. As with any switch-mode DC/DC converter, try not to run sensitive signal or control lines underneath the converter package on other layers. Recommendation 8: The VOUT sense point should be just after the last output filter capacitor. Keep the sense trace short in order to avoid noise coupling into the node. 10 September 12, 2012 www.enpirion.com Rev: C EP5348UI Recommended PCB Footprint Dimensions in mm Figure 6: EN5348UI Package PCB Footprint Package and Mechanical Figure 7 EN5348UI Package Dimensions ©Enpirion 2012 all rights reserved, E&OE 05721 11 September 12, 2012 www.enpirion.com Rev: C EP5348UI Contact Information Enpirion, Inc. Perryville III Corporate Park 53 Frontage Road, Suite 210 Hampton, NJ 08827 Phone: +1 908-894-6000 Fax: +1 908-894-6090 www.enpirion.com Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion. ©Enpirion 2012 all rights reserved, E&OE 05721 12 September 12, 2012 www.enpirion.com Rev: C