EM48AM1684VTG Revision History Revision 0.1 (Jun. 2010) - First release. - Jun. 2010 1/20 www.eorex.com EM48AM1684VTG 256Mb (4M×4Bank×16) Synchronous DRAM Features Description • Fully Synchronous to Positive Clock Edge The EM48AM1684VTG is Synchronous Dynamic • Single 3.3V ±0.3V Power Supply Random Access Memory (SDRAM) organized as • LVTTL Compatible with Multiplexed Address 4Meg words x 4 banks by 16 bits. All inputs and • Programmable Burst Length (B/L) - 1, 2, 4, 8 outputs are synchronized with the positive edge of or Full Page the clock. • Programmable CAS Latency (C/L) - 2 or 3 The 256Mb SDRAM uses synchronized pipelined • Data Mask (DQM) for Read / Write Masking architecture to achieve high speed data transfer • Programmable Wrap Sequence rates and is designed to operate at 3.3V low power – Sequential (B/L = 1/2/4/8/full Page) memory system. It also provides auto refresh with – Interleave (B/L = 1/2/4/8) power saving / down mode. All inputs and outputs • Burst Read with Single-bit Write Operation • All Inputs are sampled at the Rising Edge of voltage levels are compatible with LVTTL. the Available packages: TSOPII 54P 400mil. System Clock • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms (7.8us) Ordering Information Part No Organization Max. Freq Package EM48AM1684VTG-6F 16M X 16 166MHz @CL3 54pin TSOP(ll) Commercial Free EM48AM1684VTG-7F 16M X 16 143MHz @CL3 54pin TSOP(ll) Commercial Free EM48AM1684VTG-75F 16M X 16 133MHz @CL3 54pin TSOP(II) Commerical Free EM48AM1684VTG-6FE 16M X 16 166MHz @CL3 54pin TSOP(ll) Extended Free EM48AM1684VTG-7FE 16M X 16 143MHz @CL3 54pin TSOP(ll) Extended Free EM48AM1684VTG-75FE 16M X 16 133MHz @CL3 54pin TSOP(II) Extended Free Jun. 2010 2/20 Grade Pb www.eorex.com EM48AM1684VTG Parts Naming Rules * EOREX reserves the right to change products or specification without notice. Jun. 2010 3/20 www.eorex.com EM48AM1684VTG Pin Assignment 54pin TSOP-II Jun. 2010 4/20 www.eorex.com EM48AM1684VTG Pin Description (Simplified) Pin Name Function 38 CLK 19 /CS 37 CKE 23~26, 22, 29~36 A0~A12 20, 21 BA0, BA1 18 /RAS 17 /CAS 16 /WE 39/15 UDQM/LDQM (System Clock) Master clock input (Active on the positive rising edge) (Chip Select) Selects chip when active (Clock Enable) Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. (Address) Row address (A0 to A12) is determined by A0 to A12 level at the bank active command cycle CLK rising edge. CA (CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10= High at the pre-charge command cycle, all banks are pre-charged. But when A10= Low at the pre-charge command cycle, only the bank that is selected by BA0/BA1 is pre-charged. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output Mask) DQM controls I/O buffers. (Data Input/Output) DQ pins have the same function as I/O pins on a conventional DRAM. (Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection) This pin is recommended to be left No Connection on the device. 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 1,14,27/ 28,41,54 3, 9, 43, 49/ 6, 12, 46, 52 40 Jun. 2010 DQ0~DQ15 VDD/VSS VDDQ/VSSQ NC 5/20 www.eorex.com EM48AM1684VTG Absolute Maximum Rating Symbol Item Rating Units VIN, VOUT Input, Output Voltage -0.3 ~ Vcc±0.3 V VDD, VDDQ Power Supply Voltage -0.3 ~ +4.6 Commercial 0 ~ +70 Extended -25 ~ +85 -55 ~ +150 V °C 1 W TOP Operating Temperature Range TSTG Storage Temperature Range PD Power Dissipation °C IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (VCC=3.3V, f=1MHz, TA=25°C) Symbol Parameter Min. Typ. Max. Units CCLK Clock Capacitance Input Capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU Input/Output Capacitance - - 4 pF - - 6.5 pF - - 6.5 pF Max. Units CI CO Recommended DC Operating Conditions (TA=-25°C ~85°C) Symbol Parameter Min. Typ. VDD Power Supply Voltage 3.0 3.3 3.6 V VDDQ Power Supply Voltage (for I/O Buffer) 3.0 3.3 3.6 V VIH Input Logic High Voltage 2.0 - VCC+0.3 V VIL Input Logic Low Voltage -0.3 - 0.8 V Note: * All voltages referred to VSS. * VIH may overshoot to VCC + 2.0 V for pulse width of < 4ns with 3.3V. VIL may undershoot to -2.0V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. Jun. 2010 6/20 www.eorex.com EM48AM1684VTG Recommended DC Operating Conditions (VDD=3.3V±0.3V, TA=0°C ~70°C) Symbol Parameter ICC1 Operating Current ICC2P (Note 1) Precharge Standby Current in Power Down Mode ICC2PS ICC2N Precharge Standby Current in Non-power Down Mode CKE≥VIL(min.), /CS=VIH ICC2NS No Operating Current tCK=min. /CS=VIH(min.) 4banks active ICC3P ICC3N Max. Test Conditions ICC4 Operating Current (Burst (Note 2) Mode) ICC5 Auto Refresh Current ICC6 Self Refresh Current, CKE≤0.2V (Note 3) Units -6 -7 Burst length=1, one bank tRC≥tRC(min.), IOL=0mA, One bank active 110 110 mA CKE≤VIL(max.), tCK=min. 12 12 mA CKE≤VIL(max.), tCK= ∞ 5 5 mA tCK=min. 38 38 mA tCK= ∞ 28 28 mA CKE≤VIL(max.), power down mode 35 35 mA CKE≥VIL(min.) 65 65 mA tCCD≥2CLKs, IOL=0mA 105 100 mA tCK=min. 150 140 mA Standard 6 6 mA 1.2 1.2 mA Low Power *All voltages referenced to VSS. Note 1: ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Input signals are changed only one time during tCK (min.) Recommended DC Operating Conditions (Continued) Symbol Parameter Test Conditions Min. Typ. Max. Units -10 - +10 uA Output Leakage Current 0≤VI≤VDDQ, VDDQ=VDD All other pins not under test=0V 0≤VO≤VDDQ, DOUT is disabled -10 - +10 uA VOH High Level Output Voltage IO=-4mA 2.4 - - V VOL Low Level Output Voltage IO=+4mA - - 0.4 V IIL Input Leakage Current IOL Jun. 2010 7/20 www.eorex.com EM48AM1684VTG Block Diagram Jun. 2010 8/20 www.eorex.com EM48AM1684VTG AC Operating Test Conditions (VDD=3.3V±0.3V, TA=0°C ~70°C) Item Conditions Output Reference Level 1.4V/1.4V Output Load See diagram as below Input Signal Level 2.4V/0.4V Transition Time of Input Signals 2ns Input Reference Level 1.4V AC Operating Test Characteristics (VDD=3.3V±0.3V, TA=0°C ~70°C) Symbol -6 Parameter -7 CL=3 Min. 6 Max.. - Min. 7 Max. - CL=2 7.5 - 10 - CL=3 - 5.4 - 5.4 CL=2 - 5.4 - 6 Units tCK Clock Cycle Time tAC Access Time form CLK tCH CLK High Level Width 2 - 2.5 - ns tCL CLK Low Level Width 2 - 2.5 - ns tOH Data-out Hold Time CL=3 2.5 - 2.5 - CL=2 - - - - tHZ Data-out High Impedance (Note 5) Time CL=3 3 7 3 7 CL=2 - - - - tLZ Data-out Low Impedance Time 1 - 1 - ns tHZ Data-out High Impedance Time 3 6 3 7 ns tIH Input Hold Time 1 - 1 - ns tIS Input Setup Time 1.5 - 1.5 - ns 2 CLK 2 ns ns ns ns tDQZ DQM Data Out Disable Latency tRSC Mode Register Set-up Time 12 - 14 - ns tSB Power Down Mode Entry Time 0 6 0 7 ns tDS Data-in Set-up Time 1.5 - 1.5 - ns tDH Data-in Hold Time 1 - 1 - * All voltages referenced to VSS. Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. Jun. 2010 9/20 www.eorex.com EM48AM1684VTG AC Operating Test Characteristics (Continued) (VDD=3.3V±0.3V, TA=0°C ~70°C/TA=-25°C ~ +85°C for extended grade) Symbol tRC tRAS tRP -6 Parameter Min. ACTIVE to ACTIVE Command Period (Note 6) ACTIVE to PRECHARGE Command (Note 6) Period PRECHARGE to ACTIVE Command (Note 6) Period ACTIVE to READ/WRITE Delay Time -7 Max.. 60 42 Min. Max. 65 100K 45 Units ns 100K ns 18 20 ns (Note 6) 18 20 ns tRRD ACTIVE(one) to ACTIVE(another) (Note 6) Command 12 15 ns tCCD READ/WRITE Command to READ/WRITE Command 1 1 CLK tDPL Date-in to PRECHARGE Command 2 2 CLK tBDL Date-in to BURST Stop Command 1 1 CLK tROH Data-out to High Impedance from PRECHARGE Command CL=3 3 3 CL=2 2 2 tSREX Self Refresh Exit Time 1 1 CLK tWR Write Recovery Time, Auto precharge 2 2 CLK tDQW DQM Write Mask Latency 0 0 CLK tREF Refresh Time (8,192 cycle) tRCD 64 CLK 64 ms * All voltages referenced to VSS. Note 6: These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole number) Jun. 2010 10/20 www.eorex.com EM48AM1684VTG Recommended Power On and Initialization The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD + 0.3V on any of the input pins or VDD supplies. (CLK signal started at same time) After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required, and these may be done before or after programming the Mode Register. Jun. 2010 11/20 www.eorex.com EM48AMM1684VTG Simplified State Diagram Jun. 2010 12/20 www.eorex.com EM48AMM1684VTG Address Input for Mode Register Set BA1 BA0 A11/12 A10 A9 A8 A7 A6 Operation Mode A5 A4 A3 Cas Latency BT Burst Type Interleave Sequential BA1 0 0 Jun. 2010 BA0 0 0 A12/A11 0 0 A10 0 0 A9 0 1 A8 0 0 13/20 A6 0 0 0 0 1 1 1 1 A7 0 0 A1 A0 Burst Length Burst Length Interleave A2 1 0 2 0 4 0 8 0 Reserved 1 Reserved 1 Reserved 1 Reserved 1 Sequential 1 2 4 8 Reserved Reserved Reserved Full Page CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved A2 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 A3 1 0 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Operation Mode Burst READ/Burst WRITE Burst READ/Single WRITE www.eorex.com EM48AMM1684VTG Burst Type ( A3 ) Burst Length A2 A1 A0 2 X X X X 4 X X X X 8 Full Page * Sequential Addressing Interleave Addressing 0 0 01 10 01 10 0 0 1 1 0 1 0 1 0123 1230 2301 3012 0123 1032 2301 3210 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 n n n Cn Cn+1 Cn+2 …... - * Page length is a function of I/O organization and column addressing x16 (CA0 ~ CA8): Full page = 512bits 1. Command Truth Table CKE Command Ignore Command Symbol DESL n-1 n H X /CS H /WE BA0, BA1 A10 A11, A9~A0 X X X X X /RAS /CAS X No operation NOP H X L H H H X X X Burst stop BSTH H X L H H L X X X Read READ H X L H L H V L V H X L H L H V H V Read with auto pre-charge READA Write Write with auto pre-charge WRIT H X L H L L V L V WRITA H X L H L L V H V Bank activate ACT H X L L H H V V V Pre-charge select bank PRE H X L L H L V L X Pre-charge all banks PALL H X L L H L X H X Mode register set MRS H X L L L L L L V * H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data input Jun. 2010 14/20 www.eorex.com EM48AMM1684VTG 2. DQM Truth Table Command CKE Symbol n-1 n /CS Data write / output enable ENB H x H Data mask / output disable MASK H x L Upper byte write enable / output enable BSTH H x L Read READ H x L Read with auto pre-charge READA H x L Write WRIT H x L Write with auto pre-charge WRITA H x L Bank activate ACT H x L Pre-charge select bank PRE H x L Pre-charge all banks PALL H x L Mode register set MRS H x L * H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data input 3. CKE Truth Table Command Command Symbol Activating Clock suspend mode entry Any Clock suspend mode Clock suspend Clock suspend mode exit CKE n-1 n H L /CS X /RAS /CAS X X /WE Addr. X X L L X X X X X L H X X X X X Idle CBR refresh command REF H H L L L H X Idle Self refresh entry SELF H L L L L H X Self refresh Self refresh exit L H L H H H X L H H X X X X Idle Power down entry H L X X X X X Power down Power down exit L H X X X X X *H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input Jun. 2010 15/20 www.eorex.com EM48AMM1684VTG 4. Operative Command Table (Note 7) Current /CS /R state Idle Row active Read Write /C /W Addr. Command X DESL Action Notes H X X X Nop or power down 8 L H H L H L X X NOP or BST Nop or power down H BA/CA/A10 READ/READA ILLEGAL 9 L H L L 9 L L H H L L H L BA, A10 PRE/PALL Nop L L L H X REF/SELF Refresh or self refresh 8 BA/CA/A10 WRIT/WRITA ILLEGAL ACT BA/RA Row activating 10 L L L L Op-Code MRS Mode register accessing H X X X X DESL Nop L H H X X L H L H BA/CA/A10 READ/READA Begin read : Determine AP 11 L H L L 11 L L H H BA/RA L L H L BA, A10 PRE/PALL Pre-charge 12 L L L H X REF/SELF ILLEGAL 10 NOP or BST Nop BA/CA/A10 WRIT/WRITA Begin write : Determine AP ACT ILLEGAL 9 L L L L Op-Code MRS ILLEGAL H X X X X DESL Continue burst to end→ Row active L H H H X NOP Continue burst to end→ Row active L H H L X BST Burst stop→ Row active L H L H BA/CA/A10 READ/READA Terminate burst, new read : Determine AP L L L L L L H H BA/RA ACT L L H L BA/A10 PRE/PALL L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL BA/CA/A10 WRIT/WRITA Terminate burst, start write : Determine AP 13 13,14 ILLEGAL 9 Terminate burst, pre-charging 10 H X X X X DESL Continue burst to end→ Write recovering L H H H X NOP Continue burst to end→ Write recovering L H H L X BST Burst stop→ Row active L H L H BA/CA/A10 READ/READA Terminate burst, start read: Determine AP 7, 8 L BA/CA/A10 WRIT/WRITA Terminate burst, new write: Determine AP 7 ILLEGAL H BA/RA ACT L L L L L H L L H L BA/A10 PRE/PALL Terminate burst, pre-charging L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL 13,14 13 9 15 H = High level, L = Low level, X = High or Low level (Don't care) Jun. 2010 16/20 www.eorex.com EM48AMM1684VTG 4. Operative Command Table (Continued) (Note 7) Current state Read with AP Write with AP Pre-charging Row activating /CS /R /C /W Addr. Command Action Notes H X X X X DESL Continue burst to end→ Pre-charging L H H H X NOP Continue burst to end→ Pre-charging L H H L X BST ILLEGAL L H L H BA/CA/A10 READ/READA ILLEGAL 9 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 9 L L H H BA/RA L L H L L L L H ACT ILLEGAL 9 BA, A10 PRE/PALL ILLEGAL 9 X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL burst to end→ Write recovering with auto pre-charge L H H H X NOP Continue burst to end→ Write recovering with auto pre-charge L H H L X BST ILLEGAL L H L H BA/CA/A10 READ/READA ILLEGAL 9 L H L L BA/CA/A10 WRIT/WRITA ILLEGAL 9 L L H H BA/RA L L H L L L L H ACT ILLEGAL 9 BA, A10 PRE/PALL ILLEGAL 9 X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H X X X X DESL Nop→ Enter idle after tRP L H H H X NOP Nop→ Enter idle after tRP L H H L X L H L H L H L L BST ILLEGAL READ/READA BA/CA/A10 ILLEGAL BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA L L H L BA, A10 ACT PRE/PALL ILLEGAL L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL 9 9 9 Nop→ Enter idle after tRP H X X X X DESL Nop→ Enter idle after tRCD L H H H X NOP L H H L Nop→ Enter idle after tRCD ILLEGAL L H L H L H L L L L H H BA/RA L L H L L L L L L L X BST BA/CA/A10 READ/READA ILLEGAL BA/CA/A10 WRIT/WRITA ILLEGAL 9 9 ILLEGAL 9,16 BA, A10 ACT PRE/PALL ILLEGAL 9 H X REF/SELF ILLEGAL L Op-Code MRS ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Jun. 2010 17/20 www.eorex.com EM48AMM1684VTG 4. Operative Command Table (Continued) (Note 7) Current state /CS /R H Write recovering X /C /W X X Addr. Command Action X DESL Nop→ Enter row active after tDPL L H H H X NOP Nop→ Enter row active after tDPL L H H L X BST Nop→ Enter row active after tDPL L H L H BA/CA/A10 READ/READA L H L L BA/CA/A10 Start read, Determine AP WRIT/WRITA New write, Determine AP L H H BA/RA ACT ILLEGAL 9 L L H L BA, A10 PRE/PALL ILLEGAL 9 L L L H X REF/SELF L L L Op-Code MRS H X X X X DESL ILLEGAL Nop→ Enter pre-charge after tDPL ILLEGAL L H H H X NOP Nop→ Enter pre-charge after tDPL L H H L X BST Nop→ Enter pre-charge after tDPL L H L H BA/CA/A10 READ/READA ILLEGAL L H L L BA/CA/A10 L L H H BA/RA ACT ILLEGAL L L H L BA, A10 PRE/PALL ILLEGAL L L L H X REF/SELF ILLEGAL L L L L Op-Code MRS ILLEGAL H WRIT/WRITA ILLEGAL X X X X DESL Nop→ Enter idle after tRC Refreshing L H H X X NOP/ BST Nop→ Enter idle after tRC L H L X X L L H X X ACT/PRE/PALL ILLEGAL REF/SELF/MRS ILLEGAL Mode Register Accessing 14 L L Write recovering with AP Notes READ/WRIT 9 9 ILLEGAL L L L X X H X X X X DESL Nop L 9,14 H H H X NOP Nop L H H L X BST ILLEGAL L H L X X READ/WRIT ILLEGAL L L X X X ACT/PRE/PALL/ ILLEGAL REF/SELF/MRS Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 7: All entries assume that CKE was active (High level) during the preceding clock cycle. Note 8: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode. All input buffers except CKE will be disabled. Note 9: Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 10: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode. All input buffers except CKE will be disabled. Note 11: Illegal if tRCD is not satisfied. Note 12: Illegal if tRAS is not satisfied. Note 13: Must satisfy burst interrupt condition. Note 14: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 15: Must mask preceding data which don't satisfy tDPL. Note 16: Illegal if tRRD is not satisfied. Jun. 2010 18/20 www.eorex.com EM48AMM1684VTG 5. Command Truth Table for CKE Current state Self refresh Self refresh recovery Power down Both banks idle CKE n-1 H n X L H /CS /R /C /W Addr. Action X X X X X INVALID, CLK (n – 1) would exit self refresh H X X X X Self refresh recovery L H L H H X X Self refresh recovery L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X Maintain self refresh H H H X X X X Idle after tRC H H L H H X X Idle after tRC H H L H L X X ILLEGAL H H L L X X X ILLEGAL H L H X X X X ILLEGAL H L L H H X X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL H X X X X X X INVALID, CLK(n-1) would exit power down L H X X X X X Exit power down→ Idle X Notes L L X X X X H H H X X X H H L H X X Refer to operations in Operative Command Table H H L L H X Refer to operations in Operative Command Table H H L L L H H H L L L L Op-Code Refer to operations in Operative Command Table H L H X X X Refer to operations in Operative Command Table H L L H X X Refer to operations in Operative Command Table H L L L H X H L L L L H Maintain power down mode Refer to operations in Operative Command Table X Refresh Refer to operations in Operative Command Table X Self refresh 17 H L L L L L Op-Code Refer to operations in Operative Command Table L X X X X X X Power down 17 H X X X X X X Refer to operations in Operative Command Table L X X X X X X Power down H Any state other than H listed above L H X X X X L X X X X H X X X X X Exit clock suspend next cycle L L X X X X X Maintain clock suspend Row active 17 Refer to operations in Operative Command Table X Begin clock suspend next cycle 18 H = High level, L = Low level, X = High or Low level (Don't care) Note 17: Self refresh can be entered only from the both banks idle state. Power down can be entered only from both banks idle or row active state. Note 18: Must be legal command as defined in Operative Command Table Jun. 2010 19/20 www.eorex.com EM48AMM1684VTG Package Description 54-Pin Plastic TSOP-II (400mil) Jun. 2010 20/20 www.eorex.com