S1R72C05*** Data Sheet Rev.1.0 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. ©SEIKO EPSON CORPORATION 2007, All rights reserved. Scope This document applies to the “S1R72C05” USB 2.0 Device Host Controller LSI. Table of Contents 1. OVERVIEW .....................................................................................................................1 2. FEATURES......................................................................................................................2 3. BLOCK DIAGRAM ..........................................................................................................3 4. FUNCTIONS....................................................................................................................4 4.1 Power Supply ................................................................................................................................4 4.2 Boundary Scan..............................................................................................................................4 4.2.1 Instructions Supported..............................................................................................................4 4.2.2 DEVICE_CODE........................................................................................................................5 4.2.3 Terminals Excluded from Boundary Scan .................................................................................5 4.3 Reset ..............................................................................................................................................5 4.3.1 Hard Reset ...............................................................................................................................5 4.3.2 Soft Reset.................................................................................................................................5 4.4 Clock ..............................................................................................................................................5 4.5 Power Management ......................................................................................................................6 4.6 CPU-I/F...........................................................................................................................................7 4.7 IDE-I/F ............................................................................................................................................7 4.8 USB Device I/F ..............................................................................................................................7 4.8.1 Speed Mode and Transfer Type................................................................................................7 4.8.2 Resources ................................................................................................................................7 4.8.2.1 Endpoint...................................................................................................................................................... 7 4.8.2.2 FIFO............................................................................................................................................................ 7 4.8.3 Data Flow .................................................................................................................................7 4.8.4 USB Device Port External Circuits............................................................................................9 4.9 USB Host I/F ..................................................................................................................................9 4.9.1 Speed Mode and Transfer Type................................................................................................9 4.9.2 Resources ................................................................................................................................9 4.9.2.1 Channel....................................................................................................................................................... 9 4.9.2.2 FIFO............................................................................................................................................................ 9 4.9.3 Data Flow .................................................................................................................................9 4.9.4 USB Host Port External Circuits ............................................................................................. 11 4.10 FIFO............................................................................................................................................ 11 4.10.1 USB FIFO ............................................................................................................................. 11 4.10.2 Media FIFO........................................................................................................................... 11 5. TERMINAL LAYOUT DIAGRAMS ................................................................................12 6. TERMINAL FUNCTIONS ..............................................................................................14 7. ELECTRICAL CHARACTERISTICS .............................................................................17 7.1 Absolute Maximum Ratings .......................................................................................................17 7.2 Recommended Operating Conditions.......................................................................................17 7.3 DC Characteristics......................................................................................................................18 7.3.1 Current Consumption .............................................................................................................18 7.3.2 Input Characteristics...............................................................................................................20 7.3.3 Output Characteristics ............................................................................................................21 7.3.4 Terminal Capacitance .............................................................................................................22 7.4 AC Characteristics ......................................................................................................................22 7.4.1 Reset Timing...........................................................................................................................22 S1R72C05*** Data Sheet (Rev.1.00) EPSON i 7.4.2 Clock Timing ...........................................................................................................................22 7.4.3 CPU/DMA I/F Access Timing ..................................................................................................23 7.4.3.1 Specifications for CVDD = 1.65 V to 3.6 V ................................................................................................ 23 7.4.3.2 Specifications When Limited to CVDD = 3.0 V to 3.6 V ............................................................................ 24 7.4.4 IDE I/F Timing.........................................................................................................................25 7.4.4.1 PIO Read Timing....................................................................................................................................... 25 7.4.4.2 PIO Write Timing ....................................................................................................................................... 26 7.4.4.3 DMA Read Timing ..................................................................................................................................... 27 7.4.4.4 DMA Write Timing ..................................................................................................................................... 28 7.4.4.5 Ultra DMA Read Timing............................................................................................................................. 29 7.4.4.6 Ultra DMA Write Timing............................................................................................................................. 31 7.4.5 USB I/F Timing .......................................................................................................................32 8. CONNECTION EXAMPLES ..........................................................................................33 8.1 CPU I/F Connection Example.....................................................................................................33 8.2 USB I/F Connection Example.....................................................................................................34 8.2.1 For QFP15-128 (Device Periphery) ........................................................................................34 8.2.2 For QFP15-128 (Host Periphery)............................................................................................35 8.2.3 For PFBGA8UX121/PFBGA10UX121 (Device Periphery) .....................................................36 8.2.4 For PFBGA8UX121/PFBGA10UX121 (Host Periphery) .........................................................37 9. PRODUCT CODES .......................................................................................................38 10. EXTERNAL DIMENSION DIAGRAMS........................................................................39 ii EPSON S1R72C05*** Data Sheet (Rev.1.00) 1. OVERVIEW 1. OVERVIEW The S1R72C05** is a USB host and device controller LSI that supports USB 2.0 high-speed mode. Separate host and device ports are provided to allow use as a USB host or USB device, depending on how control is switched. An IDE I/F is also provided, making it ideal for mobile or car-mounted electronic devices with built-in HDDs. S1R72C05*** Data Sheet (Rev.1.00) EPSON 1 2. FEATURES 2. FEATURES <<USB 2.0 device functions>> • HS (480 Mbps) and FS (12 Mbps) transfer support • Built-in FS/HS termination (no external circuits required) • VBUS 5V I/F (requires external protection circuit) • Support for control, bulk, interrupt, and isochronous transfers • Support for bulk, interrupt, isochronous transfer endpoints x5 and endpoint 0 <<USB 2.0 host functions>> • Support for HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) transfers • Built-in pull-down resistor for downstream port (no external circuit required) • Built-in HS termination (no external circuit required) • Support for control, bulk, interrupt, and isochronous transfers Channel architecture Dedicated control transfer channel x1 Dedicated bulk transfer channel x1 Bulk, interrupt, and isochronous transfer channels x4 • USB power switch interface <<Media data transfer functions>> • Media FIFO independent of USB allows data transfer between IDE and CPU. <<CPU I/F>> • Supports 16-bit width standard CPU I/F • Includes DMA 2ch. (Multi-word procedure) • Big Endian (Includes bus swapping function to support Little Endian CPUs) • I/F variable voltage (3.3 V to 1.8 V) <<IDE I/F>> • Supports ATA/ATAPI6 PIO mode 0 to 4, Multi-word DMA, UDMA mode 0 to 5 <<Miscellaneous>> • Clock input: Supports 12 MHz or 24 MHz quartz oscillator. (Built-in oscillator circuit and 1 MΩ feedback resistor) • Power supply voltage: 3-voltage system, featuring 3.3 V, 1.8 V, and CPU I/F power supply (3.3 V to 1.8 V) • Supports Boundary-Scan • Package type: QFP15-128, PFBGA8UX121, PFBGA10UX121 • Guaranteed operating temperature range: -40°C to 85°C 2 EPSON S1R72C05*** Data Sheet (Rev.1.00) 3. BLOCK DIAGRAM 3. BLOCK DIAGRAM XINT XCS CA[8:1] XRD XBEL XWRH/XBEH XWRL XDREQ0 XDACK0 XDREQ1 XDACK1 CD[15:0] CPU I/F Controller DMA Controller VBUSEN_A VBUSFLG_A HDD[15:0] HDMARQ XHDMACK XHIOR XHIOW XHCS[1:0] HDA[2:0] HIORDY HINTRQ XHRESET XHDASP XHPDIAG DP_A DM_A Host SIE HTM R1_A IDE Master Controller Device SIE DTM DP_B DM_B VBUS_B R1_B 60MHz Media OSC & PLL60 XI XO Channel/Endpoint Media FIFO USB FIFO Test Mux TMS TRST TCK TDO TDI TEST XRESET Fig.3.1 Overall block diagram S1R72C05*** Data Sheet (Rev.1.00) EPSON 3 4. FUNCTIONS 4. FUNCTIONS 4.1 Power Supply This LSI has three power supply circuits and a common ground. The power supply circuits consist of HVDD (3.3 V) for USB I/O, IDE I/O, and TEST I/O; CVDD (3.3 V to 1.8 V) for CPU I/F I/O; and LVDD (1.8 V) for internal circuits. (See Fig.4.1) CPU I O CPU -I/F LVDD HVDD 1.8V 3.3V H_SIE HTM D_SIE DTM USB FIFO IDE -I/F IO TEST IO CVDD 1.8V to 3.3V IDE Fig.4.1 S1R72C05 power supplies Given below are the sequences for turning the power supplies on and off. This LSI will not operate with only some of the power supplies turned on or off. The following restrictions apply to the sequence for turning the CVDD/HVDD I/O power supplies and LVDD internal power supply on or off. There are no restrictions on the sequence for turning the CVDD and HVDD power supplies on or off. • The LVDD must be turned on before turning on the CVDD and HVDD power supplies. • The CVDD and HVDD power supplies must be turned off before turning off the LVDD. If adherence to this sequence is not possible for reasons related to power supply circuit characteristics or load, the CVDD or HVDD must be on for no longer than 1 second while the LVDD is off. 4.2 Boundary Scan Boundary scanning (JTAG) may be used when the TEST terminal is set to “Low” (default). Boundary scanning consists of a BSR (Boundary Scan Register) conforming to the JTAG (IEEE 1149.1) specifications, a connecting scan path, and a TAP controller. Boundary scan connection information may be provided in BSDL format. 4.2.1 Instructions Supported This LSI has a JTAG instruction bit width of 4 bits and supports the following JTAG instructions. 4 EPSON S1R72C05*** Data Sheet (Rev.1.00) 4. FUNCTIONS Table 4.1 JTAG instruction codes Instruction Description Code SAMPLE/PRELOAD Loads LSI internal status to BSR and sets data. 0010 BYPASS Bypasses the scan path using BSR. 1111 EXTEST Physical device connection check. 0000 CLAMP Bypasses the scan path while maintaining output values. 0011 HIGHZ Sets all outputs to Hi-Z. 0100 IDCODE Outputs the specified DEVICE_CODE. 0001 4.2.2 DEVICE_CODE The DEVICE_CODE corresponding to an IDCODE instruction is composed of the following elements. Table 4.2 DEVICE_CODE Version 1 Part Number 0x0015 Manufacturer 0x0BE The DEVICE_CODE response for an IDCODE instruction will therefore be 0001_0000000000010101_ 00010111110_1. 4.2.3 Terminals Excluded from Boundary Scan The following terminals do not include boundary scan cells and are therefore excluded from boundary scanning in this LSI: DP_A, DM_A, DP_B, DM_B, R1_A, R1_B, XI, XO, VBUS_B, and TEST. 4.3 Reset This LSI includes a hard reset function via the external XRESET terminal and soft reset function via register settings. 4.3.1 Hard Reset Start from reset status when power is turned on, then cancel the reset after confirming power on. 4.3.2 Soft Reset All LSI circuits can be reset via software, or internal USB analog macros can be reset individually. The ChipReset.AllReset bit is used to reset all circuits in this LSI, or the D_Reset.ResetDTM or H_Reset.ResetHTM bits are used to reset the respective device analog macro or host analog macro. However, note that the analog macro should be reset only in the SLEEP state. 4.4 Clock This LSI contains an internal oscillator and feedback resistor (1 MΩ) and supports clock generation using an external resonator. The oscillator frequency can be set to 12 MHz or 24 MHz via the register settings. Fig.4.2 shows a typical connection arrangement for an oscillator circuit. Cd, Cg, and Rd in the oscillator circuit must be matched based on the resonator. Contact the resonator manufacturer to obtain circuit constants. S1R72C05*** Data Sheet (Rev.1.00) EPSON 5 4. FUNCTIONS Cd Cg Rd XO XI Fig.4.2 Clock generation via the internal oscillator and external resonator 4.5 Power Management This LSI includes a power management function that features six power management states: SLEEP, SNOOZE, ACTIVE60, ACT_DEVICE, ACT_HOST, and ACT_ALL. (See Fig.4.3) All function blocks are active in the ACT_ALL state (although the USB host function and USB device function cannot be used simultaneously). In the SLEEP state, however, only the circuits necessary for restarting from standby mode are active. Intermediate power management states exist between ACT_ALL and SLEEP, depending on the required activation status. ACT _ ALL ACT _ HOST ACT _ DEVICE ACTIVE 60 SNOOZE SLEEP CPU -I/F FIFO OSC PLL CPU -I/F FIFO OSC PLL CPU -I/F FIFO OSC PLL CPU -I/F FIFO OSC PLL CPU -I/F* FIFO OSC PLL CPU -I/F* FIFO OSC PLL Active H_SIE HTM D_SIE DTM IDE-I/F H_SIE HTM D_SIE DTM IDE-I/F H_SIE HTM D_SIE DTM IDE-I/F H_SIE HTM D_SIE DTM IDE-I/F H_SIE HTM D_SIE DTM IDE-I/F H_SIE HTM D_SIE DTM IDE-I/F Inactive *The CPU-I/ F is only partially active in the SLEEP and SNOOZE states, allowing access to the asynchronous access register. Fig.4.3 Power management states 6 EPSON S1R72C05*** Data Sheet (Rev.1.00) 4. FUNCTIONS 4.6 CPU-I/F This LSI is connected to the CPU via a 16-bit interface. Endian settings can be set as Big Endian or Little Endian in 16-bit steps. For Big Endian, registers with even addresses can be accessed above the bus (CD[15:8]), while registers with odd addresses can be accessed below the bus (CD[7:0]). For Little Endian, registers with even addresses can be accessed below the bus (CD[7:0]), while registers with odd addresses can be accessed above the bus (CD[15:8]). The bus mode can be set to either Strobe mode for accessing using high/low strobe (XWRH/XWRL) or Byte Enable mode for accessing using high/low byte enable (XBEH/XBEL) for writing in 8-bit. Endian and bus mode are set by the CPUIF_MODE register immediately after resetting. The CPU-I/F on this LSI includes 2-ch DMA (slave). The registers that are accessible will depend on the power management state. For detailed information, refer to the LSI Technical Manual. 4.7 IDE-I/F This LSI includes an IDE host function supporting ATA/ATAPI6, which supports PIO modes 0 to 4, Multi Word DMA, and UDMA modes 0 to 5 transfer modes. 4.8 USB Device I/F This LSI supports high-speed specification USB device functions that comply with USB 2.0 (Universal Serial Bus Specification Revision 2.0) standards. 4.8.1 Speed Mode and Transfer Type This LSI supports HS (480 Mbps) and FS (12 Mbps) speed modes when operating USB devices. The speed mode is automatically set by the speed negotiations performed when the bus is reset. For example, HS transfer mode will be selected automatically by speed negotiations if connected to a USB host that supports HS speed mode. (Note that FS speed mode can be set deliberately via register settings.) All transfer types stipulated in the USB 2.0 standard are supported, including control transfer (endpoint 0), bulk, interrupt, and isochronous transfers. 4.8.2 Resources 4.8.2.1 Endpoint This LSI includes endpoint 0 and five standard endpoints. Endpoint 0 supports control transfer. The standard endpoints support bulk, interrupt, and isochronous transfers. The standard endpoint numbers, maximum packet size, and transfer direction (IN/OUT) can be set as desired. 4.8.2.2 FIFO This LSI includes 4.5 kB of FIFO for use with USB data transfer. This forms the data transfer route with USB. The FIFO capacity for each endpoint can be assigned as desired through software. For example, performance can be improved by assigning an adequate FIFO area to the endpoints for bulk transfers. 4.8.3 Data Flow Endpoints are assigned to USB FIFO areas on a one-to-one basis. Responses are returned to USB transactions automatically, depending on the USB FIFO effective free capacity (for OUT transfer) or effective data quantity (for IN transfer). Thus, the software need not be directly involved in individual transactions, allowing USB data S1R72C05*** Data Sheet (Rev.1.00) EPSON 7 4. FUNCTIONS transfers to be controlled as data flow on the USB FIFO. CPU USB FIFO Write Read Endpoint USB Host Data quantity < MaxPktSize FIFO_Empty Write IN token IN transaction (NAK response) NAK handshake Data quantity >= MaxPktSize FIFO_Full IN token DATA packet ACK handshake Transfer sent FIFO_Empty Write IN transaction (Data reply) Data quantity < MaxPktSize IN token IN transaction (NAK response) NAK handshake Data quantity >= MaxPktSize FIFO_Full IN token IN transaction (Data reply) DATA packet Empty ACK handshake Data Fig.4.4 Typical data flow (with FIFO assigned for MaxPktSize and IN transfer) CPU USB FIFO Read Write Endpoint Free quantity >= MaxPktSize FIFO_Empty USB Host PING token ACK handshake PING transaction (ACK response) OUT token DATA packet Transfer received NYET handshak Free quantity < MaxPktSize PING token e OUT transaction (Data receipt) FIFO_Full Read NAK handshake Free quantity >= MaxPktSize FIFO_Empty PING token ACK handshake Empty PING transaction (NAK response) PING transaction (ACK response) Data Note: PING transactions are performed only in High Speed mode. Fig.4.5 Typical data flow (with FIFO assigned for MaxPktSize and OUT transfer) 8 EPSON S1R72C05*** Data Sheet (Rev.1.00) 4. FUNCTIONS 4.8.4 USB Device Port External Circuits This LSI has internal FS and HS device termination resistors, eliminating the need for additional components normally used to adjust impedance. This allows a DP/DM line to be connected between the LSI terminal and the connector. The appropriate components should be used to protect against static electricity and implement EMI precautions. The VBUS terminal uses a 5 V input and does not require external voltage conversion. However, a protection circuit is recommended since certain commercially available USB host and hub products may apply surge voltages that exceed VBUS ratings. Refer to the “PCB Design Guidelines for S1R72V Series USB 2.0 High-Speed Devices” provided separately. 4.9 USB Host I/F This LSI supports high-speed specification USB host functions that comply with USB 2.0 (Universal Serial Bus Specification Revision 2.0) standards. 4.9.1 Speed Mode and Transfer Type This LSI supports HS (480 Mbps), FS (12 Mbps) and LS (1.5 Mbps) speed modes when operating USB hosts. The speed mode is automatically set through speed negotiation performed when the bus is reset. All transfer types stipulated in the USB 2.0 standard are supported, including control, bulk, interrupt, and isochronous transfers. 4.9.2 Resources 4.9.2.1 Channel In this LSI, the setting register sets for transfers with end points on a one-to-one basis are referred to as channels. This LSI features one dedicated channel for control transfers, one dedicated channel for bulk transfers, and four general channels that support bulk, interrupt, and isochronous transfers. The endpoint number, maximum packet size, and transfer direction (in/out) can be set as desired for all channels. Transfers are also possible for a number of endpoints exceeding the number of channels using time-multiplexing for channels via software. 4.9.2.2 FIFO This LSI includes 4.5 kB of FIFO for use with USB data transfers. This forms the data transfer route with USB. The FIFO capacity for each channel can be assigned as desired via software. For example, performance can be improved by assigning a sufficient FIFO area to the channels for bulk transfers. 4.9.3 Data Flow The channels are assigned to FIFO areas on a one-to-one basis, and transactions are automatically sent via USB, depending on the FIFO effective free capacity (for IN transfers) or effective data quantity (for OUT transfers). The software need not be directly involved in individual transactions, allowing the USB data transfer to be controlled as data flow on the FIFO. S1R72C05*** Data Sheet (Rev.1.00) EPSON 9 4. FUNCTIONS CPU FIFO Read Channel USB Device Write Free quantity >= MaxPktSize FIFO_Empty IN token NAK handshake IN transaction (NAK response) IN token DATA packet Transfer received FIFO_Full Read ACK handshake IN transaction (Data reply) Free quantity < MaxPktSize Free quantity >= MaxPktSize FIFO_Empty IN token Empty NAK handshake Data IN transaction (NAK response) Fig.4.6 Typical data flow (with FIFO assigned for MaxPktSize and IN transfers) CPU FIFO Write Channel USB Device Read Data quantity < MaxPktSize FIFO_Empty Write Data quantity >= MaxPktSize FIFO_Full OUT token DATA packet Transfer sent FIFO_Empty Write OUT transaction ACK handshake Data quantity < MaxPktSize Data quantity >= MaxPktSize FIFO_Full OUT token DATA packet Empty Data Transfer sent OUT transaction ACK handshake Fig.4.7 Typical data flow (with FIFO assigned for MaxPktSize and OUT transfers) 10 EPSON S1R72C05*** Data Sheet (Rev.1.00) 4. FUNCTIONS 4.9.4 USB Host Port External Circuits This LSI features internal USB host termination resistors, including HS termination resistors, eliminating the need for the external components typically used to adjust impedance. This allows the connection of a DP/DM line between the LSI terminal and the connector. However, note that the appropriate components should be used to protect against static electricity and to implement EMI precautions. External VBUS control components are required for VBUS. 4.10 FIFO 4.10.1 USB FIFO This LSI includes 4.5 kB of USB FIFO for use with USB data transfers. This is shared between USB device I/F and USB host I/F. The USB FIFO capacity for each endpoint or channel can be assigned as desired via software. Transfers are possible between the USB-I/F and CPU-I/F via the USB FIFO or directly between the USB-I/F and IDE-I/F. 4.10.2 Media FIFO This LSI includes 64 B of Media FIFO for use with IDE data transfers. This forms the data transfer route with the IDE-I/F and CPU-I/F. Data cannot be transferred to or from the USB-I/F with Media FIFO. S1R72C05*** Data Sheet (Rev.1.00) EPSON 11 5. TERMINAL LAYOUT DIAGRAMS HVDD LVDD VSS XHRESET HDD7 HDD8 HDD6 HDD9 VSS HDD5 HDD10 HDD4 HDD11 LVDD VSS HVDD HDD3 HDD12 HDD2 HDD13 VSS HDD1 HDD14 HDD0 HVDD HDD15 HDMARQ XHIOW XHIOR HIORDY XHDMACK HINTRQ 5. TERMINAL LAYOUT DIAGRAMS 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CVDD LVDD CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 VSS CD7 CD6 CD5 VSS CVDD CD4 CD3 CD2 CD1 CD0 VSS LVDD XDACK1 XDREQ1 XDACK0 XDREQ0 XINT VSS CVDD VSS XWRL XWRH XRD XCS CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 XBEL XRESET CVDD VSS LVDD N.C. VSS LVDD VBUS_B HVDD 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DP_B 8 VSS VSS 7 DM_B LVDD 5 6 HVDD 4 VSS 3 VSS 2 R1_B 1 XO S1R72C05F00Axxx QFP15-128 VSS HDA1 XHPDIAG HDA0 LVDD VSS HVDD HDA2 XHCS0 XHCS1 XHDASP VBUSFLG_A VBUSEN_A LVDD VSS R1_A VSS HVDD DM_A VSS DP_A HVDD LVDD VSS TEST TDO TCK HVDD TMS TDI TRST LVDD XI Fig.5.1 QFP package terminal layout diagram 12 EPSON S1R72C05*** Data Sheet (Rev.1.00) 5. TERMINAL LAYOUT DIAGRAMS S1R72C05/PFBGA8UX121,PFBGA10UX121 TOP View 1 2 3 4 5 6 7 8 9 10 11 NC XI LVDD LVDD DP_A DM_A HVDD R1_A LVDD HDA0 NC XO VSS TRST VSS HVDD VSS VBUSEN_A VSS VSS HDA2 XHPDIAG LVDD VSS TDI TCK TEST XHCS0 VBUSFLG_A VSS XHCS1 HDA1 HINTRQ R1_B VSS TDO XHDASP HVDD XHDMACK HIORDY XHIOW XHIOR HDD0 HDMARQ HVDD TMS VSS LVDD VSS HDD14 HDD15 HDD12 VSS HDD2 HDD13 DM_B VSS VSS CA2 VSS LVDD HDD3 VSS HDD1 VSS HVDD DP_B HVDD VBUS_B CA3 XINT XDACK1 HVDD HDD11 HDD5 HDD10 HDD4 LVDD VSS CVDD CA4 XDACK0 CD3 CD6 CVDD CD13 HDD8 HDD9 LVDD XRESET CA1 XBEL XDREQ1 CD0 CD4 CD7 CD10 HDD6 HDD7 CA8 XCS CA5 CA6 CA7 CD1 CD5 CD9 CD12 CD14 XHRESET NC XRD XWRH XWRL XDREQ0 CD2 CVDD CD8 CD11 CD15 NC 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L Fig.5.2 BGA package terminal layout diagram S1R72C05*** Data Sheet (Rev.1.00) EPSON 13 6. TERMINAL FUNCTIONS 6. TERMINAL FUNCTIONS OSC Pin Ball Name I/O RESET Terminal type Terminal description 128 A2 XI IN - Analog Internal oscillator circuit input (12 MHz, 24 MHz) 1 B1 XO OUT - Analog Internal oscillator circuit output I/O RESET Terminal type TEST Pin Ball Name Terminal description 120 C5 TEST IN - - 121 D3 TDO OUT Hi-Z 2mA Boundary scan TDO terminal 122 C4 TCK IN - - Boundary scan TCK terminal 124 E2 TMS IN - - Boundary scan TMS terminal 125 C3 TDI IN - - Boundary scan TDI terminal 126 B3 TRST IN - - Boundary scan TRST terminal Test terminal (Must be fixed at Low) If the boundary scan function is not used, the TEST, TCK, TMS, TDI, and TRST terminals should all be set to Low and the TDO terminal left open. PD: Pull Down PU: Pull Up USB Pin Ball Name I/O RESET Terminal type Terminal description 111 A8 R1_A IN - Analog Internal operation reference current setting terminal (Connect 6.2 kΩ ±1% resistance between VSS) 116 A5 DP_A BI Hi-Z Analog USB host data line (Data +) 114 A6 DM_A BI Hi-Z Analog USB host data line (Data -) 107 C7 VBUSFLG_A IN (PU) Schmitt (PU) USB power switch fault detection signal (1: Normal, 0: Error) 108 B7 VBUSEN_A OUT Lo 2mA USB power switch control signal 5 D1 R1_B IN - Analog Internal operation reference current setting terminal (Connect 6.2 kΩ ±1% resistance between VSS) 11 G1 DP_B BI Hi-Z Analog USB device data line (Data +) 9 F1 DM_B BI Hi-Z Analog 13 G3 VBUS_B IN (PD) (PD) USB device data line (Data -) USB device bus detection signal PD: Pull Down PU: Pull Up 14 EPSON S1R72C05*** Data Sheet (Rev.1.00) 6. TERMINAL FUNCTIONS CPU I/F Pin Ball Name I/O RESET Terminal type 20 31 J2 L2 XRESET XRD IN IN - Bus Mode ⇒ - 33 L4 XWRL (XWR) IN - - 32 30 L3 K2 XWRH (XBEH) XCS IN IN - 37 G5 XINT OUT High 38 39 40 41 L5 H5 J5 G6 XDREQ0 XDACK0 XDREQ1 XDACK1 OUT IN OUT IN High High - 2mA (Tri-state) 2mA 21 J4 XBEL IN - - 22 23 24 J3 F4 G4 CA1 CA2 CA3 IN IN IN - - 25 26 27 28 29 44 45 46 47 48 51 H4 K3 K4 K5 K1 J6 K6 L6 H6 J7 K7 CA4 CA5 CA6 CA7 CA8 CD0 CD1 CD2 CD3 CD4 CD5 IN IN IN IN IN BI BI BI BI BI BI Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2mA 2mA 2mA 2mA 2mA 2mA 52 53 55 56 57 58 59 60 61 62 H7 J8 L8 K8 J9 L9 K9 H9 K10 L10 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD13 CD14 CD15 BI BI BI BI BI BI BI BI BI BI Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA 2mA Terminal description 16bit Strobe mode Write strobe (lower) 16bit BE mode Reset signal Read strobe Write strobe Write strobe (upper) High-byte enable Chip select signal Interrupt signal DMA0 request DMA0 acknowledge DMA1 request DMA1 acknowledge 2mA - Must be fixed at High or Low Low-byte enable CPU bus address CPU data bus The XINT terminal can be set to 1/0 or Hi-Z/0 mode, depending on register settings. PD: Pull Down PU: Pull Up S1R72C05*** Data Sheet (Rev.1.00) EPSON 15 6. TERMINAL FUNCTIONS IDE I/F 103 97 99 105 104 93 92 91 95 94 96 68 106 B10 C10 A10 C9 C6 D9 D8 D11 D6 D7 C11 K11 D4 HDA2 HDA1 HDA0 XHCS1 XHCS0 XHIOR XHIOW HDMARQ XHDMACK HIORDY HINTRQ XHRESET XHDASP OUT OUT OUT OUT OUT OUT OUT IN OUT IN IN OUT IN Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z (PD) Hi-Z (PU) (PD) Hi-Z (PU) Terminal type 4mA 4mA 4mA 4mA 4mA 4mA 4mA (PD) 4mA (PU) (PD) 4mA (PU) 98 90 87 84 82 77 75 72 70 69 71 74 76 81 83 86 88 B11 E7 E6 E11 E8 G8 G10 H11 H10 J11 J10 G9 G11 F7 E10 F9 D10 XHPDIAG HDD15 HDD14 HDD13 HDD12 HDD11 HDD10 HDD9 HDD8 HDD7 HDD6 HDD5 HDD4 HDD3 HDD2 HDD1 HDD0 IN BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI (PU) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z (PD) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z (PU) 4mA(PU) 4mA(PU) 4mA(PU) 4mA(PU) 4mA(PU) 4mA(PU) 4mA(PU) 4mA(PU) 4mA(PD) 4mA(PU) 4mA(PU) 4mA(PU) 4mA(PU) 4mA(PU) 4mA(PU) 4mA(PU) Pin Ball Name I/O RESET Terminal description IDE register address Control register access chip select Command block register access chip select IDE read strobe IDE write strobe DMA transfer request DMA transfer acknowledgement IDE register ready signal IDE interrupt request IDE bus reset Drive enable/slave drive available Diagnostic sequence end signal IDE data bus PU and PD can be turned on or off via register settings. PD: Pull Down PU: Pull Up Note: The IDE I/F terminals are all 5-V tolerant. POWER Pin 8, 12, 65, 80, 89, 102, 113, 117, 123 19, 35, 49, 64 3, 14, 17, 42, 63, 66, 78, 100, 109, 118, 127 2, 4, 6, 7, 10, 15, 18, 34, 36, 43, 50, 54, 67, 73, 79, 85, 101, 110, 112, 115, 119 16 16 Ball G7, D5, F11, E1, G2, B5, A7 H3, L7, H8 J1, E4, F6, H1, A3, A4 , C1, A9 F3, E3, E5, F5, C8, F8, E9, F10, H2, F2, B2, B4, B6, B8, D2, C2, B9 A1, L1, A11, L11 Name Voltage HVDD 3.3V CVDD 1.8 to 3.3 V LVDD 1.8V VSS 0V GND N.C. 0V NC terminal (connect to GND) EPSON Terminal description Power supply for IDE I/F I/O, USB I/O, and TEST I/O Power supply for CPU I/F I/O OSC I/O and internal power supply S1R72C05*** Data Sheet (Rev.1.00) 7. ELECTRICAL CHARACTERISTICS 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Item Symbol Rating Units Power supply voltage HVDD VSS - 0.3 to 4.0 V Input voltage Output voltage CVDD VSS - 0.3 to 4.0 V LVDD VSS - 0.3 to 2.5 V HVI VSS - 0.3 to HVDD + 0.5 V CVI*1 VSS - 0.3 to CVDD + 0.5 V IVI*2 VSS - 0.3 to 5.5 V VVI*3 VSS - 0.3 to 6.0 V LVI*4 VSS - 0.3 to LVDD + 0.5 V HVO VSS - 0.3 to HVDD + 0.5 V CVO*1 VSS - 0.3 to CVDD + 0.5 V Output current/terminal IOUT ±10 mA Storage temperature Tstg -65 to 150 °C *1 CPU-I/F *2 IDE-I/F *3 VBUS_B *4 XI 7.2 Recommended Operating Conditions Item Symbol Min. Typ. Max. Units Power supply voltage HVDD 3.00 3.30 3.60 V CVDD 1.65 - 3.60 V LVDD 1.65 1.80 1.95 V HVI -0.3 - HVDD+0.3 V CVI*1 -0.3 - CVDD+0.3 V IVI*2 -0.3 - 5.5 V VVI*3 -0.3 - 6.0 V LVI*4 -0.3 - LVDD+0.3 V Ta -40 25 85 °C Input voltage Ambient temperature *1 CPU-I/F *2 IDE-I/F *3 VBUS_B *4 XI Power to the IC should be turned on in the sequence shown below. LVDD (internal) → HVDD, CVDD (IO section) Likewise, power to the IC should be turned off in the sequence shown below. HVDD, CVDD (IO section) → LVDD (internal) Note: Avoid leaving the HVDD or CVDD on continuously (for more than 1 second) when the LVDD is off, since doing so may affect the chip reliability. S1R72C05*** Data Sheet (Rev.1.00) EPSON 17 7. ELECTRICAL CHARACTERISTICS 7.3 DC Characteristics 7.3.1 Current Consumption Item Power supply feed current Power supply current Stationary current Power supply current Symbol *1 Condition Min. Typ. Max. Units IDDH HVDD = 3.3V(typ), HVDD = 3.6V(max) - 41 65 mA IDDCH CVDD = 3.3V(typ), CVDD = 3.6V(max) - 1 4 mA IDDCL CVDD = 1.8V(typ), CVDD = 1.95V(max) - 0.7 2 mA IDDL LVDD = 1.8V(typ), LVDD = 1.95V(max) - 75 120 mA VIN = HVDD,CVDD,LVDD or VSS HVDD = 3.6V CVDD = 3.6V LVDD = 1.95V - - 80 µA HVDD = 3.6V CVDD = 3.6V LVDD = 1.95V HVIH = HVDD CVIH = CVDD LVIH = LVDD VIL = VSS -5 - 5 µA HVDD = 3.0V CVDD = 1.65V LVDD = 1.65V HVOH = 5.5V -10 - 10 µA *2 IDDS Input leakage Input leakage current IL Input leakage Input leakage current (5-V tolerant) *1: *2: 18 ILIF Typ values are measured with the USB-HDD connected as USB host and when transferring data between the IDE-HDD and USB-HDD (actual transfer rate 30 MB/s). Max. values are estimated from these values. Stationary current with Ta = 25°C and both terminals in input mode. EPSON S1R72C05*** Data Sheet (Rev.1.00) 7. ELECTRICAL CHARACTERISTICS Current consumption measurements for various power management states using Seiko Epson operating conditions (Ta = 25°C) Item Condition CPU bus operation *1 *2 Power supply power HVDD = 3.3V CVDD = 3.3V LVDD = 1.8V CPU bus operation *1 *2 SLEEP SNOOZE Power supply power ACTIVE60(IDE⇔CPU) Power supply power ACT_DEVICE(IDE⇔USB) Power supply power ACT_HOST(IDE⇔USB) Power supply power ACT_HOST(IDE⇔USB) Power supply power *1: *2: *3: *4: *5: *6: HVDD = 3.3V CVDD = 3.3V LVDD = 1.8V *3 HVDD = 3.3V CVDD = 3.3V LVDD = 1.8V *4 HVDD = 3.3V CVDD = 3.3V LVDD = 1.8V Copy *5 HVDD = 3.3V CVDD = 3.3V LVDD = 1.8V Direct Copy *6 HVDD = 3.3V CVDD = 3.3V LVDD = 1.8V Min. Typ. Max. Units - 0.23 - mW - 1.8 - mW - 41 - mW - 131 - mW - 134 - mW - 273 - mW When the CPU is accessing memory (e.g., SRAM or ROM) connected to the CPU bus. Excluding current consumption due to internal S1R72C05 DP pull-up resistor (approx. 200 µA). When transferring data between the IDE-HDD and CPU (actual transfer rate 4 MB/s). When connected to the PC as a USB device and when transferring data between the IDE-HDD and USB (actual transfer rate 25 MB/s). With the USB-HDD connected as USB host and when transferring data between the IDE-HDD and USB-HDD (actual transfer rate 5.3 MB/s). With the USB-HDD connected as USB host and when transferring data between the IDE-HDD and USB-HDD (actual transfer rate 30 MB/s). S1R72C05*** Data Sheet (Rev.1.00) EPSON 19 7. ELECTRICAL CHARACTERISTICS 7.3.2 Input Characteristics Item Input characteristics (LVCMOS) H-level input voltage L-level input voltage Input characteristics (LVCMOS) Condition Min. Typ. Max. Units 2.2 - - V Terminal name: TEST, TDI, TCK, TRST, TMS VIH1 HVDD = 3.6V VIL1 HVDD = 3.0V 0.8 Terminal name: CA[8:1], CD[15:0], XCS, XRD, XWRL, XWRH, XBEL, XDACK0, XDACK1, XRESET V H-level input voltage VIH2 CVDD = 3.6V 2.2 - - V L-level input voltage VIL2 CVDD = 3.0V - - 0.8 V H-level input voltage VIH3 CVDD = 1.95V 1.27 - - V L-level input voltage Input characteristics (LVCMOS) H-level input voltage L-level input voltage Schmitt input characteristics VIL3 CVDD = 1.65V 0.57 Terminal name: HDD[15:0], HDMARQ, HIORDY, HINTRQ, XHDASP, XHPDIAG V VIH4 HVDD = 3.6V 2.2 - - V VIL4 HVDD = 3.0V Terminal name: VBUSFLG_A - - 0.8 V H-level trigger voltage VT+ HVDD = 3.6V 1.4 - 2.7 V L-level trigger voltage VT- HVDD = 3.0V 0.6 - 1.8 V Hysteresis voltage HVDD = 3.0V ∆V Terminal name: DP_A, DM_A, DP_B, DM_B 0.3 - - V H-level trigger voltage VT+(USB) HVDD = 3.6V 1.1 - 1.8 V L-level trigger voltage VT-(USB) HVDD = 3.0V 1.0 - 1.5 V Hysteresis voltage HVDD = 3.0V 0.1 ∆V(USB) Terminal name: DP_A + DM_A pair, DP_B + DM_B pair - - V - - 0.2V V Schmitt input characteristics (USB FS) Input characteristics (USB FS differential) Differential input sensitivity Input characteristics (VBUS) VDS(USB) HVDD = 3.0V Differential input voltage = 0.8 V to 2.5 V Terminal name: VBUS_B H-level trigger voltage VT+(VBUS) HVDD = 3.6V 1.86 - 2.85 V L-level trigger voltage VT-(VBUS) HVDD = 3.0V 1.48 - 2.23 V Hysteresis voltage HVDD = 3.0V 0.31 0.64 V ∆V(VBUS) Terminal name: HDD[15:8], HDD[6:0], HIORDY, XHDASP, XHPDIAG, VBUSFLG_A Input characteristics Pull-up resistor Input characteristics Pull-down resistor Input characteristics Pull-down resistor 20 Symbol RPLU VIL = VSS 50 100 240 kΩ 50 100 240 kΩ 110 125 150 kΩ Terminal name: HDD[7], HDMARQ, HINTRQ RPLD VIH = HVDD Terminal name: VBUS_B RPLDV VIH = 5.0V EPSON S1R72C05*** Data Sheet (Rev.1.00) 7. ELECTRICAL CHARACTERISTICS 7.3.3 Output Characteristics Item Output characteristics Symbol Condition Min. Typ. Max. Units Terminal name: CD[15:0], XDREQ0, XDREQ1, XINT H-level output voltage VOH1 CVDD = 3.0V IOH = -2mA CVDD0.4 - - V L-level output voltage VOL1 CVDD = 3.0V IOL = 2mA - - VSS+0.4 V H-level output voltage VOH2 CVDD = 1.65V IOH = -1mA CVDD0.4 - - V L-level output voltage VOL2 Output characteristics CVDD = 1.65V VSS+0.4 V IOL = 1mA Terminal name: HDD[15:0], HDA[2:0], XHCS1, XHCS0, XHIOR, XHIOW, XHDMACK, XHRESET H-level output voltage VOH3 L-level output voltage VOL3 Output characteristics HVDD1.0 - - V - - VSS+0.4 V HVDD0.4 - - V - VSS+0.4 V 2.8 - - V VOL(USB) HVDD=3.6V Terminal name: DP_A, DM_A, DP_B, DM_B - 0.3 V 360 - - mV - - 10.0 mV HVDD = 3.0V IOL = 4mA Terminal name: TDO, VBUSEN_A H-level output voltage VOH4 L-level output voltage VOL4 Output characteristics (USB FS) H-level output voltage L-level output voltage Output characteristics (USB HS) HVDD = 3.0V IOH = -4mA HVDD = 3.0V IOH = -2mA HVDD = 3.0V IOL = 2mA Terminal name: DP_A, DM_A, DP_B, DM_B VOH(USB) HVDD=3.0V H-level output voltage VHSOH (USB) L-level output voltage VHSOL HVDD = 3.6V (USB) Terminal name: CD[15:0], XINT Output characteristics OFF-STATE leakage current Output characteristics OFF-STATE leakage current (5-V tolerant) HVDD = 3.0V IOZ HVDD = 3.6V CVDD = 1.95V -5 5 µA CVOH = CVDD VOL = VSS Terminal name: HDD[15:0], HDA[2:0], XHCS1, XHCS0, XHIOR, XHIOW, XHDMACK, XHRESET IOZHF S1R72C05*** Data Sheet (Rev.1.00) HVDD = 3.0V HVOH = 5.5V EPSON -10 - 10 µA 21 7. ELECTRICAL CHARACTERISTICS 7.3.4 Terminal Capacitance Item Symbol Condition Min. Typ. Max. Units - - 10 pF Terminal capacitance Terminal name: All input terminals Input terminal capacitance Terminal capacitance CI f = 10MHz HVDD = CVDD = LVDD = VSS Terminal name: All output terminals Output terminal capacitance Terminal capacitance CO f = 10MHz 10 HVDD = CVDD = LVDD = VSS Terminal name: All input/output terminals (except DP_A, DM_A, DP_B, DM_B) Input/output terminal capacitance 1 Terminal capacitance CIO1 Input/output terminal capacitance 2 f = 10MHz HVDD = CVDD = LVDD = VSS Terminal name: DP_A, DM_A, DP_B, DM_B CIO2 f = 10MHz HVDD = CVDD = LVDD = VSS pF - - 10 pF - - 10 pF 7.4 AC Characteristics 7.4.1 Reset Timing tRESET XRESET Code tRESET Description Reset pulse width Min. Typ. Max. Units 40 - - ns Min. Typ. Max. Units 7.4.2 Clock Timing tCYC tCYCL tCYCH XI Code 22 Description tCYC Clock cycle (ClkSelect=0) 11.999 12 12.001 MHz tCYC Clock cycle (ClkSelect=1) 23.998 24 24.002 MHz tCYCH tCYCL Clock duty 45 - 55 % EPSON S1R72C05*** Data Sheet (Rev.1.00) 7. ELECTRICAL CHARACTERISTICS 7.4.3 CPU/DMA I/F Access Timing 7.4.3.1 Specifications for CVDD = 1.65 V to 3.6 V tcas tcah CA(I) tccn tccs tcch XCS(I) trcy tras XRD(I) trng trdf Read trbh trbd trdh CD(O) Valid twcy XWRH/L(I) XWR Write twas twng twbs XBEH/L(I) twbh twah twds twdh CD(I) tdrn XDREQ0/1(O) tdaa tdan XDACK0/1(I) (CL=30pF) Code tcas tcah tccs tcch tccn trcy tras trng trbd trdf trdh trbh twcy twas twng twbs twbh twds twdh twah tdrn tdaa tdan Item Min. Typ. Max. unit Address setup time 6 - - ns Address hold time 6 - - ns XCS setup time 6 - - ns XCS hold time 6 - - ns XCS Negate time (Only when CPUIF mode is set*) 15 - - ns Read cycle 80 - - ns Read strobe assert time 40 - - ns Read strobe negate time 25 - - ns Read data output start time 1 - - ns Read data confirmation time - - 35 ns 3 - - ns Read data output delay time - - 10 ns Write cycle 80 - - ns Write strobe assert time 40 - - ns Write strobe negate time 25 - - ns Write byte enable setup time 6 - - ns Write byte enable hold time 6 - - ns - - 10 ns Write data hold time (after strobe negation) 6 - - ns Write data hold time (after strobe assertion) 50 - - ns XDREQ0/1 negate delay time - - 35 ns XDACK0/1 setup time 6 - - ns XDACK0/1 hold time 6 - - ns Read data hold time Write data acknowledge delay time * For details of CPUIF mode setting, refer to “Technical Manual.” S1R72C05*** Data Sheet (Rev.1.00) EPSON 23 7. ELECTRICAL CHARACTERISTICS 7.4.3.2 Specifications When Limited to CVDD = 3.0 V to 3.6 V tcas tcah CA(I) tccn tccs tcch XCS(I) trcy tras XRD(I) trng trdf Read trbh trbd trdh CD(O) Valid twcy XWRH/L(I) XWR Write twas twng twbs XBEH/L(I) twbh twah twds twdh CD(I) tdrn XDREQ0/1(O) tdaa tdan XDACK0/1(I) (CL=30pF) Code tcas tcah tccs tcch tccn trcy tras trng trbd trdf trdh trbh twcy twas twng twbs twbh twds twdh twah tdrn tdaa tdan Item Min. Typ. Max. unit Address setup time 6 - - ns Address hold time 6 - - ns XCS setup time 6 - - ns XCS hold time 6 - - ns XCS Negate time (Only when CPUIF mode is set*) 15 - - ns Read cycle 75 - - ns Read strobe assert time 37 - - ns Read strobe negate time 25 - - ns Read data output start time 1 - - ns Read data confirmation time - - 30 ns 3 - - ns Read data output delay time - - 10 ns Write cycle 75 - - ns Write strobe assert time 37 - - ns Write strobe negate time 25 - - ns Write byte enable setup time 6 - - ns Write byte enable hold time 6 - - ns - - 10 ns Write data hold time (after strobe negation) 6 - - ns Write data hold time (after strobe assertion) 50 - - ns XDREQ0/1 negate delay time Read data hold time Write data acknowledge delay time - - 30 ns XDACK0/1 setup time 6 - - ns XDACK0/1 hold time 6 - - ns * For details of CPUIF mode setting, refer to “Technical Manual.” 24 EPSON S1R72C05*** Data Sheet (Rev.1.00) 7. ELECTRICAL CHARACTERISTICS 7.4.4 IDE I/F Timing 7.4.4.1 PIO Read Timing DATA S1R72C05 Data transfer direction: XHCS0(O) T321 T322 HDA[2:0](O) T323 T324 T326 T325 XHIOR(O) T327 HDD[15:0](I) T328 stable stable T329 HIORDY(I) Code Description Min. Typ. Max. Units T321 XHCS0 ↓ → HDA HDA output delay time - 0 - ns T322 XHCS0 ↑ → HDA HDA hold time - 0 - ns T323 XHCS0 ↓ → XHIOR ↓ XHCS0 setup time 80 - - ns T324 XHIOR ↓ → XHIOR ↑ XHIOR assert pulse width - (AP+4) * 16.7 - 3 - ns T325 XHIOR ↑ → XHIOR ↓ XHIOR negate pulse width - (NP+4) * 16.7 + 3 - ns T326 XHIOR ↑ → XHCS0 ↑ XHCS0 hold time 50 - - ns T327 HDD → XHIOR ↑ Data setup time 10 - - ns T328 XHIOR ↑ → HDD Data hold time 0 - - ns T329 HIORDY ↑ → XHIOR ↑ XHIOR output delay time - - 25 ns *1: AP = IDE_Tmod.AssertPulseWidth, NP = IDE_Tmod.NegatePulseWidth For detailed information, refer to “IDE Transfer Mode” in the register description. S1R72C05*** Data Sheet (Rev.1.00) EPSON 25 7. ELECTRICAL CHARACTERISTICS 7.4.4.2 PIO Write Timing DATA S1R72C05 Data transfer direction XHCS0(O) T331 T332 HDA[2:0](O) T333 T334 T336 T335 XHIOW(O) T337 HDD[15:0](O) T338 valid valid T339 HIORDY(I) Code Description Min. Typ. Max. Units T331 XHCS0 ↓ → HDA HDA output delay time - 0 - ns T332 XHCS0 ↑ → HDA HDA hold time - 0 - ns T333 XHCS0 ↓ → XHIOW ↓ XHCS0 setup time 80 - - ns T334 XHIOW ↓ → XHIOW ↑ XHIOW assert pulse width - (AP+4) * 16.7 - 3 - ns T335 XHIOW ↑ → XHIOW ↓ XHIOW negate pulse width - (NP+4) * 16.7 + 3 - ns T336 XHIOW ↑ → XHCS0 ↑ XHCS0 hold time 50 - - ns T337 XHIOW ↓ → HDD Data output delay time 0 - 10 ns T338 XHIOW ↑ → HDD Data bus negate time 33 - 45 ns T339 HIORDY ↑ → XHIOW ↑ XHIOW output delay time - - 25 ns *1: AP = IDE_Tmod.AssertPulseWidth, NP = IDE_Tmod.NegatePulseWidth For detailed information, refer to “IDE Transfer Mode” in the register description. 26 EPSON S1R72C05*** Data Sheet (Rev.1.00) 7. ELECTRICAL CHARACTERISTICS 7.4.4.3 DMA Read Timing Data transfer direction: DATA S1R72C05 XHCS[1:0](O) HDA[2:0](O) T342 HDMARQ(I) T341 T344 XHDMACK(O) T343 T346 T347 T348 XHIOR(O) T345 HDD[15:0](I) Code T349 T34a stable Description stable Min. Typ. Max. Units T341 XHCS ↑, HDA → XHDMACK ↓ Address setup time 70 - - ns T342 XHIOR ↑ → XHCS ↑, HAD Address hold time 50 - - ns T343 HDMARQ ↑ → XHDMACK ↓ ↓ XHDMACK response time 17 - - ns T344 XHIOR ↓ → HDMARQ negate HDMARQ hold time 0 - - ns T345 XHDMACK ↓ → XHIOR ↓ XHDMACK setup time 0 - - ns T346 XHIOR ↓ → XHIOR ↑ XHIOR assert pulse width - (AP+4) * 16.7 - 3 - ns T347 XHIOR ↑ → XHIOR ↓ XHIOR negate pulse width - (NP+4) * 16.7 + 3 - ns T348 XHIOR ↑ → XHDMACK ↑ XHDMACK hold time 30 - 90 ns T349 HDD → XHIOR ↑ Data setup time 10 - - ns T34a XHIOR ↑ → HDD Data bus hold time 0 - - ns *1: AP = IDE_Tmod.AssertPulseWidth, NP = IDE_Tmod.NegatePulseWidth For detailed information, refer to “IDE Transfer Mode” in the register description. S1R72C05*** Data Sheet (Rev.1.00) EPSON 27 7. ELECTRICAL CHARACTERISTICS 7.4.4.4 DMA Write Timing Data transfer direction: DATA S1R72C05 XHCS[1:0](O) HDA[2:0](O) T352 HDMARQ(I) T351 T354 XHDMACK(O) T353 T356 T357 T358 XHIOW(O) T355 T359 T35a HDD[15:0](O) Code valid Description valid Min. Typ. Max. Units T351 XHCS ↑, HDA → XHDMACK ↓ Address setup time 70 - - ns T352 XHIOW ↑ → XHCS ↑, HDA Address hold time 50 - - ns T353 HDMARQ ↑ → XHDMACK ↓ XHDMACK response time 17 - - ns T354 XHIOW ↓ → HDMARQ negate HDMARQ hold time 0 - - ns T355 XHDMACK ↓ → XHIOW ↓ XHDMACK setup time 0 - - ns T356 XHIOW ↓ → XHIOW ↑ XHIOW assert pulse width - (AP+4) * 16.7 - 3 - ns T357 XHIOW ↑ → XHIOW ↓ XHIOW negate pulse width - (NP+4) * 16.7 + 3 - ns T358 XHIOW ↑ → XHDMACK ↑ XHDMACK hold time 30 - 90 ns T359 XHIOW ↓ → HDD Data output delay time 0 - 10 ns T35a XHIOW ↑ → HDD Data bus hold time 33 - 45 ns *1: AP = IDE_Tmod.AssertPulseWidth, NP = IDE_Tmod.NegatePulseWidth For detailed information, refer to “IDE Transfer Mode” in the register description. 28 EPSON S1R72C05*** Data Sheet (Rev.1.00) 7. ELECTRICAL CHARACTERISTICS 7.4.4.5 Ultra DMA Read Timing DATA S1R72C05 Data transfer direction: Initiating Host Pausing XHCS[1:0](O) HDA[2:0](O) T361 HDMARQ(I) T362 XHDMACK(O) T363 XHIOW(O) (STOP) T363 XHIOR(O) (HDMARDY) T368 HIORDY(I) (DSTROBE) T364 HDD[15:0](I) Code T365 T366 T367 stable Description T366 Min. Typ. Max. Units T361 XHCS ↑, HDA → XHDMACK ↓ Address setup time 80 - - ns T362 HDMARQ ↑ → XHDMACK ↓ XHDMACK response time 65 - - ns T363 XHDMACK ↓ → XHIOR(W) ↓ Envelope time 28 - 40 ns T364 HDD → HIORDY Data setup time 4 - - ns T365 HIORDY → HDD Data hold time 4 - - ns T366 HIORDY → HIORDY HIORDY cycle time 15 - - ns T367 HIORDY → HIORDY HIORDY cycle time x2 30 - - ns T368 XHIOR ↑ → HIORDY Final STROBE time - - S1R72C05*** Data Sheet (Rev.1.00) EPSON IDE spec. tRFS ns 29 7. ELECTRICAL CHARACTERISTICS Ultra DMA Read Timing (continued) DATA Data transfer direction: S1R72C05 CRC Host Terminating Device Terminating XHCS[1:0](O) HDA[2:0](O) T377 T377 HDMARQ(I) T373 T375 XHDMACK(O) T371 XHIOW(O) (STOP) XHIOR(O) (XHDMARDY) T37a T372 T376 HIORDY(I) (DSTROBE) T374 HDD[15:0](O) (CRC) Code 30 T37b T378 T379 T374 CRC stable Description T378 CRC stable Min. Typ. Max. Units - ns T371 XHIOR ↑ → XHIOW ↑ Time to STOP assert 180 - T372 XHIOR ↑ → HIORDY Final STROBE time - - T373 XHIOW ↑ → HDMARQ ↓ Restricted interlock time - - T374 HDMARQ ↓ → HDD Output delay time 70 T375 HDMARQ ↓ → XHDMACK ↑ Minimum interlock time T376 IDE spec. tRFS IDE spec. ns tLI ns - - ns 160 - - ns HIORDY → XHDMACK ↑ Minimum interlock time 110 - - ns T377 XHDMACK ↑ → XHCS0, 1 XHCS0, 1 hold time 35 - - ns T378 HDD(CRC) → XHDMACK ↑ CRC data setup time 75 - - ns T379 XHDMACK ↑ → HDD(CRC) CRC data hold time 12 - - ns T37a HDMARQ ↓ → XHIOR ↑ Restricted interlock time 20 - 38 ns T37b HIORDY → XHDMACK ↑ Minimum interlock time 110 - - ns EPSON T379 S1R72C05*** Data Sheet (Rev.1.00) 7. ELECTRICAL CHARACTERISTICS 7.4.4.6 Ultra DMA Write Timing Data transfer direction: DATA S1R72C05 Initiating Device Pausing XHCS[1:0](O) HDA[2:0](O) T381 HDMARQ(I) T382 XHDMACK(O) T384 T385 XHIOW(O) (STOP) T389 T389 XHIOR(O) T386 (HSTROBE) T38a HIORDY(I) T38b (XDDMARDY) T387 HDD[15:0](O) Code T388 valid Description Min. Typ. Max. Units T381 XHCS ↑, HDA → XHDMACK ↓ Address setup time 80 - - ns T382 HDMARQ ↑ → XHDMACK ↓ XHDMACK response time 65 - - ns T384 XHDMACK ↓ → XHIOW ↓ Envelope time 28 - 40 ns T385 XHIOW ↓ → HIORDY ↓ Restricted interlock time T386 IDE spec. tLI - HIORDY ↓ → XHIOR ↓ Unrestricted interlock time 20 T387 HDD → XHIOR ↓ Data setup time T388 IDE spec. tLI ns - - ns - (cyc+1) * 16.7 - ns XHIOR ↓ → HDD Data hold time - (cyc+1) * 16.7 - ns T389 XHIOR → XHIOR XHIOR cycle time - (cyc+2) * 16.7 - ns T38a XHIOR → XHIOR XHIOR cycle time x2 - T389 * 2 - ns T38b HIORDY ↑ → XHIOR Final STROBE time 20 - 38 ns *1: cyc = UltraDMAcycle For detailed information, refer to “IDE Ultra-DMA Transfer Mode” in the register description. S1R72C05*** Data Sheet (Rev.1.00) EPSON 31 7. ELECTRICAL CHARACTERISTICS 7.4.5 USB I/F Timing Conforms to USB 2.0 standard <Universal Serial Bus Specification Revision 2.0 Released on April 27, 2000>. 32 EPSON S1R72C05*** Data Sheet (Rev.1.00) 8. CONNECTION EXAMPLES 8. CONNECTION EXAMPLES 8.1 CPU I/F Connection Example Address[8:1] CA[8:1] XBEL DATA[15:0] DATA[15:0] XCS XCS XRD XRD XWRH XWRH/XBEH XWRL XWRL/XWR XDREQ0 XDREQ0 *1 *1: Open when DMA is not used XDACK0 XDACK0 *2 XDREQ1 XDREQ1 *1 *2: Fixed at inactive level when DMA is not used XDACK1 XDACK1 *2 XINT XINT 16-bit CPU (XWRH/XWRL) connection example Address[8:1] XBEL DATA[15:0] CA[8:1] XBEL DATA[15:0] XCS XCS XRD XRD XBEH XWRH/XBEH XWR XWRL/XWR XDREQ0 XDREQ0 *1 *1: Open when DMA is not used XDACK0 XDACK0 *2 XDREQ1 XDREQ1 *1 *2: Fixed at inactive level when DMA is not used XDACK1 XDACK1 *2 XINT XINT 16-bit CPU (XBEH/XBEL) connection example S1R72C05*** Data Sheet (Rev.1.00) EPSON 33 8. CONNECTION EXAMPLES 8.2 USB I/F Connection Example 8.2.1 For QFP15-128 (Device Periphery) S1R72C05 QFP15-128 Top View 1u Cd VSS DP_B HVDD VBUS_B LVDD VSS 10 12 13 14 15 11 HVDD DM_B 7 9 VSS VSS 6 8 R1_B LVDD 3 5 VSS VSS XO 1 Cg 2 128 XI 4 127 LVDD Rd 1u 6.2k ±1% 0.1u 1u 0.1u HVDD(3.3V±0.3V) LVDD(1.8V±0.15V) VSS Static protection varistor 10 Cg, Cd, Rd: As required 1u to USB B_Connector The oscillator circuit must match the quartz resonator. Contact the quartz resonator manufacturer for detailed information on circuit constants. For detailed information on USB peripheral circuits, refer to the "PCB Design Guidelines for S1R72V Series USB 2.0 High-Speed Devices." Select power supply elements carefully; their performance will affect USB signal waveform quality. 34 EPSON S1R72C05*** Data Sheet (Rev.1.00) 8. CONNECTION EXAMPLES 8.2.2 For QFP15-128 (Host Periphery) VBUS control circuit OUT FLG ENB 107 VBUSFLG_A 108 VBUSEN_A 1u to USB A_Connector 6.2k ±1% 109 LVDD 110 VSS 111 R1_A 112 VSS 0.1u 113 HVDD 114 DM_A 115 VSS 0.1u S1R72C05 QFP15-128 116 DP_A Top View 117 HVDD 118 LVDD 119 VSS Static protection varistor 1u VCC(5.0V±0.5V) HVDD(3.3V±0.3V) LVDD(1.8V±0.15V) VSS For detailed information on USB peripheral circuits, refer to the "PCB Design Guidelines for S1R72V Series USB 2.0 High-Speed Devices." The VBUS circuit is shown for reference purposes only and should not be interpreted as a recommended configuration. Select components and circuit type to suit individual system requirements. Caution is required with components using FET switches, since a current flows from the OUT terminal to the IN terminal if the OUT terminal voltage exceeds the IN terminal voltage, whether enabled or disabled by the parasitic diode between the source and drain. Select power supply elements carefully; their performance will affect USB signal waveform quality. S1R72C05*** Data Sheet (Rev.1.00) EPSON 35 8. CONNECTION EXAMPLES 8.2.3 For PFBGA8UX121/PFBGA10UX121 (Device Periphery) Cd Cg Rd 1u A2 A3 XI B1 LV DD B2 XO C1 LV DD VS S C2 VS S S1R72C05 PFBGA8UX121 PFBGA10UX121 1u D1 D2 R1_ B VS S Top View 6.2k ±1% E1 HV DD 0.1u Static protection varistor F1 F2 to USB B_Connector DM _B G2 G1 DP _B H1 0.1u VS S LV DD G3 HV DD VBU S_B H2 VS S 1u 10 1u C11, C12, Rd: As required The oscillator circuit must match the quartz resonator. Contact the quartz resonator manufacturer for detailed information on circuit constants. HVDD(3.3V±0.3V) For detailed information on USB peripheral circuits, refer to the "PCB Design Guidelines for S1R72V Series USB 2.0 High-Speed Devices." LVDD(1.8V±0.15V) VSS Select power supply elements carefully; their performance will affect USB signal waveform quality. 36 EPSON S1R72C05*** Data Sheet (Rev.1.00) 8. CONNECTION EXAMPLES 8.2.4 For PFBGA8UX121/PFBGA10UX121 (Host Periphery) to USB A_Connector OUT FLG ENB 0.1u Static protection varistor 0.1u 1u 1u 6.2k ±1% A4 A5 LV DD DP _A B4 B5 VS S HV DD A6 A7 DM _A B6 VS S HV DD B7 VBU SEN _A A8 R1_ A B8 VS S A9 LV DD B9 VS S C6 VBU SFL G_A S1R72C05 PFBGA8UX121 PFBGA10UX121 Top View For detailed information on USB peripheral circuits, refer to the "PCB Design Guidelines for S1R72V Series USB 2.0 High-Speed Devices." VCC(5.0V±0.5V) HVDD(3.3V±0.3V) LVDD(1.8V±0.15V) The VBUS circuit is shown for reference purposes only, and should not be interpreted as a recommended configuration. Select the components and circuit type to suit individual system requirements. Caution is required with components using FET switches, since a current flows from the OUT terminal to the IN terminal if the OUT terminal voltage exceeds the IN terminal voltage, whether enabled or disabled by the parasitic diode between the source and drain. VSS Select power supply elements carefully; their performance will affect USB signal waveform quality. S1R72C05*** Data Sheet (Rev.1.00) EPSON 37 9. PRODUCT CODES 9. PRODUCT CODES Table 9.1 Product codes 38 Product code S1R72C05B08**** PFBGA8UX121 package Product type S1R72C05B10**** PFBGA10UX121 package S1R72C05F15**** QFP15-128 package EPSON S1R72C05*** Data Sheet (Rev.1.00) 10. EXTERNAL DIMENSION DIAGRAMS 10. EXTERNAL DIMENSION DIAGRAMS Refer the attached diagrams on the end of this document. QFP Package(QFP15-128) BGA Package (PFBGA8UX121) BGA Package (PFBGA10UX121) S1R72C05*** Data Sheet (Rev.1.00) EPSON 39 EXTERNAL DIMENSION DIAGRAMS Revision History Description of revision Date 08/21/2007 40 Rev. Page (old issue) Classification 1.00 All pages New Description New issue EPSON S1R72C05*** Data Sheet (Rev.1.00) Top View D A1 Corner A1 A E Index Bottom View e φ ZD A1 Corner 1 2 3 4 5 6 7 8 9 10 11 D E A A1 e b x y ZD ZE Min Nom Max - 8 8 - 0.27 - - 1.2 0.22 0.65 - - 0.37 0.08 0.1 0.75 0.75 - ZE e L K J H G F E D C B A Symbol - P-TFBGA-121-0808-0.65(PFBGA8U-121) 2900-0002-01(Rev.1.1) - Top View D A1 Corner A1 A E Index Bottom View e ZD Symbol A1 Corner 1 2 3 4 5 6 7 8 9 10 11 ZE e φ L K J H G F E D C B A P-TFBGA-121-1010-0.80(PFBGA10U-121) 2900-0002-01(Rev.1.1) D E A A1 e b x y ZD ZE Min 0.38 - Nom 10 10 0.3 0.8 1 1 Max 1.2 0.48 0.08 0.1 - International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. HEADQUARTERS EPSON (CHINA) CO., LTD. 2580 Orchard Parkway San Jose , CA 95131,USA Phone: +1-800-228-3964 FAX: +1-408-922-0238 SALES OFFICES Northeast 301 Edgewater Place, Suite 210 Wakefield, MA 01880, U.S.A. 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IC International Sales Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 FAX: +81-42-587-5117 Document Code: 411234700 First Issue September 2007 H Printed in JAPAN ○