SN74LVTH322374 3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCBS754C – MARCH 2002 – REVISED NOVEMBER 2006 • FEATURES • • • • • • Member of the Texas Instruments Widebus+™ Family Output Ports Have Equivalent 22-Ω Series Resistors, So No External Resistors Are Required Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Supports Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Ioff and Power-Up 3-State Support Hot Insertion • • • • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Distributed VCC and GND Pins Minimize High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) xxx GKE OR ZKE PACKAGE (TOP VIEW) TERMINAL ASSIGNMENTS 1 2 3 4 5 6 A 1Q2 1Q1 1OE 1CLK 1D1 1D2 A B 1Q4 1Q3 GND GND 1D3 1D4 B C 1Q6 1Q5 VCC VCC 1D5 1D6 D 1Q8 1Q7 GND GND 1D7 1D8 E 2Q2 2Q1 GND GND 2D1 2D2 1 2 3 4 5 6 C D E F G F 2Q4 2Q3 VCC VCC 2D3 2D4 G 2Q6 2Q5 GND GND 2D5 2D6 H 2Q7 2Q8 2OE 2CLK 2D8 2D7 J 3Q2 3Q1 3OE 3CLK 3D1 3D2 H K 3Q4 3Q3 GND GND 3D3 3D4 J L 3Q6 3Q5 VCC VCC 3D5 3D6 K M 3Q8 3Q7 GND GND 3D7 3D8 L N 4Q2 4Q1 GND GND 4D1 4D2 M P 4Q4 4Q3 VCC VCC 4D3 4D4 N R 4Q6 4Q5 GND GND 4D5 4D6 T 4Q7 4Q8 4OE 4CLK 4D8 4D7 P R T DESCRIPTION/ORDERING INFORMATION ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) ORDERABLE PART NUMBER TOP-SIDE MARKING LFBGA – GKE Reel of 1000 SN74LVTH322374KR HW374 LFBGA – ZKE (Pb-free) Reel of 1000 74LVTH322374ZKER HW374 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2006, Texas Instruments Incorporated SN74LVTH322374 3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCBS754C – MARCH 2002 – REVISED NOVEMBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The SN74LVTH322374 is a 32-bit edge-triggered D-type flip-flop with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to reduce overshoot and undershoot. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. FUNCTION TABLE (each 8-bit flip-flop) INPUTS 2 OE LE D OUTPUT G L ↑ H H L ↑ L L L H or L X Q0 H X X Z Submit Documentation Feedback SN74LVTH322374 3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCBS754C – MARCH 2002 – REVISED NOVEMBER 2006 LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1CLK A3 2OE A4 2CLK C1 1D1 A5 A2 1D H3 H4 C1 1Q1 2D1 E5 To Seven Other Channels 3OE 3CLK J3 4OE J4 4CLK J5 2Q1 To Seven Other Channels C1 3D1 E2 1D J2 1D T3 T4 C1 3Q1 4D1 N5 To Seven Other Channels N2 1D 4Q1 To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 4.6 V VI Input voltage range (2) –0.5 7 V VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 7 V –0.5 VCC + 0.5 state (2) VO Voltage range applied to any output in the high IO Current into any output in the low state IO Current into any output in the high state (3) IIK Input clamp current VI < 0 IOK Output clamp current VO < 0 –50 mA θJA Package thermal impedance (4) GKE/ZKE package 40 °C/W Tstg Storage temperature range 150 °C (1) (2) (3) (4) –65 V 30 mA 30 mA –50 mA Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback 3 SN74LVTH322374 3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCBS754C – MARCH 2002 – REVISED NOVEMBER 2006 Recommended Operating Conditions (1) MIN MAX 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage 5.5 V IOH High-level output current –12 mA IOL Low-level output current 12 mA ∆t/∆v Input transition rise or fall rate 10 ns/V ∆t/∆VCC Power-up ramp rate 200 TA Operating free-air temperature –40 (1) V 2 V 0.8 Outputs enabled V µs/V °C 85 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) UNIT –1.2 V VCC = 2.7 V, II = –18 mA VOH VCC = 3 V, IOH = –12 mA VOL VCC = 3 V, IOL = 12 mA 0.8 VCC = 0 or 3.6 V, VI = 5.5 V 10 VCC = 3.6 V, VI = VCC or GND ±1 Control inputs II Data inputs Ioff VCC = 3.6 V VCC = 0, V VI = VCC 1 VI = 0 VI = 0.8 V VI = 2 V Data inputs VCC = 3.6 2 V, (2) V µA –5 ±100 VI or VO = 0 to 4.5 V VCC = 3 V II(hold) µA 75 –75 µA 500 –750 VI = 0 to 3.6 V 5 µA –5 µA ±100 µA IOZH VCC = 3.6 V, VO = 3 V IOZL VCC = 3.6 V, VO = 0.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don't care ±100 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high 0.38 Outputs low 10 Outputs disabled mA 0.38 ∆ICC (3) VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND CI VI = 3 V or 0 3 pF Co VO = 3 V or 0 9 pF (1) (2) (3) 4 MAX VIK 0.2 mA All typical values are at VCC = 3.3 V, TA = 25°C. This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Submit Documentation Feedback SN74LVTH322374 3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCBS754C – MARCH 2002 – REVISED NOVEMBER 2006 Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V MIN fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ VCC = 2.7 V MAX MIN 160 UNIT MAX 160 MHz 3 3 ns High or low 1.8 2 ns High or low 0.8 0.1 ns Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPZH tPZL tPHZ tPLZ (1) TYP (1) VCC = 2.7 V MAX 160 CLK Q OE Q OE Q MIN UNIT MAX 160 MHz 2 3.4 5.3 6.2 2.2 3.3 4.9 5.1 1.8 3.5 5.6 6.9 1.8 3.5 4.9 6 2.4 4.2 5.4 5.7 2 3.8 5 5.1 tsk(LH) 0.5 tsk(HL) 0.5 ns ns ns ns All typical values are at VCC = 3.3 V, TA = 25°C. Submit Documentation Feedback 5 SN74LVTH322374 3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS www.ti.com SCBS754C – MARCH 2002 – REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V Timing Input LOAD CIRCUIT 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1.5 V Output 1.5 V VOL tPHL Output Waveform 1 S1 at 6 V (see Note B) tPLH 1.5 V 1.5 V 1.5 V VOL tPZL tPLZ 3V 1.5 V Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPZH VOH Output 2.7 V Output Control VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 13-Oct-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74LVTH322374ZKER ACTIVE LFBGA ZKE 96 1000 Green (RoHS & no Sb/Br) SN74LVTH322374KR NRND LFBGA GKE 96 1000 TBD Lead/Ball Finish MSL Peak Temp (3) SNAGCU Level-3-260C-168 HR SNPB Level-2-235C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 74LVTH322374ZKER LFBGA ZKE 96 1000 330.0 24.4 5.7 13.7 2.0 8.0 24.0 Q1 SN74LVTH322374KR LFBGA GKE 96 1000 330.0 24.4 5.7 13.7 2.0 8.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74LVTH322374ZKER SN74LVTH322374KR LFBGA ZKE 96 1000 333.2 345.9 31.8 LFBGA GKE 96 1000 333.2 345.9 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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