Typical Size 3,5 mm x 7 mm TPS54917 www.ti.com ........................................................................................................................................................................................... SLVS847 – NOVEMBER 2008 3-V TO 4-V INPUT, 9-A, SMALL SYNCHRONOUS-BUCK SWITCHER WITH INTEGRATED FETs (SWIFT™) FEATURES 1 DESCRIPTION • 13-mΩ MOSFET Switches for High Efficiency at 9-A Continuous Output • Adjustable Output Voltage Down to 0.9V With 1% Accuracy • Externally Compensated for Design Flexibility • Wide PWM Frequency: Fixed 350 kHz, 550 kHz, or Adjustable 280 kHz to 1.6 MHz • Synchronizable to 1.6MHz • Load Protected by Peak Current Limit and Thermal Shutdown • Small 3.5mm x 7mm Package and Similar Layout to TPS54910 Reduces Board Area and Total Cost • SWIFT Documentation Application Notes, and SwitcherPro™ Software: www.ti.com/swift 23 As a member of the SWIFT™ family of dc/dc regulators, the TPS54917 low-input voltage high-output current synchronous buck PWM converter offers the same features as the TPS54910 in a smaller package and higher switching frequency, which allows for a smaller total solution. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that enables maximum performance under transient conditions and flexibility in choosing the output filter L and C components; an undervoltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an internally and externally set slow-start circuit to limit in-rush currents; and a power good output useful for processor/logic reset, fault signaling, and supply sequencing. The TPS54917 is available in a thermally enhanced 34 pin QFN (RUV) PowerPAD™ package, which eliminates bulky heatsinks. TI provides evaluation modules and the SwitcherPro™ design software tool to aid in achieving high-performance power supply designs to meet aggressive equipment development cycles. APPLICATIONS • • • Low-Voltage, High-Density Systems With Power Distributed at 3.3 V Point of Load Regulation for High Performance DSPs, FPGAs, ASICs, and Microprocessors Broadband, Networking and Optical Communications Infrastructure SIMPLIFIED SCHEMATIC EFFICIENCY AT 700 kHz TPS54917 VIN SS/ENA PWRGD RT SYNC PH 95 Output 90 BOOT PGND Efficiency − % Input 100 COMP VBIAS 85 80 75 70 65 AGND VSENSE 60 Compensation Network VI = 3.3 V, VO = 2.5 V 55 50 0 1 2 3 4 5 6 7 8 9 10 11 12 IO − Output Current − A 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SwitcherPro, SWIFT, PowerPAD are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated TPS54917 SLVS847 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TJ OUTPUT VOLTAGE –40°C to 125°C (1) (2) PACKAGE 0.9 V to 2.5 V QFN (RUV) PART NUMBER (2) TPS54917RUV For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. The RUV package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54917RUVR). See the application section of this data sheet for PowerPAD drawing and layout information. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE / UNIT VI VO Input voltage range Output voltage range SS/ENA, SYNC –0.3 V to 7 V RT –0.3 V to 6 V VSENSE –0.3 V to 4 V VIN –0.3 V to 4.5 V BOOT –0.3 V to 10 V VBIAS, PWRGD, COMP –0.6 V to 7 V PH –0.6 V to 6 V PH (transient < 10 ns) IO IS source current Sink current Voltage differential PH -2.0 V Internally Limited COMP, VBIAS 6 mA PH 16 A COMP 6 mA SS/ENA, PWRGD 10 mA AGND to PGND ±0.3 V TJ Operating virtual junction temperature range –40°C to 125°C Tstg Storage temperature –65°C to 150°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VI Input voltage range TJ Operating junction temperature 2 Submit Documentation Feedback NOM MAX UNIT 3 4 V –40 125 °C Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 TPS54917 www.ti.com ........................................................................................................................................................................................... SLVS847 – NOVEMBER 2008 PACKAGE DISSIPATION RATINGS (1) (2) (1) PACKAGE THERMAL IMPEDANCE JUNCTION-TO-AMBIENT THERMAL IMPEDANCE JUNCTION-TO-CASE 34-Pin RUV with solder 14.4°C/W 0.5 °C/W (2) Test board conditions: a. 3 inch × 3 inch, 4 layers, Thickness: 0.062 inch b. 2.0 oz copper traces located on the top of the PCB c. 2.0 oz copper ground plane on the bottom of the PCB d. 2.0 oz copper ground planes on the 2 internal layers e. 12 thermal vias Maximum power dissipation may be limited by overcurrent protection. ELECTRICAL CHARACTERISTICS TJ = –40°C to 125°C, VI = 3 V to 4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE, VIN VIN input voltage range Quiescent current 3 4 fs = 350 kHz, SYNC ≤ 0.8 V, RT open, PH pin open 9.8 fs = 550 kHz, SYNC ≥ 2.5 V, RT open, PH pin open 14 23 1 1.4 2.95 3 Shutdown, SS/ENA = 0 V V 17 mA UNDER VOLTAGE LOCK OUT Start threshold voltage, UVLO Stop threshold voltage, UVLO 2.7 Hysteresis voltage, UVLO Rising and falling edge deglitch, UVLO (1) 2.8 V 0.16 V 2.5 µs BIAS VOLTAGE VO Output voltage, VBIAS I(VBIAS) = 0 2.7 2.8 Output current, VBIAS (2) 2.9 V 100 µA 0.900 V CUMULATIVE REFERENCE Vref Accuracy 0.882 0.891 REGULATION Line regulation (1) Load regulation (1) IL = 4.5 A, fs = 350 kHz, TJ = 85°C 0.07 IL = 4.5 A, fs = 550 kHz, TJ = 85°C 0.07 IL = 0 A to 9 A, fs = 350 kHz, TJ = 85°C 0.03 IL = 0 A to 9 A, fs = 550 kHz, TJ = 85°C 0.03 %/V %/A OSCILLATOR Internally set free-running frequency range SYNC ≤ 0.8 V, RT open 280 350 420 SYNC ≥ 2.5 V, RT open 440 550 660 Externally set free-running frequency range RT = 100 kΩ (1% resistor to AGND) 460 500 540 RT = 27 kΩ (1% resistor to AGND) 1480 1600 1720 High-level threshold voltage, SYNC 2.5 0.8 50 Frequency range, SYNC 330 Ramp valley (1) Ramp amplitude (peak-to-peak) (1) Minimum controllable on time (1) (2) 1600 V kHz 0.75 V 1 V 160 Maximum duty cycle kHz V Low-level threshold voltage, SYNC Pulse duration, SYNC (1) kHz ns 90% Specified by design Static resistive loads only Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 3 TPS54917 SLVS847 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) TJ = –40°C to 125°C, VI = 3 V to 4 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 90 110 3 5 MAX UNIT ERROR AMPLIFIER Error amplifier open loop voltage gain Error amplifier unity gain bandwidth 1 kΩ COMP to AGND (3) Parallel 10 kΩ, 160 pF COMP to AGND Error amplifier common-mode input voltage range Powered by internal LDO IIB Input bias current, VSENSE VSENSE = Vref VO Output voltage slew rate (symmetric), COMP (3) (3) (3) 0 MHz VBIAS 60 1 dB 250 1.4 V nA V/µs PWM COMPARATOR PWM comparator propagation delay time, PWM comparator input to PH pin (excluding dead time) 10 mV overdrive (3) 70 85 ns 1.20 1.40 V SLOW-START/ENABLE Enable threshold voltage, SS/ENA 0.82 Enable hysteresis voltage, SS/ENA (3) Falling edge deglitch, SS/ENA (3) Internal slow-start time Charge current, SS/ENA SS/ENA = 0 V Discharge current, SS/ENA SS/ENA = 1.3 V, VI = 1.5 V 0.03 V 2.5 µs 2.6 3.35 4.1 3 5 8 ms µA 1.5 2.3 4 mA POWER GOOD Power good threshold voltage VSENSE falling Power good hysteresis voltage (3) Power good falling edge deglitch (3) 90 %Vref 3 %Vref 35 Output saturation voltage, PWRGD I(sink) = 2.5 mA Leakage current, PWRGD VI = 5.5 V 0.18 µs 0.3 V 1 µA CURRENT LIMIT Current limit trip point VI = 3.3 V (3), Output shorted 15 A Current limit leading edge blanking time (3) 11 100 ns Current limit total response time (3) 200 ns THERMAL SHUTDOWN Thermal shutdown trip point (3) 135 Thermal shutdown hysteresis (3) 150 165 10 °C °C OUTPUT POWER MOSFETS rDS(on) (3) 4 Power MOSFET switches VI = 3 V 13.5 26 VI = 3.6 V 12.5 24 mΩ Specified by design Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 TPS54917 www.ti.com ........................................................................................................................................................................................... SLVS847 – NOVEMBER 2008 PIN ASSIGNMENTS PGND PGND PGND 1 34 32 30 29 33 31 2 28 3 27 4 26 5 25 THERMAL PAD 6 24 7 23 8 22 9 21 10 20 11 19 17 18 RT SYNC SS/ENA VBIAS VIN VIN VIN VIN VIN PGND PGND PGND PGND 14 15 16 PGND PGND 12 13 PGND PGND AGND VSENSE COMP PWRGD BOOT PH PH PH PH PH PH PH PGND PGND RUV PACKAGE (TOP VIEW) PIN FUNCTIONS PIN DESCRIPTION NAME NO. AGND 1 Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and SYNC pin. Connect PowerPAD to AGND. BOOT 5 Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the high-side FET driver. COMP 3 Error amplifier output. Connect frequency compensation network from COMP to VSENSE. PGND 13–20 30–34 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection to AGND is recommended. PH 6–12 Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor. PWRGD 4 Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when SS/ENA is low or internal shutdown signal active. RT 29 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs. SS/ENA 27 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and capacitor input to externally set the start-up time. SYNC 28 Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be connected to the RT pin. VBIAS 26 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high quality, low ESR 0.1-µF to 1-µF ceramic capacitor. VIN VSENSE 21–25 2 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device package with a high-quality, low-ESR 10-µF ceramic capacitor. Error amplifier inverting input. Connect to output voltage compensation network/output divider. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 5 TPS54917 SLVS847 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com INTERNAL BLOCK DIAGRAM VBIAS AGND VIN Enable Comparator SS/ENA Falling Edge Deglitch 1.2 V Hysteresis: 0.03 V 2.5 ms VIN UVLO Comparator VIN 2.95 V Hysteresis: 0.16 V REG VBIAS SHUTDOWN VIN ILIM Comparator Thermal Shutdown o 150 C 3−4V Leading Edge Blanking Falling and Rising Edge Deglitch 100 ns BOOT 15 mW 2.5 ms SS_DIS SHUTDOWN Internal/External Slow-start (Internal Slow-start Time = 3.35 ms PH + − R Q Error Amplifier Reference Vref = 0.891 V S VO CO Adaptive Dead-Time PWM Comparator LOUT and Control Logic VIN 15 mW OSC PGND Powergood Comparator PWRGD VSENSE Falling Edge Deglitch 0.90 Vref TPS54917 Hysteresis: 0.03 Vref VSENSE COMP RT SHUTDOWN 35 ms SYNC RELATED DC/DC PRODUCTS • • • • 6 TPS40000 – dc/dc controller TPS56300 – dc/dc controller TPS54619 and TPS54617 – 6 A converters TPS54910 – 9 A converter Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 TPS54917 www.ti.com ........................................................................................................................................................................................... SLVS847 – NOVEMBER 2008 TYPICAL CHARACTERISTICS DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE VI = 3.3 V IO = 5 A 20 15 10 5 0 25 85 TJ − Junction Temperature − °C VI = 3.6 V IO = 9 A 20 LRds 15 10 HRds 5 0 −40 125 0 25 85 TJ − Junction Temperature − °C 650 SYNC ≥ 2.5 V 550 450 SYNC ≤ 0.8 V 350 250 −40 0 25 85 125 TJ − Junction Temperature − °C Figure 2. Figure 3. EXTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE VOLTAGE REFERENCE vs JUNCTION TEMPERATURE DEVICE POWER LOSSES vs LOAD CURRENT 4 0.895 1800 RT = 27 kΩ 1200 1000 800 0.893 Device Power Losses − W 1400 600 0.891 0.889 0.887 RT = 100 kΩ 400 −40 0 25 VI = 3.3 V, o TJ = 125 C 3.5 1600 3 2.5 2 1.5 1 0.5 85 0 0.885 −40 125 0 25 85 TJ − Junction Temperature − °C TJ − Junction Temperature − °C 0 125 1 2 3 4 5 6 7 8 9 IL − Load Current − A Figure 4. Figure 5. Figure 6. OUTPUT VOLTAGE REGULATION INPUT VOLTAGE ERROR AMPLIFIER vs OPEN LOOP RESPONSE INTERNAL SLOW-START TIME vs JUNCTION TEMPERATURE 0 140 RL = 10 kΩ, CL = 160 pF, TA = 25°C 120 0.893 3.80 −20 −40 Gain − dB −60 0.891 0.889 80 Phase −80 −100 60 −120 40 Gain 20 −140 −160 0.887 0.885 3 3.1 3.2 3.3 3.4 VI − Input Voltage − V 3.5 3.6 Figure 7. 0 −180 −20 −200 1 k 10 k 100 k 1 M 10 M 1 10 100 f − Frequency − Hz Figure 8. Phase − Degrees 100 Internal Slow-Start Time − ms 0.895 VO − Output Voltage Regulation − V 125 750 Figure 1. Vref − Voltage Reference − V f − Externally Set Oscillator Frequency − kHz 0 −40 f − Internally Set Oscillator Frequency − kHz 25 Drain Source On-State Resistance − mΩ Drain Source On-State Resistance − mΩ 25 INTERNALLY SET OSCILLATOR FREQUENCY vs JUNCTION TEMPERATURE 3.65 3.50 3.35 3.20 3.05 2.90 2.75 −40 0 25 85 Figure 9. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 125 TJ − Junction Temperature − °C 7 TPS54917 SLVS847 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION Figure 10 shows the schematic diagram for a typical TPS54917 application. The TPS54917 (U1) can provide up to 9 A of output current at a nominal output voltage of 1.8 V. For proper thermal performance, the exposed thermal PowerPAD underneath the integrated circuit, TPS54917, package must be soldered to the printed-circuit board. U1 TPS54917RUV VOUT = 1.8 V, 9 A MAX C3 100 mF L1 0.35 mH VIN = 3 - 4 V C1 22 mF C2 22 mF C9 0.01 mF C11 0.01 mF C6 0.047 mF C12 0.01 mF C8 0.047 mF C4 100 mF R4 10 W C10 330 pF R6 2.32 kW C7 5600 pF R5 27.4 kW C5 R7 1200 pF 681 W R1 10 W R8 10 kW R2 10 kW Analog and power grounds are tied at the pad under the package of the IC Figure 10. Application Circuit COMPONENT SELECTION INPUT FILTER The values for the components used in this design example were selected for best load transient response and small PCB area. Additional design information is available at www.ti.com. The input voltage is a nominal 3.3 VDC. The input filter capacitors (C1 and C2) are 10-µF ceramic capacitors (MuRata). C12 is a 0.01-µF ceramic capacitor that provides high-frequency decoupling of the TPS54917 from the input supply. C1, C2 and C12 must be located as close as possible to the device. Input ripple current is shared among C1, C2 and C12. 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 TPS54917 www.ti.com ........................................................................................................................................................................................... SLVS847 – NOVEMBER 2008 FEEDBACK CIRCUIT The values for these components are selected to provide fast transient response times. The resistor divider network of R1 and R2 sets the output voltage for the circuit at 1.8 V. R1 along with R6, R7, C5, C7, and C10 forms the loop compensation network for the circuit. For this design, a Type-3 topology is used. The feedback loop is compensated so that the unity gain frequency is approximately 40 kHz. OPERATING FREQUENCY In the application circuit, RT is grounded through a 27.4-kΩ resistor to select the operating frequency of 1.6 MHz. To set a different frequency, place a 27-kΩ to 180-kΩ resistor between RT (pin 29) and analog ground or leave RT floating to select the default of 350 kHz. The switching frequency in MHz can be approximated using the following equation: 51000 FSW = (RT + 4400 ) (1) OUTPUT FILTER The output filter is composed of a 0.35-µH inductor and 2 x 100-µF capacitors. The inductor is a dual coil type, Coilcraft SLC7530-820ML, with the coils wired in series. The capacitors used are 100-µF, 6.3-V ceramic types with X5R dielectric. PCB LAYOUT Figure 11 shows a generalized PCB layout guide for the TPS54917. The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low ESR ceramic bypass capacitors. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the TPS54917 ground pins. The minimum recommended bypass capacitance is 10 µF ceramic with a X5R or X7R dielectric and the optimum placement is closest to the VIN pins and the PGND pins. The TPS54917 has two internal grounds (analog and power). The analog ground ties to all of the noise-sensitive signals, while the power ground ties to the noisier power signals. Noise injected between the two grounds can degrade the performance of the TPS54917, particularly at higher output currents. Ground noise on an analog ground plane can also cause problems with some of the control and bias signals. For these reasons, separate analog and power ground traces are recommended. There should be an area of ground on the top layer directly under the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the ground side of the input and output filter capacitors as well. The AGND and PGND pins should be tied to the PCB ground by connecting them to the ground area under the device as shown. Use a separate wide traces for the analog ground signal path. This analog ground should be used for the voltage set point divider, timing resistor RT, slow start capacitor, and bias capacitor grounds. Connect this trace the topside groud area near AGND (Pin 1). The PH pins should be tied together and routed to the output inductor. Since the PH connection is the switching node, the inductor should be located very close to the PH pins and the area of the PCB conductor minimized to prevent excessive capacitive coupling. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. Connect the output filter capacitor(s) as shown between the VOUT trace and PGND. It is important to keep the loop formed by the PH pins, Lout, Cout and PGND as small as practical. Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place these components too close to the PH trace. Due to the size of the IC package and the device pinout, the components will have to be routed somewhat close, but maintain as much separation as possible while still keeping the layout compact. Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350 kHz operating frequency, connect them to this trace as well. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 9 TPS54917 SLVS847 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com VOUT TOPSIDE GROUND AREA INPUT BYPASS CAPACITOR PGND PGND PGND PGND PH PH EXPOSED POWERPAD AREA VIN INPUT BULK FILTER OUTPUT INDUCTOR PGND PGND Vin PGND PGND OUTPUT FILTER CAPACITOR PH PH PH VIN PH VIN PH VIN PH VIN BOOT VBIAS PWRGD SS/ENA COMP SYNC VSENSE BOOT CAPACITOR COMPENSATION NETWORK BIAS CAPACITOR RT AGND PGND PGND PGND PGND PGND SLOW START CAPACITOR FREQUENCY SET RESISTOR ANALOG GROUND TRACE ANALOG GROUND TRACE VIA to Ground Plane Figure 11. TPS54917 PCB Layout Estimated Circuit Area The estimated printed circuit board area for the components used in the design of Figure 10 is 0.55 in2. This area does not include test points or connectors. heat, and any area available must be used when 6 A or greater operation is desired. Connection from the LAYOUT CONSIDERATIONS FOR THERMAL exposed area of the PowerPAD to the analog ground PERFORMANCE plane layer must be made using 0.013-inch diameter The RUV package has been chosen to enable a vias to avoid solder wicking through the vias. thermal management scheme, allowing a grund plane 12 vias must be in the PowerPAD area located under to extend beyond both ends of the package. the device package. Additional vias beyond the For operation at full rated load current, the analog twelve recommended may be added in the ground ground plane must provide an adequate heat area outside the package footprint to enhance dissipating area. A 3-inch by 3-inch plane of 1 ounce thermal performance. The size of the vias outside of copper is recommended, though not mandatory, the package, not in the exposed thermal pad area, depending on ambient temperature and airflow. Most can be increased to 0.018. applications have larger areas of internal ground plane available, and the PowerPAD must be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate 10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 TPS54917 www.ti.com ........................................................................................................................................................................................... SLVS847 – NOVEMBER 2008 PERFORMANCE GRAPHS EFFICIENCY vs OUTPUT CURRENT LOAD REGULATION vs OUTPUT CURRENT LINE REGULATION vs INPUT VOLTAGE 0.04 90 0.04 VI = 4 V 85 0.03 0.03 VI = 3.3 V VI = 3.3 V 75 70 65 60 fs = 1600 kHz, VO = 2.5 V 55 50 0 0.02 0.02 Percent Deviation - % VI = 3 V Percent Deviation - % Efficiency − % 80 0.01 0 -0.01 -0.02 -0.03 2 3 4 5 6 7 8 9 10 11 12 0 -0.01 -0.02 -0.03 -0.04 1 IO = 4.5 A 0.01 0 1 2 3 4 5 6 7 IO − Output Current − A IO − Output Current − A 8 -0.04 3 9 3.2 3.4 3.6 3.8 VI - Input Voltage - V 4 Figure 12. Figure 13. Figure 14. AMBIENT TEMPERATURE vs LOAD CURRENT(1) OUTPUT RIPPLE VOLTAGE TRANSIENT RESPONSE 125 VOUT 50 mV/div VOUT 75 IOUT 20 mV/div PH 2 A/div fs = 1600 kHz, TJ = 125°C, VI = 3.3 V, VO = 1.8 V 50 25 0 1 2 3 4 5 6 7 IO − Output Current − A 8 t - Time - 1 ms/div t - Time - 500 ns/div 9 Figure 15. Figure 16. SLOW-START TIMING INPUT RIPPLE Figure 17. CLOSED LOOP RESPONSE 60 2 V/div 180 50 VIN SS/ENA Phase 120 30 90 60 50 mV/div PH VOUT 1 V/div t - Time - 50 ms/div Figure 18. t - Time - 500 ns/div Figure 19. Gain - dB 20 2 V/div 150 40 10 30 Gain 0 0 Phase - deg Ambient Temperature -° C 2 V/div 100 -10 -30 -20 -60 -30 -90 -40 -120 -50 -60 10 100 1k 10k 100k f - Frequency - Hz -150 -180 1M Figure 20. (1) Safe operating area is applicable to the test board conditions listed in the dissipation rating table section of this data sheet. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 11 TPS54917 SLVS847 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com VBIAS Regulator (VBIAS) DETAILED DESCRIPTION Under Voltage Lock Out (UVLO) The TPS54917 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator, and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on VIN. Slow-Start/Enable (SS/ENA) The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of triggering the enable due to noise. The second function of the SS/ENA pin provides an external means of extending the slow-start time with a low-value capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The start-up delay is approximately: 1.2 V t +C d (SS) 5 mA (2) Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor. The slow-start time set by the capacitor is approximately: 0.7 V t +C (SS) (SS) 5 mA (3) The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND. External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V, and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a reference voltage for external circuits. Voltage Reference The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the high precision regulation of the TPS54917, since it cancels offset errors in the scale and error amplifier circuits. Oscillator and PWM Ramp The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the SYNC pin as a static digital input. If a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 to 1600 kHz by connecting a resistor between the RT pin to ground and floating the SYNC pin. The switching frequency in MHz is approximated by the following equation, where R is the resistance in Ohms from RT to AGND: 51000 FSW = (RT + 4400 ) (4) External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 1600 kHz by driving a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose a RT resistor that sets the free running frequency to 80% of the synchronization signal. Table 1 summarizes the frequency selection configurations: The actual slow-start time is likely to be less than the above approximation due to the brief ramp-up at the internal rate. 12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 TPS54917 www.ti.com ........................................................................................................................................................................................... SLVS847 – NOVEMBER 2008 Table 1. Summary of the Frequency Selection Configurations SWITCHING FREQUENCY SYNC PIN RT PIN 350 kHz, internally set Float or AGND Float 550 kHz, internally set ≥ 2.5 V Float Externally set 280 kHz to 1.6MHz Float R = 27 k to 180 k Externally synchronized frequency Synchronization signal R = RT value for 80% of external synchronization frequency Error Amplifier The high performance, wide bandwidth, voltage error amplifier sets the TPS54917 apart from most dc/dc converters. The user is given the flexibility to use a wide range of output L and C filter components to suit the particular application needs. Type-2 or Type-3 compensation can be employed using external compensation components. PWM Control Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch, and portions of the adaptive dead-time and control-logic block. During steady-state operation below the current limit threshold, the PWM comparator output and oscillator pulse train alternately reset and set the PWM latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM ramp. During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting VSENSE to approximately the same voltage as VREF. If the error amplifier output is low, the PWM latch is continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE voltage decreases to a range that allows the PWM comparator to change states. The TPS54917 is capable of sinking current continuously until the output reaches the regulation set-point. If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds the error amplifier output. The high-side FET turns off and low-side FET turns on to decrease the energy in the output inductor and consequently the output current. This process is repeated each cycle in which the current limit comparator is tripped. Dead-Time Control and MOSFET Drivers Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. While the low-side driver does not turn on until the voltage at the gate of the high-side MOSFET is below 2 V. The high-side and low-side drivers are designed with 300-mA source and sink capability to drive the power MOSFETs gates. The low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit uses an external BOOT capacitor and an internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins. The integrated bootstrap switch improves drive efficiency and reduces external component count. Overcurrent Protection The cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and comparing this signal to a preset overcurrent threshold. The high side MOSFET is turned off within 200 ns of reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents current limit false tripping. Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter. Load protection during current sink operation is provided by thermal shutdown. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 13 TPS54917 SLVS847 – NOVEMBER 2008 ........................................................................................................................................................................................... www.ti.com Thermal Shutdown Power Good (PWRGD) The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction temperature exceeds 150°C. The device is released from shutdown automatically when the junction temperature decreases to 10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit. The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE is 10% below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is less than the UVLO threshold or SS/ENA is low. When VIN ≥ UVLO threshold, SS/ENA ≥ enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A hysteresis voltage equal to 3% of Vref and a 35 µs falling edge deglitch circuit prevent tripping of the power good comparator due to high frequency noise. Thermal shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent fault condition, the device cycles continuously; starting up by control of the soft-start circuit, heating up due to the fault condition, and then shutting down upon reaching the thermal shutdown trip point. This sequence repeats until the fault condition is removed. 14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :TPS54917 PACKAGE OPTION ADDENDUM www.ti.com 16-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS54917RUVR ACTIVE VQFN RUV 34 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS54917RUVT ACTIVE VQFN RUV 34 250 CU NIPDAU Level-3-260C-168 HR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS54917RUVR VQFN RUV 34 3000 330.0 16.4 3.85 7.35 1.2 8.0 16.0 Q1 TPS54917RUVT VQFN RUV 34 250 180.0 16.4 3.85 7.35 1.2 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS54917RUVR VQFN RUV 34 3000 367.0 367.0 38.0 TPS54917RUVT VQFN RUV 34 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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