TI TPS22981RGPR

TPS22981
www.ti.com
SLVSBM6 – DECEMBER 2012
3.3V to 18V Thunderbolt Power Mux
Check for Samples: TPS22981
FEATURES
1
•
•
•
•
•
•
•
•
Powered from 3.3V
4.5V to 19.8V High Voltage Switch
3V to 3.6V Switch
Adjustable Current Limit
Thermal Shutdown
Make Before Break Switch
High Voltage Discharge Before Low Voltage
Make
Reverse Current Blocking
APPLICATIONS
•
•
•
Notebook Computers
Desktop Computers
Power Management Systems
HV_EN
OUT
GND
OUT
RSVD
connector
RSET_S0
ENHVU
ISET_S0
S0
ISET_S3
RSET_S3
RSET_V3P3
V3P3OUT
ISET_V3P3
VHV
The TPS22981 is a current-limited power mux
providing a connection to a peripheral device from
either a low voltage supply (3V to 3.6V) or a high
voltage supply (4.5V to 19.8V). The desired output is
selected by digital control signals.
The high voltage (VHV) and low voltage (V3P3)
switch current limits are set with external resistance.
Once the current limit is reached, the TPS22981 will
control the switch to maintain the current at this limit.
When the high voltage supply is not present, the
TPS22981 will maintain the connection to the output
from the low voltage supply. Upon the presence of a
high voltage line and high voltage enable signal, the
high voltage switch is turned on in conjunction with
the low voltage switch until a reverse current is
detected through the low voltage switch, allowing a
seamless transition from low voltage to the high
voltage supply with minimal droop and shoot-through
current.
To prevent current backflow during a switch over from
a VHV connection to a V3P3 connection, the
TPS22981 will break the VHV connection, discharge
the output to approximately 3.3V and then make the
V3P3 connection. The output will transition to 0V
when a load is present, before returning to 3.3V.
The TPS22981 is available in a 4mm x 4mm x 1mm
QFN package.
DC/DC
EN
GND
V3P3
FAULTZ
VHV
GND
V3P3
GND
DC/DC
Exposed Pad
DESCRIPTION
µC
Figure 1. Typical Application
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS22981
SLVSBM6 – DECEMBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE
DEVICE SPECIFIC FEATURES
TPS22981RGPR
PS22981
RGP
Tape and Reel
11
V3P3
S0
V3P3
V3P3OUT
V3P3OUT
V3P3
S0
V3P3
ENHVU
15
14
13
OUT
ENHVU
12
11
HV_EN
HV_EN
12
OUT
OUT
13
GND
GND
14
GND
OUT
15
Bottom View
GND
GND
Top View/Footprint
Package Size: 4mm x 4mm x 1mm height
Pad Pitch: 0.5mm
DISSIPATION RATINGS
(1)
(2)
2
PACKAGE
THERMAL RESISTANCE (1)
θJA
POWER RATING (1)
TA = 25°C
POWER RATING (1)
TA = 70°C
DERATING FACTOR ABOVE (2)
TA = 25°C
RGP
39.3°C/W
2.16W
1.02W
25.4mW/°C
Simulated with high-K board
Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / θJA.
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SLVSBM6 – DECEMBER 2012
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
Input voltage range on V3P3 (VDD)
(2)
–0.3 to 3.6
Input voltage range on EN, HV_EN, ENHVU, ISET_V3P3, ISET_S0, ISET_S3, S0 (2)
–0.3 to V3P3+0.3
Output voltage range on FAULTZ
–0.3 to V3P3+0.3
Input voltage range on VHV (2)
VI
Output voltage range at OUT
–0.3 to 20
(2)
Output voltage range at V3P3OUT (2)
TJ
(MAX)
Tstg
(1)
(2)
(3)
–7 to 20
–0.3 to V3P3+0.3
Operating ambient temperature range (3)
–40 to 85
°C
Maximum operating junction temperature
110
°C
–65 to 150
°C
Storage temperature range
ESD Rating
V
–0.3 to 20
Voltage range between VHV and OUT (VVHV–VOUT)
TA
UNIT
Charge Device Model (JESD 22 C101)
Human Body Model (JESD 22 A114)
500
V
2
kV
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)],
the maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the
part/package in the application (M JA), as given by the following equation: TA(max) = TJ(max) – (M JA × PD(max))
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
V3P3
VHV
Supply voltage range
MAX
UNIT
3
3.6
4.5
19.8
V
V
0
500
mA
ILIM3P3OUT
V3P3OUT Switch current range
VIH
Input logic high
EN, HV_EN, ENHVU, S0
V3P3-0.6
V3P3
VIL
Input logic low
EN, HV_EN, ENHVU, S0
0
0.6
V
RSET_V3P3
3.3V switch current limit set resistance
26.7
402
kΩ
RSET_S0
VHV switch current limit in S0 mode set resistance
26.7
402
kΩ
RSET_S3
VHV switch current limit in S3 mode set resistance
26.7
402
kΩ
RFAULTZ
FAULTZ pull-up resistance to V3P3
30
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V
kΩ
3
TPS22981
SLVSBM6 – DECEMBER 2012
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ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies over the VDD range and operating junction temp –40°C ≤ TJ ≤ 85°C. Typical
values are for V3P3 = 3.3V, VHV = 15V, and TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
3
3.3
MAX
UNIT
POWER SUPPLIES AND CURRENTS
V3P3
V3P3 Input voltage range
VHV
VHV Input voltage range
IVHVACT
Active quiescent current from VHV
HV_EN = 1, EN = 1
IVHVSD
Shutdown leakage current from VHV
HV_EN = 0, EN = 0 or 1
IDDACT
4.5
Active quiescent current from V3P3
IDDACTHV
3.6
V
19.8
V
150
µA
60
µA
EN = 1, HV_EN = 0
500
µA
EN = 1, HV_EN = 1
500
µA
30
µA
10
mA
IDDSD
Shutdown quiescent current from V3P3
EN = 0, OUT = 0 V
IDIS
OUT Discharge current
EN = 1, VHV = 5V, HV_EN = 1→0
IIN
HV_EN, EN, ENHVU, S0, S3 Input pin leakage
5
V=0V
1
V = V3P3
1
µA
SWITCH AND RESISTANCE CHARACTERISTICS
RSHV
VHV Switch resistance
VHV = 5V to 18V, IVHV = 0.9A
250
mΩ
RS3P3
V3P3 Switch resistance
V3P3 = 3.3 V, IV3P3 = 0.9 A
125
mΩ
RS3P3BYP
V3P3 Bypass switch resistance
V3P3 = 3.3 V, IV3P3 = 500 mA
500
mΩ
VOLFAULTZ
FAULTZ VOL
IFAULTZ = 250 µA
0.6
V
VOLTAGE THRESHOLDS
VHVUVLO
VHV Under voltage lockout
V3P3UVLO
V3P3 Under voltage lockout
VFAULTZVAL
V3P3 Voltage for valid FAULTZ
VHV Input falling
3.6
VHV Input rising
V3P3 Input falling
4
1.8
V3P3 Input rising
EN = 1
4
4.3
2.25
2.25
2.5
1.8
V
V
V
THERMAL SHUTDOWN
TSD
Shutdown temperature
TSDHYST
Shutdown hysteresis
110
120
130
10
°C
°C
CURRENT LIMIT
ILIMHV
VHV Switch current limit state S0 or S3
ILIMVHVMAX
ILIM3P3
Maximum VHV switch current limit
V3P3 Switch current limit
RSET_S0,3 = 402 kΩ (1)
80
100
RSET_S0,3 = 80.6 kΩ (1)
446
496
546
RSET_S0,3 = 26.7 kΩ (1)
1423
1498
1573
120
RSET_S0,3 = 0 Ω
1.8
2.4
3.1
RSET_V3P3 = 402 kΩ (1)
80
100
120
mA
A
RSET_V3P3 = 80.6 kΩ (1)
446
496
546
RSET_V3P3 = 26.7 kΩ (1)
1423
1498
1573
1.8
2.4
3.1
A
10
40
85
mA
100
µs
RSET_V3P3 = 0Ω
mA
ILIM3P3MAX
Maximum V3P3 switch current limit
IREV3P3
V3P3 Switch reverse current limit
TV3P3RC
V3P3 Switch reverse current response time
VOUT = V3P3→V3P3 + 20 mV
TVHVSC
VHV Switch short circuit response time
COUT ≤ 20 pF
8
µs
TV3P3SC
V3P3 Switch short circuit response time
COUT ≤ 20 pF
8
µs
TRANSITION DELAYS
T3P3OFF
VHV to V3P3 Off time
COUT = 1.1 µF, EN = 1, HV_EN = 1→0
6
ms
T0-3.3V
0V to 3.3V Ramp time
COUT ≤ 20 pF
6
ms
T3.3V-VHV
3.3V to VHV Ramp time
COUT ≤ 20 pF
6
ms
TVHV-3.3V
VHV to 3.3V Ramp time
COUT ≤ 20 pF
23
ms
TLIM
Overcurrent response time
COUT ≤ 20 pF, IOUT = 6 A
0.5
ms
(1)
4
Equation 1 is used to calculate the required resistance for a given minimum ILIM. The nearest 1% resistance is chosen and the
corresponding ILIM variance is shown.
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SLVSBM6 – DECEMBER 2012
FUNCTIONAL BLOCK DIAGRAM
6
VHV
7
S0
17
ISET_V3P3
8
VTHV
OUT
12
10
ISET_S0
14
9
GND
ISET_S3
1
Switch
CTRL
Logic
11
HV_EN
2
16
ENHVU
3
5
EN
4
FAULTZ
13
Thermal
Shutdown
15
V3P3
19
V3P3OUT
20
18
Figure 2. Functional Block Diagram
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TPS22981
SLVSBM6 – DECEMBER 2012
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PIN FUNCTIONS
PIN
NO.
1, 2, 3, 13, 15 GND
Device ground. All GND pins must be connected to board ground.
4
FAULTZ
Fault condition output. This pin is an open drain pull-down indicating a fault condition. Place a pull-up
resistance (RFAULTZ) between this pin and V3P3. Float pin or tie pin to GND if unused.
5
EN
Device active-high enable.
VHV
High voltage power supply input. See the Input Inductive Bounce at Short Circuit section for more information.
8
ISET_V3P3
Sets the current limit for V3P3. Place resistor between this pin and GND. See Equation 3 to calculate resistor
value.
9
ISET_S3
Sets the current limit for VHV in S3 mode. Place resistor between this pin and GND. See Equation 1 to
calculate resistor value.
10
ISET_S0
Sets the current limit for VHV in S0 mode. Place resistor between this pin and GND. See Equation 2 to
calculate resistor value.
11
HV_EN
Active-high voltage output enable.
OUT
Power output. Place a minimum of 1µF capacitor as close to this pin as possible.
16
ENHVU
Enable VHV UVLO control of device enable. When asserted high, both V3P3 and VHV must be present for
device enable. When low, only V3P3 must be present for device enable.
17
S0
When this pin is asserted, the device is put in S0 mode. Otherwise the device operates in S3 mode.
18
V3P3OUT
3.3V bypass output. When ENHVU is low, this path is enabled by EN and the V3P3 UVLO. When ENHVU is
high, this path is enabled by EN and both the V3P3 UVLO and the VHV UVLO. Place a minimum of 0.1µF
capacitor as close to this pin as possible.
19, 20
V3P3
3.3V power supply input. Place a minimum of 0.1µF capacitor as close to this pin as possible.
EP
GND
Exposed pad must be connected to device GND.
6, 7
12, 14
6
DESCRIPTION
NAME
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SLVSBM6 – DECEMBER 2012
APPLICATION INFORMATION
TYPICAL APPLICATION
HV_EN
OUT
GND
OUT
RSVD
connector
RSET_S0
ENHVU
ISET_S0
S0
ISET_S3
RSET_S3
RSET_V3P3
V3P3OUT
VHV
DC/DC
EN
FAULTZ
V3P3
GND
VHV
GND
V3P3
GND
DC/DC
Exposed Pad
ISET_V3P3
µC
Figure 3. Typical Application
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TPS22981
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CURRENT LIMIT
Figure 4 shows a simplified view of the TPS22981 current limit function. Both the high voltage supply current limit
and the V3P3 supply current limit are adjustable by external resistors
VHV
4.5 - 18V
IREF _HV
Switch
CTRL
Logic
OUT
I REF_V3P3
3.3V
Figure 4. Simplified Current Limit Diagram
The current IREF_HV and IREF_V3P3 that set the current limit threshold are set with three external resistors as shown
in Figure 5. When the TPS22981 is passing the V3P3 voltage, the current limit is set by RSET_V3P3. The VHV path
has two modes that allow setting two different current limits. The S0 pin determines which current limit is used.
When S0 is asserted high, RSET_S0 sets the current limit. When S0 is low, RSET_S3 sets the current limit. This
allows the system to have two separate VHV current limits for different modes such as active and sleep.
RSET_V3P3
ISET_V3P3
RSET_S3
ISET_S3
RSET_S0
ISET_S0
Figure 5. External RSET Resistance to set Current Limits
8
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SLVSBM6 – DECEMBER 2012
CURRENT LIMIT THRESHOLD
1600
20%
1400
15%
% variance from min - mA
25%
ILIMHV/V3P3 - mA
1800
1200
1000
min
800
typ
600
max
400
typ
5%
max
0%
0
15%
-20%
100
150
200
250
300
RSET_S0/S3/V3P3 (kΩ)
350
400
150
200
250
300
350
400
450
450
-25%
Figure 6. ILIM vs RSET for VHV and V3P3
100
10%
0
50
50
-5%
200
0
min
10%
RSET_S0/S3/V3P3 (kΩ)
Figure 7. % Variance from min ILIM vs RSET
Figure 6 shows the minimum, typical, and maximum current limit for either supply versus its corresponding RSET
value. Equation 1 is used to determine the RSET needed to set a typical ILIM for a given supply and mode.
Figure 7 shows the percent variation from the typical ILIM value to the minimum and maximum ILIM values.
40 kW ´ Amps
RSET =
ILIMTYP
(1)
Where
RSET = external resistor used to set the current limit for V3P3, VHV (S0), or VHV (S3), and
ILIMTYP = typical current limit for V3P3, VHV (S0), or VHV (S3) set by the external RSET resistor.
Each resistor is placed between the corresponding ISET pin and GND, as shown in Figure 5, providing a
minimum current limit between 100mA and 1.5A. For a given RSET the minimum current limit and the maximum
current limit are determined by Equation 2 and Equation 3.
38429
ILIMMIN =
– 0.0161 A
RSET
(2)
ILIMMAX =
41571
+ 0.0161 A
RSET
(3)
MAXIMUM CURRENT LIMIT THRESHOLD
The TPS22981 has a maximum current limit ILIMVHVMAX and ILIM3P3MAX. This prevents excessive current in the
case of an ISET pin being shorted to ground.
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TRANSITION DELAYS
Output transitions of the TPS22981 voltages are shown in Figure 8. When the device transitions from VHV to V3P3
at the output, the power switches both turn off until the output falls to near the V3P3 voltage. During this time, a
discharge current of IDIS pulls OUT down. If a load is also pulling current from OUT, the output will drop to near
0V due to the switch off time of T3P3OFF.
VOUT
VHV
t3P3OFF
V3P3
Time
t0-3.3V
t3.3V-VHV
tVHV-3.3V
t0-3.3V
Figure 8. Output Voltage Transitions (Timing transitions are 10% to > 90%)
DIGITAL CONTROL SIGNALS
The voltage at OUT is controlled by two input digital logic signals, EN and HV_EN. HV_EN controls the state of
the VHV switch and EN controls the state of V3P3 switch. Table 1 lists the possible output states given the
conditions of the digital logic signals and the device is not in UVLO. See Table 2 for a more complete description
including both UVLO conditions.
Table 1. Output state of OUT Given the States EN and HV_EN
10
EN
HV_EN
OUT
0
0
OPEN
0
1
OPEN
1
0
V3P3
1
1
VHV
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Figure 9 shows possible combinations of EN and HV_EN controlling OUT of the TPS22981.
EN
HV_EN
V3P3
VHV
IDIS
0mA
IDIS
VHV
OUT Hi-Z
3.3V
Hi-Z
3.3V
Hi-Z
Figure 9. Logic Waveforms Displaying the Transition Between VHV and V3P3
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OVER-CURRENT LIMIT AND SHORT CIRCUIT PROTECTION
When the load at OUT attempts to draw more current than the limit set by the external RSET resistors for the
V3P3 switch and VHV switch (for both S0 and S3 modes), the device will operate in a constant current mode
while lowering the output voltage. Figure 10 shows the delay, tLIM, which occurs from the instance an overcurrent fault is detected until the output current is lowered to ILIMHV tolerances for VHV or ILIM3V3 tolerances for
V3P3 shown in Figure 6. Figure 11 shows the response time versus a resistance shorted across the output.
Output
Voltage
t
Load
Current
OC Limit
tLIM delay
Figure 10. Overcurrent Output Response
1.00E-02
1.00E-03
TLIM
1.00E-04
1.00E-05
1.00E-06
1.00E-07
1.00E-08
0
1
2
3
4
5
6
Short Resistance - Ω
7
8
9
Figure 11. Overcurrent Response Time vs Short Resistance
All short circuit conditions are treated as over-current conditions. In the event of a short circuit, the device will
limit the output current to the corresponding RSET value and continue to do so until thermal shutdown is
encountered or the short circuit condition is removed.
REVERSE CURRENT PROTECTION
Reverse current protection for the V3P3 supply to OUT triggers at IREV3P3 causing the V3P3 supply switch to
open. When the HV_EN signal is not asserted and reverse current protection is triggered, a discharge current
source is turned on to bring the output voltage to near the V3P3 voltage.
12
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REVERSE CURRENT BLOCKING
The VHV switch blocks reverse current flow from OUT to VHV when the switch is off.
THERMAL SHUTDOWN
The device enters thermal shutdown when junction temperature reaches TSD. The device will resume previous
state on power up once the junction temperature has dropped by 10C. Connect thermal vias to the exposed
GND pad underneath the device package for improved thermal diffusion.
UVLO and ENABLE
When ENHVU is low, the TPS22981 is enabled by the logical AND of the EN input, the V3P3 UVLO, and the
Thermal Shutdown. When the V3P3 UVLO threshold has been crossed, the device is not in thermal shutdown,
and the EN input is high, the device will enable. When the V3P3 UVLO triggers, regardless of the states of any
digital logic controls, the device will open all switches.
ENHVU adds the VHV UVLO to the logical decision enabling the device. When ENHVU is high, the TPS22981 is
enabled by the logical AND of the EN input, the V3P3 UVLO, the VHV UVLO, and the Thermal Shutdown. When
both UVLO thresholds have been crossed, the device is not in thermal shutdown, and the EN input is high, the
device will enable. When either UVLO triggers, regardless of the states of any digital logic controls, the device
will open all switches. Table 2 shows the pin and voltage configurations for enabling the device. Note, a 1 for the
UVLO columns means the device is in a UVLO condition.
Table 2. Device Enable Control (when in an under-voltage condition, UVLO = 1)
EN
ENHVU
HV_EN
V3P3 UVLO
VHV UVLO
OUT
0
X
X
X
X
OPEN
1
X
X
1
X
OPEN
1
1
X
X
1
OPEN
1
0
0
0
X
V3P3
1
1
0
0
0
V3P3
1
X
1
0
0
VHV
1
0
1
0
1
V3P3
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FAULTZ Output
The TPS22981 has an open-drain FAULTZ output. When the device is in a fault condition, the FAULTZ output
will pull low. Connect FAULTZ through a pull-up resistance to V3P3. A Fault occurs during any of the following
conditions.
• EN = 1 and V3P3 is in UVLO (device enabled and V3P3 is in an under-voltage condition)
• EN = 1 and in Thermal Shutdown condition
• EN = 1, HV_EN = 1, and VHV is in UVLO (device enabled, high voltage enabled, and VHV is in an undervoltage condition)
Table 3 shows these conditions and the resulting FAULTZ output. Note, when V3P3 is below the UVLO
threshold, FAULTZ will be 0 when EN=1 or 1 when EN=0. However, when V3P3 falls below VFAULTZVAL, the
FAULTZ output is unknown.
Table 3. FAULTZ Output Conditions (when in an under-voltage condition, UVLO = 1)
EN
HV_EN
Thermal Shutdown
V3P3 UVLO
VHV UVLO
FAULTZ (Active Low)
0
X
X
X
X
1
1
X
X
1
X
0
1
X
Yes
0
X
0
1
0
No
0
1
1
1
1
No
0
1
0
1
X
No
0
0
1
It is recommended that the pull-up resistance on FAULTZ be 100kΩ and must be greater than or equal to 30kΩ.
INPUT INDUCTIVE BOUNCE AT SHORT CIRCUIT
When a significant inductance is seen at the VHV input, suddenly turning off large current through the device
may produce a large enough inductive voltage bounce on the VHV pin to exceed the maximum safe operating
condition and damage the TPS22981. To prevent this, reduce any inductance at the VHV input.
14
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PACKAGE OPTION ADDENDUM
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13-Dec-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS22981RGPR
ACTIVE
Package Type Package Pins Package Qty
Drawing
QFN
RGP
20
3000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
CU NIPDAU
MSL Peak Temp
Samples
(3)
(Requires Login)
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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