SAMSUNG K4J55323QF-GC

256M GDDR3 SDRAM
K4J55323QF-GC
256Mbit GDDR3 SDRAM
Revision 1.8
April 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
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TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
Revision History
Revision 1.8 (April 9, 2005)
- Modified note description for the Write Latency on page 47.
Revision 1.7 (Jan. 18 , 2005)
- Added Lead Free package part number in the data sheet.
Revision 1.6 (Dec 2 , 2004)
- Changed ICC2P and ICC6 for all frequency. Separted ICC6 for -GC and -GL.
Revision 1.5 (Oct 5 , 2004)
- Added K4J55323QF-G(V)C15
- Timing diagram corrected on page 28
Revision 1.4 (July 9 , 2004)
- Added K4J55323QF-G(V)L20 which is VDD&VDDQ=1.8V(typical)
Revision 1.3 (June 14 , 2004)
- Changed DC spec value for all the frequency. Refer to the DC characteristics of page 45.
- Removed -GC12 from the spec.
Revision 1.2 (February 18 , 2004)
- Changed VDD/VDDQ from 1.9V+ 0.1V to 2.0V+ 0.1V in all frequencies.
- DC changes : Refer to the DC characteristics of page 45.
Revision 1.1 (January 29 , 2004)
- Typo corrected
Revision 1.0 (January 15 , 2004)
- Changed VDD/VDDQ of K4J55323QF-GC12 from 2.1V+ 0.1V to 1.9V+ 0.1V
- Changed VDD/VDDQ of K4J55323QF-GC14/16/20 from 1.8V+ 0.1V to 1.9V+ 0.1V
- Changed tCK(max) from 3.0ns to 3.3ns
- DC spec finalized. Typo corrected
- 2 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
Revision History
Revision 0.5 (January 7 , 2004) - Preliminary spec
- Added "Dummy MRS" command during the power-up sequence. Typo corrected
Revision 0.4 (December 10 , 2003) - Preliminary spec
- Typo corrected
- Added K4J55323QF-GC12 (800MHz) in the spec
- Key AC parameter changes : Refer to the AC spec table on page 46,47
. Added tDAL in the AC characteristics table,
. Added AC parameter of -GC12 in the AC characteristics table,
. Changed tRC of -GC14 from 31tCK to 30tCK,
. Changed tRFC of -GC16 from 34tCK to 33tCK,
- DC changes : Refer to the DC characteristics table of page 45.
- Capacitance table change : Refer to the Capacitance table of page 45.
Revision 0.3 (November 13, 2003) - Target Spec
- Typo corrected
- Removed 800MHz from the spec
- Changed ICC6 from 4mA to 7mA
- Key AC parameter changes : Refer to the AC spec table on page 46,47
. Changed tWR of -GC14 from 6tCK to 9tCK,
. Changed tWR of -GC16 from 5tCK to 8tCK,
. Changed tWR of -GC20 from 4tCK to 6tCK
. Changed tPDEX and tXSR at low power from 100tCK to 300tCK
Revision 0.2 (October 17, 2003) - Target Spec
- Typo corrected
Revision 0.1 (September 26, 2003) - Target Spec
- Typo corrected
Revision 0.0 (September 25, 2003) - Target Spec
- 3 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
2M x 32Bit x 4 Banks Graphic Double Data Rate 3 Synchronous DRAM
with Uni-directional Data Strobe
FEATURES
• 2.0V + 0.1V power supply for device operation
• RDQS edge-aligned with data for READs
• 2.0V + 0.1V power supply for I/O interface
• WDQS center-aligned with data for WRITEs
• On-Die Termination (ODT)
• Data Mask(DM) for masking WRITE data
• Output Driver Strength adjustment by EMRS
• Auto & Self refresh mode
• Calibrated output drive
• Auto Precharge option
• Pseudo Open drain compatible inputs/outputs
• 32ms, auto refresh (4K cycle)
• 4 internal banks for concurrent operation
• 144 Ball FBGA
• Differential clock inputs (CK and CK)
• Maximum clock frequency up to700MHz
• Commands entered on each positive CK edge
• Maximum data rate up to 1.4Gbps/pin
• CAS latency : 5, 6, 7, 8 and 9 (clock)
• DLL for outputs
• Additive latency (AL): 0 and 1 (clock)
• Programmable Burst length : 4
• Programmable Write latency : 1, 2, 3, 4, 5 and 6 (clock)
• Single ended READ strobe (RDQS) per byte
• Single ended WRITE strobe (WDQS) per byte
ORDERING INFORMATION
Part NO.
Max Freq.
Max Data Rate
K4J55323QF-GC14
700MHz
1400Mbps/pin
K4J55323QF-GC15
667MHz
1334Mbps/pin
K4J55323QF-GC16
600MHz
1200Mbps/pin
K4J55323QF-GC20*
500MHz
1000Mbps/pin
Interface
Package
Pseudo
Open Drain
144 - Ball FBGA
*K4J55323QF-GL20/VL20 : VDD & VDDQ = 1.8V+0.1V(1.7V ~ 1.9V)
*K4J55323QF-V is the Lead Free package part number
GENERAL DESCRIPTION
FOR 2M x 32Bit x 4 Bank GDDR3 SDRAM
The 8Mx32 GDDR3 is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words
by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 5.6GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, and programmable latencies allow the device to be useful for a variety of high performance memory
system applications.
- 4 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
PIN CONFIGURATION
Normal Package (Top View)
2
3
4
5
6
7
8
9
10
11
12
13
B WDQS0 RDQS0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
C
DQ4
DM0
VDDQ
VDDQ
DQ1
VDDQ
VDDQ
DQ30
VDDQ
VDDQ
DM3
DQ27
D
DQ6
DQ5
VSSQ
VSSQ
VSSQ
VDD
VDD
VSSQ
VSSQ
VSSQ
DQ26
DQ25
E
DQ7
RFU3
VDD
VSS
VSSQ
VSS
VSS
VSSQ
VSS
VDD
RFU4
DQ24
F
DQ17
DQ16
VDDQ
VSSQ
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSSQ
VDDQ
DQ15
DQ14
G
DQ19
DQ18
VDDQ
VSSQ
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSSQ
VDDQ
DQ13
DQ12
H WDQS2 RDQS2
VDDQ
VSSQ
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSSQ
VDDQ
RDQS1
WDQS1
J
DQ20
DM2
VDDQ
VSSQ
NC,
VSS
NC,
VSS
NC,
VSS
NC,
VSS
VSSQ
VDDQ
DM1
DQ11
K
DQ21
DQ22
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ9
DQ10
L
DQ23
A3
VDD
VSS
RFU2
VDD
VDD
RFU1
VSS
VDD
A4
DQ8
M
VREF
A2
A10
/RAS
RESET
CKE
RFU5
ZQ
/CS
A9
A5
VREF
N
A0
A1
A11
BA0
/CAS
CK
/CK
/WE
BA1
A8/AP
A6
A7
RDQS3 WDQS3
NOTE :
1. RFU1 is reserved for A12
2. RFU2 is reserved for BA2
3. (M,13) VREF for CMD and ADDRESS
4. (M,2) VREF for Data input
- 5 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
Input
Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive
edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both
directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all
banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and
exit, and for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high
throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during powerdown. Input buffers, excluding CKE, are disabled during self refresh.
CS
Input
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection
on systems with multiple banks. CS is considered part of the command code.
RAS,
CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM0
~DM3
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH
coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM
pins are input only, the DM loading matches the DQ and DQS loading.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is
being applied. BA0 also determines if the mode register or extended mode register is to be accessed during a
MRS or EMRS cycle.
A0 ~ A11
Input
Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8
is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW)
or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address
inputs also provide the op-code during Mode Register Set commands.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 . Column address CA8 is used for auto
precharge.
DQ0
~ DQ31
Input/
Output
Data Input/ Output: Bi-directional data bus.
RDQS0
~ RDQS3
Output
READ Data Strobe: Output with read data. RDQS is edge-aligned with read data.
WDQS0
~ WDQS3
Input
CK, CK
NC/RFU
WRITE Data Strobe: Input with write data. WDQS is center-aligned to the input data.
No Connect: No internal electrical connection is present.
VDDQ
Supply
DQ Power Supply: 2.0V ± 0.1V
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 2.0V ± 0.1V
VSS
Supply
Ground
VREF
Supply
Reference voltage: 0.7*VDDQ ,
2 Pins : (M,2) for Data input , (M,13) for CMD and ADDRESS
ZQ
RES
Reference Resistor connection pin for On-die termination.
The value of Resistor = 240 Ω
Input
Reset pin: RESET pin is a VDDQ CMOS input
- 6 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
BLOCK DIAGRAM (2Mbit x 32I/O x 4 Bank)
WDQS
Input Buffer
32
Input Buffer
I/O Control
Data Input Register
Serial to parallel
Bank Select
LWE
LDMi
128
2M x 32
32
Output Buffer
2M x 32
128
4-bit prefetch
Sense AMP
Row Decoder
Refresh Counter
Row Buffer
ADDR
Address Register
iCK
2M x 32
x32
DQi
2M x 32
Column Decoder
Col. Buffer
LCBR
LRAS
Latency & Burst Length
LRAS LCBR
Strobe
Gen.
Programming Register
LCKE
Output
DLL
RDQS
LWE
LCAS
LWCBR
CK,CK
LDMi
Timing Register
iCK
CKE
CS
RAS
CAS
WE
DMi
* iCK : internal clock
- 7 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
FUNCTIONAL DESCRIPTION
Simplified State Diagram
Power
Applied
Power
On
Self
Refresh
Precharge
PREALL
REFS
REFSX
MRS
EMRS
MRS
Auto
Refresh
REFA
Idle
CKEL
CKEH
Active
Power
Down
ACT
Precharge
Power
Down
CKEH
CKEL
Row
Active
Read
Write
Write A
Write
Write
Read A
Read
Read
Read A
Write A
Read
A
PRE
Write
A
PRE
PRE
PRE
Read
A
Precharge
PREALL
Automatic Sequence
Command Sequence
PREALL = Precharge All Banks
MRS = Mode Register Set
EMRS = Extended Mode Register Set
REFS = Enter Self Refresh
REFSX = Exit Self Refresh
REFA = Auto Refresh
CKEL = Enter Power Down
CKEH = Exit Power Down
ACT = Active
Write A = Write with Autoprecharge
Read A = Read with Autoprecharge
PRE = Precharge
- 8 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
INITIALIZATION
GDDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation.
1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined)
- Apply VDD and VDDQ simultaneously
- Apply VDDQ before Vref. ( Inputs are not recognized as valid until after VREF is applied )
2. Required minimum 100us for the stable power before RESET pin transition to HIGH
- Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE.
- On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value.
If CKE is sampled at a zero the address termination is set to 1/2 of ZQ.
If CKE is sampled at a one the address termination is set to ZQ.
- RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs will
be in a High-Z state, all active terminators off, and all DLLs off.
4. Minimum 200us delay required prior to applying any executable command after stable power and clock.
5. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be
brought to HIGH,
6. Issue a PRECHARGE ALL command following after NOP command.
7. Issue a dummy MRS command ("00001000100001")
8. Issue a EMRS command (BA1BA0="01") to enable the DLL.
9. Issue MRS command (BA0BA1 = "00") to reset the DLL and to program the operating parameters.
20K clock cycles are required to lock the DLL.
9. Issue a PRECHARGE ALL command
10 . Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers.
Following these requirements, the GDDR3 SDRAM is ready for normal operation.
VDDQ
VDD
VREF
T0
T1
Ta0
Tb0
Tc0
Td0
Te0
Tf0
PRE
Dummy
MRS
EMRS
MRS
PRE
AR
AR
CK
CK
RES
t
CH
tATS
t
t
ATH
IS
t
tCL
IH
CKE
CKE
tIS
COMMAND
t
IH
NOP
ACT
DM
t
IS
tIH
t
CODE
t
IS
ALL BANKS
A0-A7, A9-A11
t
IS
t
t
IS
IH
t
t
IH
IS
CODE
t
IS
RA
t
ALL BANKS
IH
CODE
tIH
BAO=L,
BA1 =L
BA0, BA1
tIH
CODE
CODE
A8
IS
CODE
RA
tIH
t
BAO=H,
BA1 =L
IS
t
IH
BAO=L,
BA1 =L
BA
High
RDQS
High
WDQS
High
DQ
T = 200us
T=10ns
Power-up:
VDD and CK stable
tRP
Precharge
All Banks
tMRD
tMRD
Load Mode Register
(Dummy MRS)
Load Extended
Mode Register
- 9 -
tMRD
20K cycle
Load Mode Register
Precharge
DLL Reset
All Banks
tRP
tRFC
1st
Auto Refresh
tRFC
2nd
Auto Refresh
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
MODE REGISTER SET(MRS)
The mode register stores the data for controlling the various operating modes of GDDR3 SDRAM. It programs CAS
latency, addressing mode, test mode and various vendor specific options to make GDDR3 SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after
EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE (The GDDR3
SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins
A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum six
clock cycles are requested to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state.
The mode register is divided into various fields depending on functionality. The Burst length uses A0 ~ A2. CAS latency
(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A9 ~ A11 are used
for Write latency. Refer to the table for specific codes for various addressing modes and CAS latencies.
BA1
BA0
0
0
A11
A10
WL
A9
A8
A7
A6
DLL
TM
A5
CAS Latency
Test Mode
A4
A3
A2
BT
A1
A0
Burst Length
Burst Type
BA0
An ~ A0
A7
mode
0
MRS
0
Normal
1
EMRS
1
Test
A3
Burst Type
0
Sequential
1
Reserved
0
DLL
Write Latency
A8
Write Latency
Burst Length
DLL Reset
A11
A10
A9
0
0
0
Reserved
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
CAS Latency
1
0
1
5
0
0
0
1
1
0
6
0
0
1
1
1
1
Reserved
0
No
A2
A1
A0
1
Yes
0
0
0
Reserved
0
1
Reserved
1
0
4
1
1
Reserved
1
0
0
Reserved
8
1
0
1
Reserved
9
1
1
0
Reserved
1
1
1
Reserved
CAS Latency
A6
A5
A4
0
1
0
Reserved
0
1
1
Reserved
1
0
0
Reserved
1
0
1
5
1
1
0
6
1
1
1
7
- 10 -
Burst Length
Rev 1.8 (Apr. 2005)
0
256M GDDR3 SDRAM
K4J55323QF-GC
PROGRAMMABLE IMPEDANCE OUTPUT BUFFER AND ACTIVE TERMINATOR
The GDDR3 SDRAM is equipped with programmable impedance output buffers and Active Terminators. This allows a user to match
the driver impedance to the system. To adjust the impedance, an external precision resistor(RQ) is connected between the ZQ pin and
Vss. The value of the resistor must be six times the desired output impedance.
For example, a 240Ω resistor is required for an output impedance of 40Ω. To ensure that output impedance is one sixth the value of RQ
(within 10 %), the range of RQ is 120Ω to 360Ω (20Ω to 60Ω output impedance).
RES, CK and /CK are not internally terminated. CK and /CK will be terminated on the system module using external 1% resisters. The
output impedance is updated during all AUTO REFRESH commands and NOP commands when a READ is not in progress to compensate for variations in supply voltage and temperature. The output impedance updates are transparent to the system. Impedance updates
do not affect device operation, and all data sheet timing and current specifications are met during an update. To guarantee optimum output driver impedance after power-up, the GDDR3(x32) needs 20us after the clock is applied and stable to calibrate the impedance upon
power-up. The user can operate the part with fewer than 20us, but optimal output impedance is not guaranteed. The value of ZQ is also
used to calibrated the internal address/command termination resisters. The two termination values that are selectable at power up are 1/
2 of ZQ and ZQ. The value of ZQ is used to calibrate the internal DQ termination resisters. The two termination values that are selectable are 1/4 of ZQ and 1/2 of ZQ.
BURST LENGTH
Read and write accesses to the GDDR3 SDRAM are burst oriented, with the burst length being programmable, as shown in MRS
table. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst length of 4 only is available. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. The block
is uniquely selected by A2-Ai when the burst length is set to four (Where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmable
burst length applies to both READ and WRITE bursts.
BURST TYPE
Accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit A3.
This device does not support the interleaved burst mode found in DDR SDRAM devices. The ordering of accesses within a burst is
determined by the burst length, the burst type, and the starting column address, as shown in below table: Burst Definition
Burst Definition
Burst
Length
4
Starting Column
Address
A1
A0
0
0
Order of Access
within A burst
Type= Sequential
0-1-2-3
NOTE : 1. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block and must be
set to zero
- 11 -
Rev 1.8 (Apr. 2005)
CAS LATENCY (READ LATENCY)
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
data. The latency can be set to 5~9 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will
be available nominally coincident with clock edge n+m. Below table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
CAS Latency
Allowable operating
Frequency (MHz)
SPEED
CL=9
CL=8
CL=7
CL=6
CL=5
-12
≤ 800
-
-
-
-
-14
≤ 700
-
-
-
-
-16
-
≤ 600
-
-
-
-20
-
-
≤ 500
-
-
T0
/CK
CK
COMMAND
READ
RDQS
DQ
T3
∼ ∼∼ ∼
∼ ∼
∼∼
0
256M GDDR3 SDRAM
K4J55323QF-GC
T0
COMMAND
RDQS
DQ
READ
T5
NOP
NOP
T5
T6
NOP
NOP
T5n
CL = 5
T4
∼ ∼∼ ∼
∼ ∼
∼∼
/CK
CK
NOP
T4
NOP
T6n
CL = 6
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
DON’T CARE
TRANSITIONING DATA
- 12 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
WRITE LATENCY
The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of
input data. The latency can be set from 1 to 6 clocks depending in the operating frequency and desired current draw. When the write
latencies are set to 1 or 2 or 3 clocks, the input receivers never turn off when the WRITE command is registered. If a WRITE command
is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n+m. Reserved
states should not be used as unknown operation or incompatibility with future versions may result.
* Maximum frequency of GDDR3 can be limited in WL4, 5 and 6
T0
T2
T3
NOP
NOP
T2
T3
T4
NOP
NOP
NOP
T1
T3n
/CK
CK
COMMAND
WRITE
NOP
WL = 3
WDQS
DQ
T0
COMMAND
WDQS
DQ
WRITE
∼ ∼ ∼ ∼
∼ ∼ ∼ ∼
/CK
CK
T4n
WL = 4
Burst Length = 4 in the cases shown
DON’T CARE
TRANSITIONING DATA
- 13 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
TEST MODE
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7 set to zero, and bits A0-A6 and A8A11 set to the desired values. Test mode is entered by issuing a MODE REGISTER SET command with bit A7 set to one, and bits A0A6 and A8-A11 set to the desired values. Test mode functions are specific to each Dram Manufacturer and its exact functions are hidden
from the user.
DLL RESET
The normal operating mode is selected by issuing a MODE REGISTER SET command with bit A8 set to zero, and bits A0-A7 and A9A11 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bit A8 set to one, and bits A0A7 and A9-A11 set to the desired values. When a DLL Reset is complete the GDDR3 SDRAM reset bit 8 of the mode register to a zero.
After DLL Reset MRS, Power down can not be issued during 10 clock.
0
- 14 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
EXTENDED MODE REGISTER SET(EMRS)
The extended mode register stores the data output driver strength and on-die termination options. The
extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The GDDR3
SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA0 in the same cycle as CS, RAS, CAS and WE going low are
written in the extended mode register. Six clock cycles are required to complete the write operation in the
extended mode register. 4 kinds of the output driver strength are supported by EMRS (A1, A0) code. The
mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. "High" on BA0 is used for EMRS. Refer to the table for specific
codes.
BA1
BA0
A11
A10
0
1
LP
ID
A9
A8
AL
A7
A6
tWR
DLL
An ~ A0
0
MRS
1
EMRS
A10
A4
tWR
DLL
Vendor ID
BA0
A5
Vendor ID
0
Off
1
On
A3
A2
A1
Termination
A0
Drive Strength
Drive Strength
A6
DLL
A1
A0
Drive Strength
0
Enable
0
0
Autocal
1
Disable
0
1
30Ω
1
0
40Ω
1
1
50Ω
Additive Latency
A9
A8
AL
0
0
0
0
1
1
1
0
Reserved
1
1
Reserved
Low Power
A11
Low Power
tWR
A7
A5
A4
tWR
0
0
0
3
0
0
1
4
0
1
0
5
0
1
1
6
1
0
0
7
1
0
1
Reserved
0
Disable
1
1
0
Reserved
1
Enable
1
1
1
Reserved
Termination
A3
A2
Termination
0
0
ODT Disabled
0
1
Reserved
1
0
ZQ/4
1
1
ZQ/2
* ZQ : Resistor connection pin for On-die termination
- 15 -
Rev 1.8 (Apr. 2005)
0
256M GDDR3 SDRAM
K4J55323QF-GC
DLL ENABLE/DISABLE
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning
to normal operation after disabling the DLL for debugging or evaluation. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled, 20K clock cycles must occur before a READ command can be
issued.
DATA TERMINATION
The Data Termination, DT, is used to determine the value of the internal data termination resisters. The GDDR3 SDRAM
supports 60Ω and 120Ω termination. The termination may also be disabled for testing and other purposes.
DATA DRIVER IMPEDANCE
The Data Driver impedance (DZ) is used to determine the value of the data drivers impedance. When autocalibration is
used the data driver impedance is set to 40Ωs and it’s tolerance is determined by the calibration accuracy of the device.
When any other value is selected the target impedance is set nominally to the desired impedance. However, the accuracy
is now determined by the device’s specific process corner, applied voltage and operating temperature.
ADDITIVE LATENCY
The Additive Latency function (AL) is used to optimize the command bus efficiency. The AL value is used to determine the
number of clock cycles that is to be added to CL after CAS is captured by the rising edge of CK. Thus the total CAS latency
is determined by adding CL and AL.
MANUFACTURERS VENDOR CODE AND REVISION IDENTIFICATION
The Manufacturers Vendor Code, V, is selected by issuing a EXTENDED MODE REGISTER SET command with bits A10
set to one, and bits A0-A9 and A11 set to the desired values. When the V function is enabled the GDDR3 SDRAM will provide its manufacturers vendor code on DQ[3:0] and revision identification on DQ[7:4]
Manufacturer
DQ[3:0]
Manufacturer
DQ[3:0]
Manufacturer
DQ[3:0]
Reserved
0
Hynix
6
Reserved
C
Samsung
1
Mosel
7
Reserved
D
Infineon
2
Winbond
8
Reserved
E
3
ESMT
9
Micron
F
Etron
4
Reserved
A
Nanya
5
Reserved
B
Elpida
- 16 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
LOW POWER MODE
Low power mode can be enabled by A11="H" during the EMRS command and in this case, Precharge Power
Down command activates LP mode1 and Self Refresh command activates LP mode2. In case that A11 set to
"L" during the EMRS, Low Power mode is disabled and Precharge Power Down command and Self Refresh
command will do normal operation.
If a Precharge Power Down command issued under the condition of Low Power mode enabled, a device
enters the LP mode1 and it can reduce Precharge Power Down current significantly by disabling DLL during
the Precharge Power Down, however it requires more time to exit Power Down. If the power down duration is
less than 20us, the required tPDEX is 300tCK. Otherwise, 20000tCK required for the tPDEX.
If a Self Refresh command issued under the condition of Low Power mode enabled, a device enters the LP
mode2 and it can reduce tXSR while slightly increase the Self Refresh current. If the Self Refresh duration is
less than 20us, the required tXSR is 300tCK. Otherwise, 20000tCK required for the tXSR.
Low Power
Command
Disabled
(A11="L" @ EMRS)
Enabled
(A11="H" @ EMRS)
Precharge Power Down
Precharge Power Down
LP Mode1
Self Refresh
Self Refresh
LP Mode2
0
- 17 -
Comments
. DLL disabled for the purpose of current
saving ( ICC2P minimized)
. tPDEX increased
- [email protected] power down exit within 20us
- [email protected] power down exit after 20us
. Short tXSR
- [email protected] Self Refresh exit within 20us
- [email protected] Self Refresh exit after 20us
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
COMMANDS
Below Truth table-COMMANDs provides a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables appear following the operation section : these tables provide current
state/next state information.
TRUTH TABLE - COMMANDs
Name (Function)
CS
RAS
CAS
WE
ADDR
NOTES
DESELECT (NOP)
H
X
X
X
X
8, 11
NO OPERATION (NOP)
L
H
H
H
X
8
ACTIVE (Select bank and activate row)
L
L
H
H
Bank/Row
3
READ (Select bank and column, and start READ burst)
L
H
L
H
Bank/Col
4
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L
Bank/Col
4
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
Code
5
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
L
L
L
H
X
6, 7
LOAD MODE REGISTER
L
L
L
L
Op-Code
2
DATA TERMINATOR DISABLE
X
H
L
H
X
TRUTH TABLE - DM Operation
Name (Function)
DM
DQS
Write Enable
L
Valid
Write Inhibit
H
X
Note :
NOTES
10
1. CKE is HIGH for all commands except SELF REFRESH.
2. BA0~BA1 select either the mode register or the extended mode register (BA0=0, BA1=0 select the mode register;
BA0=1, BA1=0 select extended mode register; other combinations of BA0~BA1 are reserved). A0~A11 provide the op-code
to be written to the selected mode register.
3. BA0~BA1 provide bank address and A0~A11 provide row address.
4. BA0~BA1 provide bank address; A0~A7 and A9 provide column address; A8 HIGH enables the auto precharge feature
(nonpersistent) , and A8 LOW disables the auto precharge feature.
5. A8 LOW : BA0~BA1 determine which bank is precharged.
A8 HIGH : All banks are precharged and BA0~BA1 are "Don’t Care."
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; ll inputs and I/Os are "Don’t Care" except for CKE.
8. DESELECT and NOP are functionally interchangeable.
9. Cannot be in powerdown or self-refresh state.
10. Used to mask write data ; provided coincident with the corresponding data.
11. Except DATA Termination disable.
- 18 -
Rev 1.8 (Apr. 2005)
0
256M GDDR3 SDRAM
K4J55323QF-GC
DESELECT
The DESELECT function (/CS high) prevents new commands from being executed by the DDR(x32). The GDDR3(x32)
SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct selected GDDR3(x32) to perform a NOP (/CS LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not
affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A0-A11. See mode register descriptions in the Register Definition section. The
Load Mode Register command can only be issued when all banks are idle, and a subsequent executable command cannot
be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the
BA0,BA1 inputs selects the bank, and the address provided on inputsA0-A11 selects the row. This row remains active (or
open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0-A7, A9 selects the starting column location. The value on input A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at
the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-A7, A9 selects the starting column location. The value on inputs A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at
the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input
data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the
data. If a given DM signal is registered LOW. the corresponding data will be written to memory; If the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued.
Input A8 determines whether one or all banks are to be precharged, and in the case where only one banks are to be precharged, inputs BA0,BA1 select the bank. Otherwise BA0, BA1 are treated as "Don’t Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE command will be treated as a NOP if
there is no open row is already in the process of precharging.
- 19 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
AUTO PRECHARGE
Auto precharge is a feature which performs the same individual-bank precharge function described above, but without
requiring an explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific
READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either
enable or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated
at the earliest valid state within a burst. This "earliest valid stage" is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating tRAS(min), as described for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the precharge time(tRP) is completed.
AUTO REFRESH
Auto Refresh is used during normal operation of the GDDR3 SDRAM and is analogous to /CAS-BEFORE-/RAS (CBR)
REFRESH in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. The
addressing is generated by the internal refresh controller. This makes the address bits a "Don’t Care" during an Auto
Refresh command. The 256Mb(x32) DDR2(x32) requires Auto Refresh cycles at an average interval of 7.8us (maximum).
A maximum of eight Auto Refresh commands can be posted to any given GDDR3(x32) SDRAM, meaning that the maximum absolute interval between any Auto Refresh command and the next Auto Refresh command is 9 x 7.8us(70.2us).
This maximum absolute interval is to allow GDDR3(x32) SDRAM output drivers and internal terminators to automatically
recalibrate compensating for voltage and temperature changes.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the GDDR3(x32) SDRAM ,even if the rest of the system is
powered down. When in the self refresh mode,the GDDR3(x32) SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled and reset upon exiting SELF REFRESH. The
active termination is also disabled upon entering Self Refresh and enabled upon exiting Self Refresh. (200 clock cycles
must then occur before a READ command can be issued). Input signals except CKE are "Don’t Care" during SELF
REFRESH. The procedure for exiting self refresh requires a sequence of commands. First, CK and /CK must be stable
prior to CKE going back HIGH. Once CKE is HIGH,the GDDR3(x32) must have NOP commands issued for tXSNR
because tine is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh,
DLL requirements and out-put calibration is to apply NOPs for 200 clock cycles before applying any other command to
allow the DLL to lock and the output drivers to recalibrate.
DATA TERMINATOR DISABLE
(BUS SNOOPING FOR READ COMMAND)
The DATA TERMINATOR DISABLE COMMAND is detected by the device by snooping the bus for READ commands
excluding /CS. The GDDR3 DRAM will disable its Data terminators when a READ command is detected. The terminators
are disable CL-1 Clocks after the READ command is detected. In a two rank system both dram devices will snoop the bus
for READ commands to either device and both will disable their terminators if a READ command is detected. The command and address terminators and always enabled.
- 20 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
ON-DIE TERMINATION
Bus snooping for READ commands other than /CS is used to control the on-die termination. The GDDR3 SDRAM will disable the on-die termination when a READ command is detected, regardless of the state of /CS. The on-die termination is
disabled x clocks after the READ command where x equals CL-1 and stay off for a duration of BL/2 + 2, as below figure,
Data Termination Disable Timing. In a two-rank system, both DRAM devices snoop the bus for READ commands to either
device and both will disable the on-die termination if a READ command is detected. The on-die termination for all other
pins on the device are always on for both a single-rank system and a dual-rank system.
The on-die termination value on address and control pins is determined during power-up in relation to the state of CKE on
the first transition of RESET. On the rising edge of RESET, if CKE is sampled LOW, then the configuration is determined to
be a single-rank system. The on-die termination is then set to one-half ZQ for the address pins. On the rising edge of
RESET, if CKE is sampled HIGH, then the configuration is determined to be a dual-rank system. The on-die termination for
the DQs, WDQS, and DM pins is set in the EMRS.
Data Termination Disable Timing
T0
T7
T8
T8n
NOP
NOP
T9
T9n
T10
T11
NOP
NOP
∼
∼
∼
∼
CK#
CK
∼
∼
READ
ADDRESS
Bank a,
Col n
NOP
∼
∼
COMMAND
∼
∼
∼
∼
∼
∼
CL = 8
RDQS
∼
∼
DQ
DQ
TERMINATION
DO
n
GDDR3 Data Termination is Disabled
DON’T CARE
TRANSITIONING DATA
Note : 1. DO n = data-out from column n.
2. Burst length = 4.
3. Three subsequent elements of data-out appear in the specified order following DO n.
4. Shown with nominal tAC and tDQSQ.
5. RDQS will start driving high one-half cycle prior to the first falling edge.
6. The Data Terminators are disabled starting at CL-1 and the duration is BL/2 + 2
7. READS to either rank disable both ranks’ termination regardless of the logic level of /CS.
- 21 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
OPERATIONS
BANK/ROW ACTIVATION
/CK
CK
Before any READ or WRITE commands can be issued to a banks within the GDDR3 SDRAM,
a row in that bank must be "opened." This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated.
After a row is opened with an ACTIVE command, a READ or WRITE command may be issued
to that row, subject to the tRCD specification. tRCD(min) should be divided by the clock period
and rounded up to the next whole number to determine the earliest clock edge after the
ACTIVE command in which a READ or WRITE command can be entered. For example, a tRCD
specification of 16ns with a 450MHz clock (2.2ns period) results in 7.2 clocks rounded to 8.
This is reflected in below figure, which covers any case where 7<tRCD(min)/tCK≤ 8.
The same procedure is used to convert other specification limits from tome units to clock
cycles).
A subsequent ACTIVE command to a different row in the same bank can only be issued after
the previous active row has been "closed"(precharged). The minimum time interval between
successive ACTIVE commads to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
CKE
HIGH
/CS
/RAS
/CAS
/WE
A0-A11
RA
BA0,1
BA
RA = Row Address
BA = Bank Address
Activating a Specific Row
in a Specific Bank
Example : Meeting tRCD
T1
T2
T3
T4
ACT
NOP
NOP
ACT
NOP
T7
T8
T9
NOP
RD/WR
NOP
∼
∼
T0
/CK
∼
∼
CK
∼
∼
COMMAND
∼
∼
∼
∼
A0-A11
Bank x
Bank y
∼
∼ ∼
∼
Row
∼
∼
BA0, BA1
Row
Col
Bank y
tRCD
tRRD
DON’T CARE
- 22 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
READs
READ bursts are initiated with a READ command, as below figure. The starting column and bank addresses are provided with the READ command and
auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is prechrged at the completion of
the burst after tRAS(min) has been met. For the generic READ commands used
in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column
address will be available following the CAS Latency after the READ command. Each subsequent data-out element will be valid nominally at the next
positive or negative strobe edge. READ burst figure shows general timing for
2 of the possible CAS latency settings. The GDDR3(x32) drives the output
data edge aligned to the crossing of CK and /CK and to RDQS. The initial
HIGH transitioning LOW of RDQS is known as the read preamble ; the half
cycle coincident with the last data-out element is known as the read postamble.
/CK
CK
CKE
HIGH
/CS
/RAS
/CAS
/WE
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A detailed explanation of tDQSQ (valid data-out
skew), tDV (data-out window hold), the valid data window are depicted in Data
Output Timing (1) figure. A detailed explanation of tAC (DQS and DQ transition
skew to CK) is shown in Data Output Timing (2) figure.
Data from any READ burst may be concatenated with data from a subsequent READ command. A continuous flow of data can be maintained. The
first data element from the new burst follows the last element of a completed
burst. The new READ command should be issued x cycles after the first
READ command, where x equals the number of data element nibbles (nibbles
are required by the 4n-prefetch architecture) depending on the burst length.
This is shown in consecutive READ bursts figure. Nonconsecutive read data
is shown for illustration in nonconsecutive READ bursts figure. Full-speed
random read accesses within a page (or pages) can be performed as shown
in Random READ accesses figure. Data from a READ burst cannot be terminated or truncated.
During READ commands the GDDR3 Dram disables its data terminators.
A0-A7, A9
CA
A10, A11
EN AP
A8
DIS AP
BA0,1
BA
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
READ Command
- 23 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
Data Output Timing (1) - tDQSQ, tQH and Data Valid Window
T0
T1
T2
T2n
T3
T3n
T4
CK#
CK
tCH
tCL
tDQSQ2 (MAX)
tDQSQ2 (MAX)
2
RDQS
tDQSQ2 (MIN)
tDQSQ (MIN)
1.6
tDQSH4
DQ(Last data valid)
tDQSH4
T2
DQ(First data no longer valid)
T2
All DQs and RDQS, collectively5
T3
T2n
T3n
T3
T2n
T3n
T2
T2n
T3
T3n
tDV4
tDV4
tDV4
tDV4
Data Output Timing (2) - tDQSQ, tQH and Data Valid Window
T0
T1
T2
T2n
T3
T3n
tDQSH4
tDQSH4
T2n
T3
T4
CK#
CK
tCH
tCL
tAC(MAX)
RDQS 1.6
All DQs and RDQS, collectively5
T2
RDQS 1.6
T3n
tAC(MIN)
All DQs and RDQS, collectively5
T2
tDQSH4
tDQSH4
T2n
T3
T3n
Note : 1. tDQSQ represents the skew between the 8 DQ lines and the respective RDQS pin.
2. tDQSQ is derived at each RDQS clock edge and is not cumulative over time and begins with first DQ transition and ends
with the last valid transition of DQs.
3. tAC is show in the nominal case
4. tDQHP is the lesser of tDQSL or tDQSH strobe transition collectively when a bank is active.
5. The data valid window is derived for each RDQS transitions and is defined by tDV.
6. There are 4 RDQS pins for this device with RDQS0 in relation to DQ0-DQ7, RDQS1 in relation DQ8-DQ15, RDQS2 in
relation to DQ16-24 and RDQS3 in relation to DQ25-DQ31.
7. This diagram only represents one of the four byte lanes.
8. tAC represents the relationship between DQ, RDQS to the crossing of CK and /CK.
- 24 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
READ Burst
T0
NOP
NOP
ADDRESS
Bank a,
Col n
CL = 8
RDQS
DQ
∼∼ ∼
∼∼
∼
READ
∼
∼
COMMAND
T0
T8n
T9
T9n
COMMAND
ADDRESS
Bank a,
Col n
CL = 9
∼ ∼∼ ∼
∼ ∼
∼ ∼
READ
NOP
T11
NOP
NOP
T10
T11
NOP
NOP
DO
n
T7
T8
T9
NOP
NOP
NOP
T9n
DO
n
DON’T CARE
NOTE :
T10
∼
∼
/CK
CK
DQ
T8
∼
∼
/CK
CK
RDQS
T7
TRANSITIONING DATA
1. DO n=data-out from column n.
2. Burst length = 4
3. Three subsequent elements of data-out appear in the programmed order following DQ n.
4. Shown with nominal tAC and tDQSQ.
5. RDQS will start driving high 1/2 clock cycle prior to the first falling edge.
- 25 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
Consecutive READ Bursts
T1
T2
COMMAND
READ
NOP
READ
ADDRESS
Bank a,
Col n
/CK
CK
∼ ∼
∼ ∼
T0
RDQS
∼∼
∼∼
DQ
∼
∼
Bank a,
Col b
CL = 8
T8
T8n
NOP
T9
T9n
NOP
T10
NOP
DO
n
DON’T CARE
T10n
DO
b
TRANSITIONING DATA
NOTE : 1. DO n (or b) = data-out from column n (or column b).
2. Burst length = 4
3. Three subsequent elements of data-out appear in the programmed order following DQ n.
4. Three subsequent elements of data-out appear in the programmed order following DQ b.
5. Shown with nominal tAC and tDQSQ.
6. Example applies when READ commands are issued to different devices or nonconsecutive READs.
7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
- 26 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
Nonconsecutive READ Bursts
T0
T18
READ
NOP
NOP
NOP
Bank a,
Col b
∼
∼
∼
∼
∼
∼
∼
∼
DQ
T17n
∼
∼
RDQS
T17
∼
∼
CL = 8
T10
∼
∼
Bank a,
Col n
NOP
T9n
∼
∼
ADDRESS
NOP
T9
∼
∼
READ
T8n
∼∼
∼∼
COMMAND
T8
∼ ∼
∼ ∼
/CK
CK
T7
DO
n
DO
b
DON’T CARE
TRANSITIONING DATA
NOTE : 1. DO n (or b) = data-out from column n (or column b).
2. Burst length = 4
3. Three subsequent elements of data-out appear in the programmed order following DQ n.
4. Three subpsequent elements of data-out appear in the programmed order following DQ b.
5. Shown with nominal tAC and tDQSQ.
6. Example applies when READ commands are issued to different devices or nonconsecutive READs.
7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
- 27 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
Random READ Accesses
T1
T2
COMMAND
READ
NOP
READ
ADDRESS
Bank a,
Col n
/CK
CK
T8
∼ ∼
∼ ∼
T0
RDQS
∼∼
∼∼
DQ
∼
∼
Bank a,
Col b
CL = 8
COMMAND
READ
NOP
ADDRESS
Bank a,
Col n
/CK
CK
CL = 8
RDQS
DO
n
T8
READ
NOP
T9n
T10
NOP
DO
n
T8n
T10n
NOP
DO
n
T9
DO
n
T9n
DO
b
T10
NOP
T10n
NOP
Bank a,
Col b
DO
n
DON’T CARE
NOTE :
T9
NOP
T7
∼
∼
DQ
∼∼
∼∼
T1
∼ ∼
∼ ∼
T0
T8n
DO
n
DO
n
DO
n
TRANSITIONING DATA
1. DO n (or x or b or g) = data-out from column n (or column x or column x or column b or column g).
2. Burst length = 4
3. n’ or x or b’ or g’ indicates the next data-out following DO n or DO x or DO b OR DO g, respectively
4. READs are to an active row in any bank.
5. Shown with nominal tAC and tDQSQ.
6. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
- 28 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
READ to WRITE
COMMAND
READ
ADDRESS
Bank
Col n
RDQS
∼
∼ ∼ ∼∼
∼ ∼
∼
T0
/CK
CK
T7
T8
T8n
NOP
WRITE
T9
T9n
NOP
T10
T11
T12
NOP
NOP
NOP
T12n
Bank a,
Col b
CL = 8
tWL = 4
DQ
∼∼
∼∼
WDQS
DM
∼
∼
DQ
Termination
DI
b
DO
n
∼
∼
DQ Termination Disabled
1tCK <
DON’T CARE
NOTE :
DQ Termination Enbaled
TRANSITIONING DATA
1. DO n = data-out from column n.
2. DI b = data-in from column b.
3. Burst length = 4
4. One subsequent element of data-out appears in the programmed order following DO n.
5. Data-in elements are applied following DI b in the programmed order.
6. Shown with nominal tAC and tDQSQ.
7. tDQSS in nominal case.
8. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
9. The gap between data termination enable to the first data-in should be greater than 1tCK
- 29 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
READ to PRECHARGE
T1
T2
COMMAND
READ
NOP
PRE
ADDRESS
Bank a,
Col n
Bank a
T8n
NOP
T9
NOP
T9n
T10
ACT
Bank a,
Row
∼
∼
CL = 8
T8
∼
∼ ∼ ∼
∼ ∼
T0
/CK
CK
tRP
RDQS
∼
∼
DQ
DO
n
DON’T CARE
TRANSITIONING DATA
NOTE : 1. DO n (or b) = data-out from column n (or column b).
2. Burst length = 4
3. Three subsequent elements of data-out appear in the programmed order following DQ n.
4. Read to precharge equals two clocks, which enables two data pairs of data-out.
5. Shown with nominal tAC and tDQSQ.
6. Example applies when READ commands are issued to different devices or nonconsecutive READs.
7. RDQS will start driving high one half-clock cycle prior to the first falling edge of RDQS.
- 30 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure.
The starting column and bank addresses are provided with the WRITE
command, and auto precharge is either enabled or disabled for that
access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands
used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered in a
rising edge of WDQS following the WRITE latency set in the mode register
and subsequent data elements will be registered on successive edges of
WDQS. Prior to the first valid WDQS edge a half cycle is needed and specified as the WRITE Preamble; the half cycle in WDQS following the last
data-in element is known as the write postamble.
The time between the WRITE command and the first valid falling edge of
WDQS (tDQSS) is specified with a relative to the write latency. All of the
WRITE diagrams show the nominal case, and where the two extreme
cases (i.e., tDQSS(min) and tDQSS(max)) might not be intuitive, they have also
been included. Write Burst figure shows the nominal case and the
extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming
no other commands have been initiated, the DQs will remain High-Z and
any additional input data will be ignored. Data for any WRITE burst may not
be truncated with a subsequent WRITE command. The new WRITE command can be issued on any positive edge of clock following the previous
WRITE command after the burst has completed. The new WRITE command should be issued x cycles after the first WRITE command should be
equals the number of desired nibbles (nibbles are required by 4n-prefetch
architecture).
An example of nonconsecutive WRITEs is shown in Nonconsecutive
WRITE to READ figure. Full-speed random write accesses within a page or
pages can be performed as shown in Random WRITE cycles figure. Data
for any WRITE burst may be followed by a subsequent READ command.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE the WRITE burst, tWR should be
met as shown in WRITE to PRECHARGE figure.
Data for any WRITE burst can not be truncated by a subsequent PRECHARGE command.
- 31 -
/CK
CK
CKE
HIGH
/CS
/RAS
/CAS
/WE
A0-A7, A9
CA
A10, A11
EN AP
A8
DIS AP
BA0,1
BA
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
WRITE Command
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
Bank a,
Col b
T3n
T4
T4n
T5
T5n
T6
/CK
CK
tDQSS(NOM)
NOP
NOP
NOP
tDQSS
WDQS
DI
b
DI
b
DQ
DI
b
DI
b
DM
tDQSS(MIN)
tDQSS
WDQS
DI
b
DQ
DI
b
DI
b
DI
b
DM
tDQSS(MAX)
tDQSS
WDQS
DI
b
DQ
DI
b
DI
b
DI
b
DM
DON’T CARE
NOTE :
TRANSITIONING DATA
1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. A burst of 4 is shown.
4. A8 is LOW with the WRITE command (auto precharge is disabled).
5. Write latency is set to 4
- 32 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
Consecutive WRITE to WRITE
T0
T1
T2
T3
COMMAND
WRITE
NOP
WRITE
NOP
ADDRESS
Bank
Col b
T3n
T4
T4n
T5
T5n
T6
T6n
T7
CK#
CK
NOP
NOP
NOP
NOP
Bank
Col n
tDQSS (NOM)
WDQS
DQ
DI
b
DI
b
DI
b
DI
b
DI
n
DI
n
DI
n
DI
n
DM
DON’T CARE
NOTE :
TRANSITIONING DATA
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. Burst of 4 is shown.
5. Each WRITE command may be to any bank of the same device.
6. Write latency is set to 3
- 33 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
Nonconsecutive WRITE to WRITE
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
WRITE
ADDRESS
Bank,
Col b
T3n
T4
T4n
T5
T5n
T6
T6n
T7
/CK
CK
NOP
NOP
NOP
NOP
Bank,
Col n
tDQSS (NOM)
WDQS
DQ
DI
b
DIDON’TDICAREDI
b
b
b
DI
n
DI
n
DI
n
DM
DON’T CARE
NOTE :
TRANSITIONING DATA
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. burst of 4 is shown.
5. Each WRITE command may be to any bank.
6. Write latency is set to 3
- 34 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
Random WRITE Cycles
T0
T1
T2
T3
COMMAND
WRITE
NOP
WRITE
NOP
ADDRESS
Bank
Col b
T3n
T4
T4n
T5
T5n
T6
T6n
T7
/CK
CK
WRITE
Bank
Col x
NOP
NOP
NOP
Bank
Col g
tDQSS (NOM)
WDQS
DQ
DI
b
DI
b
DI
b
DI
b
DI
x
DI
x
DI
x
DI
x
DI
g
DI
g
DM
DON’T CARE
NOTE :
TRANSITIONING DATA
1. DI b, etc. = data-in for column b, etc.
2. b: etc. = the next data - in following DI b. etc., according to the programmed burst order.
3. Programmed burst length = 4 cases shown.
4. Each WRITE command may be to any bank.
5. Last write command will have the rest of the nibble on T8 and T8n
6. Write latency is set to 3
- 35 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
WRITE to READ
T2
T3
COMMAND
WRITE
NOP
WRITE
NOP
ADDRESS
Bank
Col b
T3n
T4
T4n
T5
T6
NOP
NOP
CK
NOP
Bank
Col b
tCDLR = 5
tDQSS (NOM)
tDQSS
WDQS
DI
b
DQ
DM
RDQS
T19
NOP
NOP
T19n
CL = 9
DI
n
RDQS
∼ ∼∼∼
∼ ∼∼∼
DM
tDQSS
DI
n
CL = 9
DI
b
DM
RDQS
∼
∼ ∼ ∼∼
∼∼
∼
∼
∼ ∼ ∼∼
∼∼
∼
WDQS
NOTE :
T18
CL = 9
DI
b
DQ
DQ
Bank a.
Col n
tDQSS
WDQS
tDQSS (MAX)
READ
∼ ∼∼∼
∼ ∼∼∼
tDQSS (MIN)
T10
∼ ∼ ∼∼ ∼ ∼ ∼∼
∼ ∼ ∼∼ ∼ ∼ ∼∼
T1
∼ ∼ ∼∼ ∼ ∼ ∼∼
∼ ∼ ∼∼ ∼ ∼ ∼∼
T0
/CK
DI
n
DON’T CARE
TRANSITIONING DATA
1. DI b = data-in for column b.
2. Three subsequent elements of data-in the programmed order following DI b.
3. A burst of 4 is shown.
4. tCDLR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be
to different devices, in which case tCDLR is not required and the READ command could be applied earlier.
6. A8 is LOW with the WRITE command (auto precharge is disabled).
7. WRITE latency is set to 3
- 36 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
WRITE to PRECHARGE
T1
T2
T3
COMMAND
WRITE
NOP
WRITE
NOP
ADDRESS
Bank
Col b
T3n
T4
T4n
T5
CK
tDQSS (NOM)
NOP
Bank
Col b
DM
T13
T14
NOP
tWR
PRE
NOP
tRP
NOP
∼ ∼ ∼
∼ ∼ ∼
DI
b
DQ
DM
tDQSS
∼ ∼ ∼
∼ ∼
∼
WDQS
DI
b
DM
DON’T CARE
NOTE :
Bank
tDQSS
WDQS
DQ
T12
∼ ∼ ∼
∼ ∼ ∼
DI
b
DQ
tDQSS (MAX)
T11
tDQSS
WDQS
tDQSS (MIN)
NOP
∼ ∼ ∼
∼ ∼ ∼
T0
/CK
TRANSITIONING DATA
1. DI b = data-in for column b.
2. Three subsequent elements of data-in the programmed order following DI b.
3. A burst of 4 is shown.
4. A8 is LOW with the WRITE command (auto precharge is disabled).
5. WRITE latency is set to 3
- 37 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
PRECHARGE
/CK
The PRECHARGE command is used to deactivate the open row in a
particular bank or the open row in all banks. The bank(s) will be available
for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A8 determines whether one or all
banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. When all banks are to
be precharged, inputs BA0, BA1 are treated as "Don’t Care." Once a
bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to the bank.
CK
CKE
HIGH
/CS
/RAS
/CAS
POWER-DOWN (CKE NOT ACTIVE)
Unlike SDRAMs,GDDR3(x32) SDRAM requires CKE to be active at all
times an access is in progress; from the issuing of a READ or WRITE
command until completion of the burst. For READs, a burst completion is
defined when the Read Postamble is satisfied; For WRITEs, a burst
completion is defined BL/2 cycles after the Write Postamble is satisfied.
/WE
A0-A7, A9-A11
ALL BANKS
A8
Power-down is entered when CKE is registered LOW. If power-down
occurs when there is a row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates the input and output buffers, excluding CK,/CK and CKE. For maximum power savings,
the user has the option of disabling the DLL prior to entering powerdown. However, power-down duration is limited by the refresh requirements of the device, so in most applications,the self-refresh mode is preferred over the DLL-disabled power-down mode.
ONE BANK
BA0,1
BA
DON’T CARE
BA=Bank Address
(if A8 is LOW; otherwise "Don’t Care")
PRECHARGE Command
When in power-down, CKE LOW and a stable clock signal must be
maintained at the inputs of the GDDR3 SDRAM, while all other input signals are "Don’t Care."
The power-down state is synchronously exited when CKE is registered
HIGH (in conjunction with a NOP or DESELECT command). A valid executable command may be applied six clock cycle later.
Power-Down
T0
T1
Ta0
T2
Ta1
Ta2
Ta7
/CK
CK
tIS
tIS
tPDEX
CKE
COMMAND
VALID
No PEAD/WRITE
access in progress
NOP
NOP
NOP
Enter power - down mode
- 38 -
NOP
VALID
Exit power - down mode
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
TRUTH TABLE - Clock Enable (CKE)
CKEn-1
CKEn
L
L
L
H
CURRENT STATE
COMMANDn
ACTIONn
NOTES
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
Power-Down
DESELECT or NOP
Exit Power-Down
Self Refresh
DESELECT or NOP
Exit Self Refresh
All Banks Idle
DESELECT or NOP
Precharge Power-Down Entry
Bank(s) Active
DESELECT or NOP
Active Power-Down Entry
All Banks Idle
AUTO REFRESH
Self Refresh Entry
H
L
5
NOTES :
1. CKEn is the logic state of CKE at clock edge n; CKEn-1was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR2(x32) immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn
4. All state and sequence not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSA period.
- 39 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK n
CURRENT STATE
Any
/CS
/RAS /CAS
/WE
COMMAND/ ACTION
NOTES
H
X
X
X
DESELECT (NOP/ continue previous operation)
13
L
H
H
H
NO OPERATION (NOP/continue previous operation)
X
H
L
H
DATA TERMINATOR DISABLE
L
L
H
H
ACTIVE (Select and activate row)
L
L
L
H
AUTO REFRESH
7
L
L
L
L
LOAD MODE REGISTER
7
L
H
L
H
READ (Select column and start READ burst)
10
L
H
L
L
WRITE (Select Column and start WRITE burst)
10
L
L
H
L
PRECHARGE (Deactivate row in bank or banks)
8
L
H
L
H
READ (Select column and start new READ burst)
10
L
H
L
L
WRITE (Select column and start WRITE burst)
L
L
H
L
PRECHARGE (Only after the READ burst is complete)
L
H
L
H
READ (Select column and start READ burst)
L
H
L
L
WRITE (Select column and start new WRITE burst)
L
L
H
L
PRECHARGE (Only after the WRITE burst is complete)
Idle
Row Active
Read
(Auto-Precharge
Disable)
Write
(Auto-Precharge
Disabled)
10, 12
8
10, 11
10
8, 11
NOTES :
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see CKE Truth Table) and after tXSNR has been met
(if the previous state was self refresh).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.
3. Current state definitions :
Idle : The bank has been precharged, and tRP has been met.
Row Active : A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read : A READ burst has been initiated, with auto precharge disabled.
Write : A WRITE burst has been initiated, with auto precharge disabled.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP
commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and truth table- current state bank n command to bank n. and according to truth table - current state bank n -command to bank m.
Precharging : Starts with registration of a PRECHARGE command and ends when tRP is met.
Once tRP is met, the bank will be in the idle state.
Row Activating : Starts with registration of an ACTIVE command and ends when tRCD is met.
Once tRCD is met, the bank will be in the :row active" state.
- 40 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
Read w/ Auto- : Starts with registration of an READ command with auto precharge enabled and ends
Precharge Enabled when tRP has been met. Once tRP is met, the bank will be in the idle state.
Write w/ Auto- : Starts with registration of a WRITE command with auto precharge enabled and ends
Precharge Enabled when tRP has been met. Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command ; COMMAND INHIBIT or NOP commands
must be applied on each positive clock edge during these states.
Refreshing : Starts with registration of an AUTO REFRESH command and ends when tRC is met.
Once tRC is met, the DDR2(x32) will be in the all banks idle state.
Accessing Mode : Starts with registration of a LOAD MODE REGISTER command and ends when tMRD
Register has been met. Once tMRD is met, the GDDR3(x32) SDRAM will be in the all banks idle state.
Precharge All : Starts with registration of a PRECHARGE ALL command and ends when tRP is met.
Once tRP is met, all banks will be in the idle state.
READ or WRITE : Starts with registration of the ACTIVE command and ends the last valid data nibble.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific ; If multiple banks are to be precharged, each must be in a valid state for precharging.
9. Left blank
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled
and READs or WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst.
13. Except data termination disable.
- 41 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK m
CURRENT STATE
Any
Idle
Row Activating,
Active, or
Prechrging
Read
(Auto-Precharge
Disable)
Write
(Auto-Precharge
Disabled)
Read
(With
Auto-Precharge)
Write
(With
Auto-Precharge)
/CS
/RAS /CAS
/WE
COMMAND/ ACTION
NOTES
H
X
X
X
DESELECT (NOP/ continue previous operation)
8
L
H
H
H
NO OPERATION (NOP/continue previous operation)
X
H
L
H
DATA TERMINATOR DISABLE
X
X
X
X
Any Command Otherwise Allowed to Bank m
L
L
H
H
ACTIVE (Select and activate row)
L
H
L
H
READ (Select column and start READ burst)
6
L
H
L
L
WRITE (Select Column and start WRITE burst)
6
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (Select and activate row)
L
H
L
H
READ (Select column and start new READ burst)
6
L
H
L
L
WRITE (Select column and start WRITE burst)
6
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (Select and activate row)
L
H
L
H
READ (Select column and start READ burst)
L
H
L
L
WRITE (Select column and start new WRITE burst)
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (Select and activate row)
L
H
L
H
READ (Select column and start new READ burst)
6
L
H
L
L
WRITE (Select column and start WRITE burst)
6
L
L
H
L
PRECHARGE
L
L
H
H
ACTIVE (Select and activate row)
L
H
L
H
READ (Select column and start READ burst)
6
L
H
L
L
WRITE (Select column and start new WRITE burst)
6
L
L
H
L
PRECHARGE
6, 7
6
NOTES :
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see TRUTH TABLE- CKE ) and after tXSNR has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
- 42 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
3. Current state definitions :
Idle : The bank has been precharged, and tRP has been met.
Row Active : A row in the bank has been activated, and tRCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read : A READ burst has been initiated, with auto precharge disabled.
Write : A WRITE burst has been initiated, with auto precharge disabled.
Read w/ Auto- : See following text
Precharge Enabled
Write w/ Auto- : See following text
Precharge Enabled
3a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two
parts : the access period and the precharge period. For read with auto precharge, the precharge period is defined
as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge
period begins when tWR ends, with tWR command and ends where the precharge period (or tRP) begins.
During the precharge period of the read with auto precharge enabled or write with auto precharge enabled states,
ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other
related Limitations apply (e.g., contention between read data write data must be avoided).
3b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different
bank is summarized below.
From Command
To Command
Minimum delay (with concurrent auto precharge)
READ or READ w/AP
[WL + (BL/2)] tCK + tCDLR
WRITE or WRITE w/AP
(BL/2) * tCK
WRITE w/AP
PRECHARGE
1 tCK
ACTIVE
1 tCK
READ or READ w/AP
(BL/2) * tCK
WRITE or WRITE w/AP
[CLRU + (BL/2)] + 1 - WL * tCK
READ w/AP
PRECHARGE
1 tCK
ACTIVE
1 tCK
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. All states and sequences not shown are illegal or reserved.
6. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and
READs or WRITEs with auto precharge disabled.
7. Requires appropriate DM masking.
8. Except data termination disable
- 43 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
VIN, VOUT
-0.5 ~ VDDQ + 0.5V
V
Voltage on VDD supply relative to Vss
VDD
-0.5 ~ 2.5
V
Voltage on VDDQ supply relative to Vss
VDDQ
-0.5 ~ 2.5
V
Voltage on any pin relative to Vss
TJ
+125
°C
TSTG
-55 ~ +150
°C
Power dissipation
PD
TBD
W
Short Circuit Output Current
IOS
50
mA
MAX Junction Temperature
Storage temperature
Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure periods may affect reliability.
POWER & DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to 0°C ≤ Tc ≤ 85°C ; VDD=2.0V + 0.1V, VDDQ=2.0V + 0.1V)
Symbol
Min
Typ
Max
Unit
Note
Device Supply voltage
Parameter
VDD
1.9
2.0
2.1
V
1
Output Supply voltage
VDDQ
1.9
2.0
2.1
V
1
Reference voltage
VREF
0.69*VDDQ
-
0.71*VDDQ
V
3
VIH (DC)
VREF+0.15
-
-
V
4
4
DC Input logic high voltage
DC Input logic low voltage
VIL (DC)
-
-
VREF-0.15
V
Output logic low voltage
VOL(DC)
-
-
0.76
V
AC Input logic high voltage
VIH(AC)
VREF+0.25
-
-
V
4,5,6
AC Input logic low voltage
VIL(AC)
-
-
VREF-0.25
V
4,5,6
II
-5
-
5
uA
IIOZ
-5
-
5
uA
Input leakage current
Any input 0V-<VIN -< VDDQ
(All other pins not under test = 0V)
Output leakage current
(DQs are disabled ; 0V-<VOUT -< VDDQ)
Note : 1.Under all conditions, VDDQ must be less than or equal to VDD.
3. VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
VREF may not exceed + 2 percent of the DC value. Thus, from 70% of VDDQ, VREF is allowed + 25mV for DC error and an additional +25mV
for AC noise.
4. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain
a valid level. The inputs require the AC value to be achieved during signal transition edge and the driver should achieve the same slew rate
through the AC values.
5. Input and output slew rate =3V/ns. If the input slew rate is less than 3V/ns, input timing may be compromised. All slew rate are measured between
Vih and Vil.
DQ and DM input slew rate must not deviate from DQS by more than 10%. If the DQ,DM and DQS slew rate is less than 3V/ns, timing is longer
than referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.
6. VIH overshoot : VIH(max) = VDDQ + 0.5V for a pulse width ≤ 500ps and the pulse width can not be greater than 1/3 of the cycle rate.
VIL undershoot : VIL(min)=0.0V for a pulse width ≤ 500ps and the pulse width can not be greater than 1/3 of the cycle rate.
- 44 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
CLOCK INPUT OPERATING CONDITIONS
Recommended operating conditions (0°C ≤ Tc ≤85°C ; VDD=2.0V + 0.1V, VDDQ=2.0V + 0.1V)
Parameter/ Condition
Symbol
Min
Max
Unit Note
Clock Input Mid-Point Voltage ; CK and /CK
VMP(DC)
1.16
1.36
V
1,2,3
Clock Input Voltage Level; CK and /CK
VIN(DC)
0.42
VDDQ + 0.3
V
2
Clock Input Differential Voltage ; CK and /CK
VID(DC)
0.22
VDDQ + 0.5
V
2,4
Clock Input Differential Voltage ; CK and /CK
VID(AC)
0.22
VDDQ + 0.3
V
4
Clock Input Crossing Point Voltage ; CK and /CK
VIX(AC)
VREF - 0.15
VREF + 0.15
V
3
Note : 1. This provides a minimum of 1.16V to a maximum of 1.36V, and is always 70% of VDDQ
2. For AC operations, all DC clock requirements must be satisfied as well.
3. The value of VIX is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same.
4. VID is the magnitude of the difference between the input level in CK and the input level on /CK.
5. The CK and /CK input reference level (for timing referenced to CK and /CK) is the point at which CK and /CK cross;
the input reference level for signals other than CK and /CK is VREF.
6. CK and /CK input slew rate must be > 3V/ns
1.26V
VDDQ
VREF
60Ω
GDDR3
Z0=60 Ω
ZQ
10pf
240 Ω
Output Load Circuit
Note : 1 . Outputs measured into equivalent load of 10pf at a driver impedance of 40 Ω.
- 45 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted, 0°C ≤ Tc ≤85°C )
Version
Parameter
Symbol
Operating Current
(One Bank Active)
ICC1
Test Condition
Unit
-14
-15
-16
-20
Burst Length=4 tRC ≥ tRC(min). IOL=0mA, tCC=
tCC(min). DQ,DM,DQS inputs changing twice
per clock cycle. Address and control inputs
changing once per clock cycle
505
500
495
485
mA
Precharge Standby Current
in Power-down mode
ICC2P
CKE ≤ VIL(max), tCC= tCC(min)
140
140
135
130
mA
Precharge Standby Current
in Non Power-down mode
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min),tCC= tCC(min)
Address and control inputs changing once per
clock cycle
220
215
200
185
mA
Active Standby Current
power-down mode
ICC3P
CKE ≤ VIL(max), tCC= tCC(min)
175
170
160
145
mA
Active Standby Current in
in Non Power-down mode
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min)
DQ,DM,DQS inputs changing twice per clock
cycle. Address and control inputs changing
once per clock cycle
385
380
350
265
mA
ICC4
IOL=0mA ,tCC= tCC(min),
Page Burst, All Banks activated. DQ,DM,DQS
inputs changing twice per clock cycle. Address
and control inputs changing once per clock.
940
935
865
750
mA
ICC5
tRC≥ tRFC
440
435
420
390
mA
Operating Current
( Burst Mode)
Refresh Current
-GC
Self Refresh Current
ICC6
Operating Current
(4Bank interleaving)
-GL
ICC7
CKE ≤ 0.2V
Burst Length=4 tRC ≥ tRC(min). IOL=0mA, tCC=
tCC(min). DQ,DM,DQS inputs changing twice
per clock cycle. Address and control inputs
changing once per clock cycle
1060
20
mA
5
mA
1055
970
950
mA
Note : 1. Measured with outputs open and ODT off
2. Refresh period is 32ms
3. Measured current at VDD & VDDQ = 2.0V
CAPACITANCE (VDD=2.0V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance ( CK, CK )
CIN1
2.0
3.0
pF
Input capacitance (A0~A11, BA0~BA1)
CIN2
2.0
3.0
pF
Input capacitance
( CKE, CS, RAS,CAS, WE )
CIN3
2.0
3.0
pF
Data & DQS input/output capacitance(DQ0~DQ31)
COUT
3.5
4.5
pF
Input capacitance(DM0 ~ DM3)
CIN4
3.5
4.5
pF
- 46 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
AC CHARACTERISTICS - I
Parameter
Symbol
-14
-15
-16
-20
Min
Max
Min
Max
Min
Max
Min
Max
Unit
DQS out access time from CK
tDQSCK
-0.26
+0.26
-0.26
+0.26
-0.29
+0.29
-0.35
+0.35
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCK
1.4
-
3.3
-
1.4
-
3.3
-
1.6
3.3
-
-
ns
ns
-
-
-
-
-
-
2.0
3.3
ns
WRITE Latency
tWL
5
-
5
-
5
-
4
-
tCK
DQ and DM input hold time relative to DQS
tDH
0.18
-
0.18
-
0.20
-
0.25
-
ns
DQ and DM input setup time relative to DQS
tDS
0.18
-
0.18
-
0.20
-
0.25
-
ns
Active termination setup time
tATS
10
-
10
-
10
-
10
-
ns
Active termination hold time
tATH
10
-
10
-
10
-
10
-
ns
DQS input high pulse width
tDQSH
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
DQS input low pulse widthl
tDQSL
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
Data strobe edge to Dout edge
tDQSQ
-
0.160
-
0.160
-
0.180
-
0.225
ns
DQS read preamble
tRPRE
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
Write command to first DQS latching transition
tDQSS
CK low-level width
CK cycle time
CL=9
CL=8
CL=7
WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2 WL-0.2 WL+0.2
Note
1
tCK
tCK
DQS write preamble
tWPRE
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS write preamble setup time
tWPRES
0
-
0
-
0
-
0
-
ns
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
-
tCLmin
or
tCHmin
-
tCLmin
or
tCHmin
-
tCLmin
or
tCHmin
-
tCK
Half strobe period
tHP
tCLmin
or
tCHmin
Data output hold time from DQS
tQH
tHP-0.16
-
tHP-0.16
-
tHP-0.18
-
tHP0.225
-
ns
2
3
Data-out high-impedance window from CK and /CK tHZ
-0.3
-
-0.3
-
-0.3
-
-0.3
-
ns
4
Data-out low-impedance window from CK and /CK tLZ
-0.3
-
-0.3
-
-0.3
-
-0.3
-
ns
4
Address and control input hold time
tIH
0.35
-
0.35
-
0.4
-
0.5
-
ns
Address and control input setup time
tIS
0.35
-
0.35
-
0.4
-
0.5
-
ns
Address and control input pulse width
tIPW
1.0
-
1.0
-
1.1
-
1.3
-
ns
Note : 1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks(this case can be used regardless of fre
quency), the input buffers are turned on during the ACTIVE commands reducing the latency but added power. When the WRITE latency is set to
4 ~7 clocks , the input buffers are turned on during the WRITE commands for lower power operation. The WRITE latency which is over 4 clocks
can be used only in case that Write Latency*tCK is greater than 7ns.
2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be riven high by the controller. WDQS can not be pulled high by
the on-die termination alone.
4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific
voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
- 47 -
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
AC CHARACTERISTICS - II
Parameter
Symbol
-14
-15
-16
Min
Max
Min
Max
-20
Min
Max
Min
Max
Unit
Row active time
tRAS
22
100K
22
100K
19
100K
15
100K
tCK
Row cycle time
tRC
31
-
31
-
27
-
21
-
tCK
Refresh row cycle time
tRFC
39
-
39
-
33
-
27
-
tCK
RAS to CAS delay for Read
tRCDR
10
-
10
-
9
-
7
-
tCK
RAS to CAS delay for Write
tRCDW
6
-
6
-
5
-
4
-
tCK
Row precharge time
tRP
9
-
9
-
8
-
6
-
tCK
Row active to Row active
tRRD
8
-
8
-
7
-
5
-
tCK
Last data in to Row precharge @ Normal precharge
tWR
9
-
9
-
8
-
7
-
tCK
Last data in to Row precharge @ Auto precharge tWR_A
7
Last data in to Read command
tCDLR
5
-
5
-
4
-
3
-
Mode register set cycle time
tMRD
6
-
6
-
5
-
4
-
tCK
Auto precharge write recovery time + Precharge tDAL
18
-
18
-
16
-
13
-
tCK
tXSR
20000
-
20000
-
20000
-
20000
-
tCK
Power-down exit time
tPDEX
6tCK
+tIS
-
6tCK
+tIS
-
6tCK
+tIS
-
4tCK
+tIS
-
tCK
Refresh interval time
tREF
-
7.8
-
7.8
-
7.8
-
7.8
us
Exit self refresh to Read command
7
- 48 -
7
7
Note
tCK
tCK
Rev 1.8 (Apr. 2005)
256M GDDR3 SDRAM
K4J55323QF-GC
PACKAGE DIMENSIONS (FBGA)
A1 INDEX MARK
12.0
12.0
<Top View>
0.8x11=8.8
A1 INDEX MARK
0.10 Max
0.8
B
C
D
E
F
G
H
J
K
L
M
N
0.40
0.8x11=8.8
0.45 ± 0.05
0.8
13 12 11 10 9 8 7 6 5 4 3 2
0.35 ± 0.05
0.40
1.40 Max
<Bottom View>
Unit : mm
- 49 -
Rev 1.8 (Apr. 2005)