HT48R062/HT48C062 Cost-Effective I/O Type 8-Bit MCU Technical Document · Tools Information · FAQs · Application Note - HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM - HA0013E HT48 & HT46 LCM Interface Design - HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series - HA0075E MCU Reset and Oscillator Circuits Application Note - HA0126E Nickel Cadmium and Nickel Hydride Battery Charging Applications Using the HT48R062 Features · Operating voltage: · 63 powerful instructions fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V · Up to 0.5ms instruction cycle with 8MHz system clock · All instructions in 1 or 2 machine cycles · 11 bidirectional I/O lines · 14-bit table read instructions · On-chip crystal and RC oscillator · One-level subroutine nesting · Watchdog Timer · Bit manipulation instructions · 1K´14 program memory · Low voltage reset function · 32´8 data RAM · 16-pin DIP/NSOP package · HALT function and wake-up feature reduce power consumption General Description The advantages of low power consumption, I/O flexibility, oscillator options, HALT and wake-up functions, watchdog timer, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem controllers, etc. The HT48R062/HT48C062 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for cost-effective multiple I/O control product applications. The mask version HT48C062 is fully pin and functionally compatible with the OTP version HT48R062 devices. Block Diagram S ta c k P ro g ra m C o u n te r P ro g ra m In s tr u c tio n R e g is te r M M P U X D a ta M e m o ry P A C A L U S y s te m X ¸ 2 C lo c k /4 W D T O S C (2 4 k H z ) L V R M U X T im in g G e n e ra to r U E N /D IS H A L T In s tr u c tio n D e c o d e r M W D T S T A T U S P A P o rt A P A 0 ~ P A 7 S h ifte r P B C O S C 2 Rev. 1.21 O S R E V D V S S C 1 S D P B P o rt B P B 0 ~ P B 2 A C C 1 December 30, 2008 HT48R062/HT48C062 Pin Assignment P A 3 1 1 6 P A 4 P A 2 2 1 5 P A 5 P A 1 3 1 4 P A 6 P A 0 4 1 3 P A 7 P B 0 5 1 2 O S C 2 V S S 6 1 1 O S C 1 P B 1 7 1 0 V D D P B 2 8 9 R E S H T 4 8 R 0 6 2 /H T 4 8 C 0 6 2 1 6 D IP -A /N S O P -A Pin Description I/O Code Option Description PA0~PA7 I/O Pull-high Wake-up Bidirectional 8-bit input/output port. A configuration option determines if all of the pins on this port are configured as wake-up inputs. Software instructions determine the CMOS output or Schmitt trigger input with a pull-high resistor (determined by pull-high options). PB0~PB2 I/O Pull-high Bidirectional 3-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with a pull-high resistor (determined by pull-high options). VDD ¾ ¾ Positive power supply VSS ¾ ¾ Negative power supply, ground OSC2 OSC1 O I Crystal or RC RES I ¾ Pin Name OSC1, OSC2 are connected to an RC network or a crystal (determined by code option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock (NMOS open drain output). Schmitt trigger reset input. Active low. Note: The Port A wake-up configuration option applies to all pins on Port A. Individual pins on this port cannot be setup to have a wake-up function. Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total .............................................................150mA Total Power Dissipation .....................................500mW Operating Temperature...........................-40°C to 85°C IOH Total ..........................................................-100mA Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.21 2 December 30, 2008 HT48R062/HT48C062 D.C. Characteristics Symbol VDD IDD1 IDD2 Parameter Operating Voltage Ta=25°C Test Conditions VDD Conditions ¾ 5.5 V ¾ fSYS=8MHz 3.3 ¾ 5.5 V ¾ 0.6 1.5 mA No load, fSYS=4MHz 5V ¾ 2 4 mA 3V ¾ 0.8 1.5 mA ¾ 2.5 4 mA ¾ 4 8 mA ¾ ¾ 5 mA ¾ ¾ 10 mA ¾ ¾ 1 mA ¾ ¾ 2 mA No load, fSYS=4MHz 5V Standby Current (WDT Enabled) 5V No load, fSYS=8MHz 3V No load, system HALT 5V ISTB2 Unit 2.2 Operating Current (RC OSC) ISTB1 Max. fSYS=4MHz 3V Operating Current (Crystal OSC, RC OSC) Typ. ¾ Operating Current (Crystal OSC) IDD3 Min. 3V Standby Current (WDT Disabled) No load, system HALT 5V VIL1 Input Low Voltage for I/O Port ¾ ¾ 0 ¾ 0.3VDD V VIH1 Input High Voltage for I/O Port ¾ ¾ 0.7VDD ¾ VDD V VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V VLVR Low Voltage Reset ¾ LVR enabled 2.7 3 3.3 V 4 8 ¾ mA 10 20 ¾ mA -2 -4 ¾ mA -5 -10 ¾ mA 20 60 100 kW 10 30 50 kW IOL 3V I/O Port Sink Current VOL=0.1VDD 5V IOH 3V I/O Port Source Current VOH=0.9VDD 5V RPH 3V ¾ Pull-high Resistance 5V A.C. Characteristics Symbol fSYS1 fSYS2 Parameter System Clock (Crystal OSC) System Clock (RC OSC) tWDTOSC Watchdog Oscillator Period Ta=25°C Test Conditions VDD ¾ Conditions 2.2V~5.5V Min. Typ. Max. Unit 400 ¾ 4000 kHz ¾ 3.3V~5.5V 400 ¾ 8000 kHz ¾ 2.2V~5.5V 400 ¾ 4000 kHz ¾ 3.3V~5.5V 400 ¾ 8000 kHz 22 45 90 ms 16 32 64 ms 1 ¾ ¾ ms ¾ 1024 ¾ tSYS 0.25 1 2 ms 3V ¾ 5V tRES External Reset Low Pulse Width ¾ tSST System Start-up Timer Period ¾ tLVR Low Voltage Width to Reset ¾ ¾ Power-up or wake-up from HALT ¾ Note: tSYS=1/fSYS Rev. 1.21 3 December 30, 2008 HT48R062/HT48C062 Functional Description After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. Execution Flow The HT48R062/HT48C062 system clock can be derived from a crystal/ceramic resonator oscillator or an RC. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The 10-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed and its contents specify a maximum of 1024 addresses. The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. T 1 S y s te m T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 C lo c k In s tr u c tio n C y c le P C P C P C + 1 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) P C + 2 F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Mode Initial Reset Program Counter *9 *8 *7 *6 0 0 0 0 Skip *5 *4 *3 *2 *1 *0 0 0 0 0 0 0 @3 @2 @1 @0 Program Counter+2 Loading PCL *9 *8 @7 @6 @5 @4 Jump, Call Branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *9~*0: Program counter bits S9~S0: Stack register bits #9~#0: Instruction code bits @7~@0: PCL bits Rev. 1.21 4 December 30, 2008 HT48R062/HT48C062 Program Memory - ROM Stack Register - STACK The program memory is used to store the program instructions which are to be executed. It also contains data and table and is organized into 1024´14 bits, addressed by the program counter and table pointer. This is a special part of the memory used to save the contents of the Program Counter only. The stack is organized into one level and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call the contents of the program counter are pushed onto the stack. At the end of a subroutine signaled by a return instruction (RET), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. Certain locations in the program memory are reserved for special usage: · Location 000H This area is reserved for the initialization program. After chip reset, the program always begins execution at location 000H. · Table location If the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent return address is stored). Any location in the EPROM space can be used as look-up tables. The instructions ²TABRDC [m]² (the current page, one page=256 words) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, the remaining 2 bits are read as ²0². The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), where P indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. All table related instructions need 2 cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. 0 0 0 H Data Memory - RAM The data memory is designed with 44´8 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (32´8). Most of them are read/write, but some are read only. The special function registers include the Indirect Addressing Register (00H), the Memory Pointer register (MP;01H), the Accumulator (ACC;05H) the Program Counter Lower-order byte register (PCL;06H), the Table Pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the Watchdog Timer option setting register (WDTS;09H), the STATUS register (STATUS;0AH), the I/O registers (PA;12H, PB;14H) and I/O control registers (PAC;13H, PBC;15H). The remaining space before the 20H is reserved for future expanded usage and reading these locations will return the result 00H. The general purpose data memory, addressed from 20H to 3FH, is used for data and control information under instruction command. D e v ic e in itia liz a tio n p r o g r a m n 0 0 H P ro g ra m L o o k - u p ta b le ( 2 5 6 w o r d s ) n F F H All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the ²SET [m].i² and ²CLR [m].i² instructions, respectively. They are also indirectly accessible through memory pointer register (MP;01H). L o o k - u p ta b le ( 2 5 6 w o r d s ) 3 F F H 1 4 b its N o te : n ra n g e s fro m 0 to 3 Program Memory Table Location Instruction(s) *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 TABRDC [m] P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: *9~*0: Table location bits P9~P8: Current program counter bits Rev. 1.21 @7~@0: Table pointer bits 5 December 30, 2008 HT48R062/HT48C062 0 0 H In d ir e c t A d d r e s s in g R e g is te r 0 1 H M P result ²1². Any writing operation to MP will only transfer the lower 7-bit data to MP. 0 2 H Accumulator 0 3 H 0 4 H 0 5 H The accumulator closely relates to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. Data movement between two data memory locations has to pass through the accumulator. A C C 0 6 H P C L 0 7 H T B L P 0 8 H T B L H 0 9 H W D T S 0 A H S T A T U S S p e c ia l P u r p o s e D a ta M e m o ry 0 B H Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions. 0 C H 0 D H 0 E H · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) 0 F H · Logic operations (AND, OR, XOR, CPL) 1 0 H · Rotation (RL, RR, RLC, RRC) 1 1 H 1 2 H P A 1 3 H P A C 1 4 H P B 1 5 H 1 6 H P B C · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data operation but also changes the contents of the status register. : U n u s e d , re a d a s "0 0 " 1 F H 2 0 H Status Register - STATUS This 8-bit status register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. G e n e ra l P u rp o s e D a ta M e m o ry (3 2 B y te s ) 3 F H RAM Mapping With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other register. Any data written into the status register will not change the TO or PDF flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PDF flags can only be changed by the Watchdog Timer overflow, chip power-up, clearing the Watchdog Timer and executing the ²HALT² instruction. Indirect Addressing Register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses data memory pointed to by MP (01H). Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer register MP (01H) is a 7-bit register. The bit 7 of MP is undefined and reading will return the Bit No. Label Function 0 C C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. 1 AC AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. 2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. 3 OV OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. 4 PDF PDF is cleared when either a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. 5 TO TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. 6~7 ¾ Unused bit, read as ²0² Status (0AH) Register Rev. 1.21 6 December 30, 2008 HT48R062/HT48C062 RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by options. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by an option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Once the internal WDT oscillator (RC oscillator with a period of 32ms at 5V normally) is selected, it is first divided by 512 (9-stage) to get the nominal time-out period of approximately 17ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.1s at 5V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user¢s defined flags, which can be used to indicate some specified status. Oscillator Configuration There are two oscillator circuits implemented in the microcontroller. V D D 4 7 0 p F C 1 O S C 1 O S C 1 R O S C C 2 R 1 O S C 2 C r y s ta l O s c illa to r fS Y S /4 N M O S o p e n d r a in O S C 2 R C O s c illa to r System Oscillator Both are designed for system clocks; the RC oscillator and the Crystal oscillator, which are determined by code options. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores the external signal to conserve power. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. If an RC oscillator is used, an external resistor between OSC1 and VSS in needed and the resistance must range from 24kW to 1MW. The system clock, divided by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift for the oscillator. No other external components are needed. Instead of a crystal, the resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. WS2 WS1 WS0 Division Ratio 0 0 0 1:1 0 0 1 1:2 0 1 0 1:4 0 1 1 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 WDTS (09H) Register The WDT overflow under normal operation will initialize ²chip reset² and set the status bit ²TO². But in the HALT mode, the overflow will initialize a ²warm reset², and only the Program Counter and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a Watchdog Timer - WDT The clock source of WDT is implemented by a dedicated W D T P r e s c a le r S y s te m C lo c k /4 W D T O S C (2 4 k H z ) O p tio n S e le c t 8 - b it C o u n te r ¸ 2 7 - b it C o u n te r 8 -to -1 M U X W S 0 ~ W S 2 W D T T im e - o u t Watchdog Timer Rev. 1.21 7 December 30, 2008 HT48R062/HT48C062 low level to RES), software instruction and a ²HALT² instruction. The software instruction include ²CLR WDT² and the other set - ²CLR WDT1² and ²CLR WDT2². Of these two types of instruction, only one can be active depending on the option - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times equal one), any execution of the ²CLR WDT² instruction will clear the WDT. In the case that ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur: · RES reset during normal operation · RES reset during HALT · WDT time-out reset during normal operation Some registers remain unchanged during reset conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different ²chip resets². Power Down Operation - HALT TO PDF The HALT mode is initialized by the ²HALT² instruction and results in the following... 0 0 RES reset during power-up · The system oscillator turns off and the WDT stops. u u RES reset during normal operation · The contents of the on-chip RAM and registers remain 0 1 RES wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT unchanged. · WDT prescaler are cleared. · All I/O ports maintain their original status. RESET Conditions · The PDF flag is set and the TO flag is cleared. Note: ²u² means unchanged. The system can quit the HALT mode by means of an external reset or an external falling edge signal on Port A. An external reset causes a device initialization. Examining the TO and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared when the system powers up or execute the ²CLR WDT² instruction and is set when the ²HALT² instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the program counter and SP, the others keep their original status. To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system powers up or when the system awakes from a HALT state. When a system power up occurs, an SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status is shown below. A Port A wake-up can be considered as a continuation of normal execution. A configuration option determines if all of the pins on Port A are configured as wake-up pins. Individual Port A pins cannot be setup as wake-up inputs. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. Program Counter 000H WDT Prescaler Clear Input/Output ports Input mode Stack Pointer Points to the top of the stack Once a wake-up event(s) occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy cycle period will be inserted after the wake-up. V D D R E S tS S T S S T T im e - o u t C h ip R e s e t Reset Timing Chart Rev. 1.21 8 December 30, 2008 HT48R062/HT48C062 V V D D H A L T D D 0 .0 1 m F 1 0 0 k W W D T 1 0 0 k W R E S 0 .1 m F B a s ic R e s e t C ir c u it 0 .1 m F H i-n o is e R e s e t C ir c u it S S T 1 0 -s ta g e R ip p le C o u n te r O S C 1 Reset Circuit Note: R e s e t R E S R E S 1 0 k W W D T T im e - o u t R e s e t P o w e r - o n D e te c tio n Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise, it is recommended to use the Hi-noise Reset Circuit. Reset Configuration The chip reset status of the registers is summarized in the following table: Register Program Counter Reset (Power-on) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* 000H 000H 000H 000H 000H MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu WDTS 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu PBC ---- -111 ---- -111 ---- -111 ---- -111 ---- -uuu STATUS Note: ²*² means ²warm reset² ²u² means ²unchanged² ²x² means ²unknown² Rev. 1.21 9 December 30, 2008 HT48R062/HT48C062 Input/Output Ports After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H or 14H) instructions. There are up to 11 bidirectional input/output lines in the microcontroller labeled with port names PA and PB, which are mapped to the data memory of [12H] and [14H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H or 14H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Some instructions first input data and then follow the output operations. For example, ²SET [m].i², ²CLR [m].i², ²CPL [m]², ²CPLA [m]² read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each I/O line has its own control register (PAC, PBC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write ²1². The input source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modifywrite² instruction. Each line of Port A has the capability of waking-up the device. The highest 5-bit of Port B are not physically implemented; on reading them a ²0² is returned whereas writing then results in a no-operation. See Application note. There are pull-high options available for PA and PB. Once the pull-high option is selected, I/O lines have pull-high resistors. Otherwise, the pull-high resistors are absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H and 15H. V D a ta B u s W r ite C o n tr o l R e g is te r C o n tr o l B it Q D C K D D P u ll- h ig h Q S C h ip R e s e t R e a d C o n tr o l R e g is te r W r ite D a ta R e g is te r P A 0 ~ P A 7 P B 0 ~ P B 2 D a ta B it Q D C K S Q M R e a d D a ta R e g is te r S y s te m U X W a k e -u p ( P A o n ly ) W a k e - u p O p tio n Input/Output Ports Rev. 1.21 10 December 30, 2008 HT48R062/HT48C062 Low Voltage Reset - LVR The relationship between VDD and VLVR is shown below. V D D 5 .5 V The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally. V O P R 5 .5 V V The LVR includes the following specifications: · The low voltage (0.9V~VLVR) has to remain in their 2 .2 V original state to exceed 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and do not perform a reset function. 0 .9 V · The LVR uses the ²OR² function with the external RES signal to perform chip reset. V L V R 3 .0 V Note: VOPR is the voltage range for proper chip operation at 4MHz system clock. D D 5 .5 V V L V R L V R D e te c t V o lta g e 0 .9 V 0 V R e s e t S ig n a l N o r m a l O p e r a tio n R e s e t R e s e t *1 *2 Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode. Options The following table shows eight kinds of code option in the HT48R062/HT48C062. All the code options must be defined to ensure proper system functioning. No. Options 1 WDT clock source: WDTOSC or fSYS/4 2 WDT function: enable or disable 3 LVR function: enable or disable 4 CLRWDT instruction(s): one or two clear WDT instruction(s) 5 System oscillator: RC or crystal 6 PA and PB pull-high resistors: none or pull-high 7 PA0~PA7 wake-up: enable or disable Rev. 1.21 11 December 30, 2008 HT48R062/HT48C062 Application Circuits V D D V D D P A 0 ~ P A 7 R e s e t C ir c u it 1 0 0 k W 0 .1 m F V P B 0 ~ P B 2 R E S O S C 1 0 .1 m F R V S S O S C C ir c u it O S C O S C 1 C 2 O S C 1 O S C 2 R C S y s te m O s c illa to r 2 4 k W < R O S C < 1 M W fS Y S /4 O S C 2 N M O S o p e n d r a in C 1 R 1 O S C 2 O S C H T 4 8 R 0 6 2 /H T 4 8 C 0 6 2 Note: D D 4 7 0 p F C ry s ta l S y s te m F o r th e v a lu e s , s e e ta b le b e lo w O s c illa to r C ir c u it 1. Crystal/resonator system oscillators For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. Reset circuit The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and remains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of the wiring connected to the RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information. Rev. 1.21 12 December 30, 2008 HT48R062/HT48C062 Instruction Set subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. Logical and Rotate Operations For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and Rev. 1.21 13 December 30, 2008 HT48R062/HT48C062 Bit Operations Other Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the ²SET [m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. In addition to the above functional instructions, a range of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Read Operations Table conventions: Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Mnemonic x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description Cycles Flag Affected 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z 1 1Note 1 1Note Z Z Z Z Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rev. 1.21 Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 14 December 30, 2008 HT48R062/HT48C062 Mnemonic Description Cycles Flag Affected Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.21 15 December 30, 2008 HT48R062/HT48C062 Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC ¬ ACC + [m] + C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] ¬ ACC + [m] + C Affected flag(s) OV, Z, AC, C ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC ¬ ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x Add immediate data to ACC Description The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. Operation ACC ¬ ACC + x Affected flag(s) OV, Z, AC, C ADDM A,[m] Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. Operation [m] ¬ ACC + [m] Affected flag(s) OV, Z, AC, C AND A,[m] Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²AND² [m] Affected flag(s) Z AND A,x Logical AND immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²AND² x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. Operation [m] ¬ ACC ²AND² [m] Affected flag(s) Z Rev. 1.21 16 December 30, 2008 HT48R062/HT48C062 CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Operation Stack ¬ Program Counter + 1 Program Counter ¬ addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] ¬ 00H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i ¬ 0 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO, PDF CLR WDT1 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO, PDF CLR WDT2 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO ¬ 0 PDF ¬ 0 Affected flag(s) TO, PDF Rev. 1.21 17 December 30, 2008 HT48R062/HT48C062 CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] ¬ [m] Affected flag(s) Z CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC ¬ [m] Affected flag(s) Z DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] ¬ ACC + 00H or [m] ¬ ACC + 06H or [m] ¬ ACC + 60H or [m] ¬ ACC + 66H Affected flag(s) C DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] ¬ [m] - 1 Affected flag(s) Z DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ¬ [m] - 1 Affected flag(s) Z HALT Enter power down mode Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO ¬ 0 PDF ¬ 1 Affected flag(s) TO, PDF Rev. 1.21 18 December 30, 2008 HT48R062/HT48C062 INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. Operation [m] ¬ [m] + 1 Affected flag(s) Z INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC ¬ [m] + 1 Affected flag(s) Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter ¬ addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC ¬ [m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC ¬ x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] ¬ ACC Affected flag(s) None NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²OR² [m] Affected flag(s) Z Rev. 1.21 19 December 30, 2008 HT48R062/HT48C062 OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²OR² x Affected flag(s) Z ORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. Operation [m] ¬ ACC ²OR² [m] Affected flag(s) Z RET Return from subroutine Description The Program Counter is restored from the stack. Program execution continues at the restored address. Operation Program Counter ¬ Stack Affected flag(s) None RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter ¬ Stack ACC ¬ x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Operation Program Counter ¬ Stack EMI ¬ 1 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. Operation [m].(i+1) ¬ [m].i; (i = 0~6) [m].0 ¬ [m].7 Affected flag(s) None RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; (i = 0~6) ACC.0 ¬ [m].7 Affected flag(s) None Rev. 1.21 20 December 30, 2008 HT48R062/HT48C062 RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].(i+1) ¬ [m].i; (i = 0~6) [m].0 ¬ C C ¬ [m].7 Affected flag(s) C RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) ¬ [m].i; (i = 0~6) ACC.0 ¬ C C ¬ [m].7 Affected flag(s) C RR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i ¬ [m].(i+1); (i = 0~6) [m].7 ¬ [m].0 Affected flag(s) None RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ¬ [m].(i+1); (i = 0~6) ACC.7 ¬ [m].0 Affected flag(s) None RRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i ¬ [m].(i+1); (i = 0~6) [m].7 ¬ C C ¬ [m].0 Affected flag(s) C RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i ¬ [m].(i+1); (i = 0~6) ACC.7 ¬ C C ¬ [m].0 Affected flag(s) C Rev. 1.21 21 December 30, 2008 HT48R062/HT48C062 SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ¬ ACC - [m] - C Affected flag(s) OV, Z, AC, C SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ¬ ACC - [m] - C Affected flag(s) OV, Z, AC, C SDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ¬ [m] - 1 Skip if [m] = 0 Affected flag(s) None SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC ¬ [m] - 1 Skip if ACC = 0 Affected flag(s) None SET [m] Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] ¬ FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i ¬ 1 Affected flag(s) None Rev. 1.21 22 December 30, 2008 HT48R062/HT48C062 SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] ¬ [m] + 1 Skip if [m] = 0 Affected flag(s) None SIZA [m] Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC ¬ [m] + 1 Skip if ACC = 0 Affected flag(s) None SNZ [m].i Skip if bit i of Data Memory is not 0 Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m].i ¹ 0 Affected flag(s) None SUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ¬ ACC - [m] Affected flag(s) OV, Z, AC, C SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] ¬ ACC - [m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ¬ ACC - x Affected flag(s) OV, Z, AC, C Rev. 1.21 23 December 30, 2008 HT48R062/HT48C062 SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 « [m].7 ~ [m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4 ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0 Affected flag(s) None SZ [m] Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation Skip if [m] = 0 Affected flag(s) None SZA [m] Skip if Data Memory is 0 with data movement to ACC Description The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC ¬ [m] Skip if [m] = 0 Affected flag(s) None SZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i = 0 Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ¬ program code (low byte) TBLH ¬ program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] ¬ program code (low byte) TBLH ¬ program code (high byte) Affected flag(s) None Rev. 1.21 24 December 30, 2008 HT48R062/HT48C062 XOR A,[m] Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²XOR² [m] Affected flag(s) Z XORM A,[m] Logical XOR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. Operation [m] ¬ ACC ²XOR² [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ¬ ACC ²XOR² x Affected flag(s) Z Rev. 1.21 25 December 30, 2008 HT48R062/HT48C062 Package Information 16-pin DIP (300mil) Outline Dimensions A B A 1 6 9 1 8 B 1 6 9 1 8 H H C C D D G E G E I F I F Fig1. Full Lead Packages Fig2. 1/2 Lead Packages · MS-001d (see fig1) Symbol A Dimensions in mil Min. Nom. Max. 780 ¾ 880 B 240 ¾ 280 C 115 ¾ 195 D 115 ¾ 150 E 14 ¾ 22 F 45 ¾ 70 G ¾ 100 ¾ H 300 ¾ 325 I ¾ ¾ 430 · MS-001d (see fig2) Symbol A Rev. 1.21 Dimensions in mil Min. Nom. Max. 735 ¾ 775 B 240 ¾ 280 C 115 ¾ 195 D 115 ¾ 150 E 14 ¾ 22 70 F 45 ¾ G ¾ 100 ¾ H 300 ¾ 325 I ¾ ¾ 430 26 December 30, 2008 HT48R062/HT48C062 · MO-095a (see fig2) Symbol A Rev. 1.21 Dimensions in mil Min. Nom. Max. 745 ¾ 785 B 275 ¾ 295 C 120 ¾ 150 D 110 ¾ 150 E 14 ¾ 22 F 45 ¾ 60 G ¾ 100 ¾ H 300 ¾ 325 I ¾ ¾ 430 27 December 30, 2008 HT48R062/HT48C062 16-pin NSOP (150mil) Outline Dimensions 1 6 A 9 B 8 1 C C ' G H D E a F · MS-012 Symbol Rev. 1.21 Dimensions in mil Min. Nom. Max. A 228 ¾ 244 B 150 ¾ 157 C 12 ¾ 20 C¢ 386 ¾ 394 D ¾ ¾ 69 E ¾ 50 ¾ F 4 ¾ 10 G 16 ¾ 50 H 7 ¾ 10 a 0° ¾ 8° 28 December 30, 2008 HT48R062/HT48C062 Product Tape and Reel Specifications Reel Dimensions D T 2 A C B T 1 SOP 16N (150mil) Symbol Description Dimensions in mm A Reel Outer Diameter 330.0±1.0 B Reel Inner Diameter 100.0±1.5 C Spindle Hole Diameter 13.0+0.5/-0.2 D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.21 2.0±0.5 16.8+0.3/-0.2 22.2±0.2 29 December 30, 2008 HT48R062/HT48C062 Carrier Tape Dimensions P 0 D P 1 t E F W C D 1 B 0 P K 0 A 0 R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . SOP 16N (150mil) Symbol Description Dimensions in mm W Carrier Tape Width 16.0±0.3 P Cavity Pitch 8.0±0.1 E Perforation Position 1.75±0.1 F Cavity to Perforation (Width Direction) 7.5±0.1 D Perforation Diameter 1.55+0.1/-0.0 D1 Cavity Hole Diameter 1.50+0.25/-0.0 P0 Perforation Pitch 4.0±0.1 P1 Cavity to Perforation (Length Direction) 2.0±0.1 A0 Cavity Length 6.5±0.1 B0 Cavity Width 10.3±0.1 K0 Cavity Depth 2.1±0.1 t Carrier Tape Thickness 0.30±0.05 C Cover Tape Width 13.3±0.1 Rev. 1.21 30 December 30, 2008 HT48R062/HT48C062 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.21 31 December 30, 2008