TPS386596L33 www.ti.com SLVSA75 – JULY 2010 Quad Reset Supervisor with Manual Reset Input Check for Samples: TPS386596L33 FEATURES 1 • • • • • • • • • DESCRIPTION 4 Voltage Monitors Threshold Accuracy: 0.25% (Typical) Fixed 50ms RESETdelay time Active Low Manual Reset Input Very Low Quiescent Current: 7µA typical SVS-1: Fixed Threshold for monitoring 3.3V SVS-2/3/4 – Adjustable Threshold Down to 0.4V Open Drain RESET Output Space Saving 8-pin MSOP Package The TPS386596L33 monitors four power rails and asserts the RESET signal when any of the SENSE inputs drop below their respective thresholds. SVS-1 can be used to monitor a 3.3V nominal power supply with no external components required. SVS-2, SVS-3, and SVS-4 are adjustable using external resistors and can be used to monitor any power supply voltage higher than 0.4V. All SENSE inputs have a threshold accuracy of 0.25% (typical). The TPS386596L33 also has an active low Manual Reset (MR) that can be used to assert the RESET signal as desired by the application. The open drain, active low RESEToutput de-asserts using a fixed 50ms delay. APPLICATIONS • • • • • • The TPS386596L33 has a low quiescent current of 7µA typical and is available in a space saving 8-pin MSOP package. Notebook / Desktop Computers Industrial Equipment Telecom, Networking Infrastructure Server, Storage Equipment DSP and Microcontroller Applications FPGA/ASIC Applications SPACER SPACER VIN DC-DC LDO DC-DC LDO Sub CPU MSP430 DC-DC LDO __ RSH4 RSH3 RSH2 VCC RP MR DC-DC LDO 3.3V SENSE2 VCC1 ____ ____ TPS386596 RESET RESET SENSE1 SENSE3 VCC2 VCC3 VCC4 DSP CPU FPGA SENSE4 GND RSL4 RSL3 RSL2 Figure 1. TPS386596L33 Typical Application Circuit 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS386596L33 SLVSA75 – JULY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Custom threshold voltages from 0.80V to 4.6V, 4.8V to 6.0V are available through the use of factory EEPROM programming. Minimum order quantities apply. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) TPS386596 UNIT Input voltage range, VCC –0.3 to 7.0 V Other voltage ranges: VMR, VSENSE1, VSENSE2, VSENSE3, VSENSE4, VRESET –0.3 to 7.0 V 5 mA ESD rating, HBM 2 kV ESD rating, CDM 500 V RESETpin current Continuous total power dissipation See Thermal Information Table Operating virtual junction temperature range, TJ –40 to 150 °C Operating ambient temperature range, TA –40 to 125 °C Storage temperature range, Tstg –65 to 150 °C (1) (2) Stresses beyond those listed under Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. As a result of the low dissipated power in this device, it is assumed that TJ = TA THERMAL INFORMATION THERMAL METRIC (1) TPS386596 DGK (8 PINS) qJA Junction-to-ambient thermal resistance 183.8 qJCtop Junction-to-case (top) thermal resistance 70.7 qJB Junction-to-board thermal resistance 72.8 yJT Junction-to-top characterization parameter 4.9 yJB Junction-to-board characterization parameter 68.4 qJCbot Junction-to-case (bottom) thermal resistance n/a (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS386596L33 TPS386596L33 www.ti.com SLVSA75 – JULY 2010 ELECTRICAL CHARACTERISTICS Over the operating temperature range of TJ = –40°C to +125°C. 1.8V < VCC < 6.5V, R/RESET = 100kΩ to VCC, C/RESET = 50pF to GND, unless otherwise noted. Typical values are at TJ = +25°C. PARAMETER TEST CONDITIONS VVCC Input supply range IVCC VCC Supply current (current into VCC pin) VCC = 3.3V, RESET not asserted VCC = 6.5V, RESET not asserted Power-up Reset Voltage (1) VOL(max) = 0.2V, IRESET = 15µA TYP 1.8 (2) Negative-going Input Threshold Accuracy VITn MIN MAX V 7 19 µA 7.5 22 µA 0.9 V SENSE1 2.87 2.90 2.93 V SENSE2, SENSE3, SENSE4 396 400 404 mV SENSE1 25 72 mV SENSE2, SENSE3, SENSE4 3.5 10 mV VHYS Hysteresis (Positive-going) on VIT pin tw Input pulse width to SENSEn and MR pins SENSEn: 1.05VIT ≥ 0.95VIT ISENSE1 Input Current at SENSE1 VSENSE1 = 3.3V ISENSEn Input Current at SENSEn pin, n = 2, 3, VSENSEn = 0.42V 4 td RESETdelay time 30 VIL MR logic low input 0 VIH MRlogic high input 0.7Vcc RMR_Pullup Internal pullup resistor on MR pin to VCC IOL = 1mA 0.4 VOL Low-level RESET output voltage SENSEn = 0V, 1.3V < VCC < 1.8V, IOL = 0.4mA (1) 0.3 ILKG RESET Leakage Current VRESET = 6.5V, RESET not asserted CIN Input pin capacitance (1) (2) UNIT 6.5 4 MR: 0.7VCC ≥ 0.3VCC µs 50 2.2 2.75 -25 50 ns 3.3 µA 25 nA 70 ms 0.3Vcc V V 100 –300 kΩ 300 5 V nA pF These specs are out of recommended VCC range and only define RESET output performance during VCC ramp up. The lowest supply voltage (VCC) at which RESET becomes active. Trise(VDD) ≥ 15us/V. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS386596L33 3 TPS386596L33 SLVSA75 – JULY 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM VCC RESET MR Delay 50ms 3.3V SENSE1 + _ 400mV SENSE2 + _ 400mV SENSE3 + _ 400mV SENSE4 + _ 400mV GND Figure 2. TPS386596L33 Block Diagram 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS386596L33 TPS386596L33 www.ti.com SLVSA75 – JULY 2010 DEVICE INFORMATION PIN CONFIGURATION SENSE4 1 8 VCC SENSE3 2 7 /MR SENSE2 3 6 /RESET SENSE1 4 5 GND MSOP-8 PIN FUNCTIONS PIN DESCRIPTION NAME NO. SENSE1 4 Monitor voltage input for Supply 1 When the voltage at this terminal drops below the threshold voltage (VIT1= 2.9V), RESET is asserted. SENSE2 3 Monitor voltage input for Supply 2 When the voltage at this terminal drops below the threshold voltage (VIT2= 0.4V), RESET is asserted. SENSE3 2 Monitor voltage input for Supply 3 When the voltage at this terminal drops below the threshold voltage (VIT3= 0.4V), RESET is asserted. SENSE4 1 Monitor voltage input for Supply 4 When the voltage at this terminal drops below the threshold voltage (VIT4= 0.4V), RESET is asserted. MR 7 Manual reset input with internal 100k pull-up to Vcc and 50ns deglitch. Logic low level of this pin asserts RESET. RESET 6 RESET is an open-drain output pin. When RESET is asserted, this pin remains in a low-impedance state. When RESET is released, this pin goes to a high-impedance state after 50ms. Vcc 8 Supply voltage. Connecting a 0.1 µF ceramic capacitor close to this pin is recommended. GND 5 Ground GENERAL DESCRIPTION The TPS386596L33 multi-channel reset supervisor provides a complete single reset function for a four power supply system. The design of the SVS is based on the TPS386000 quad supervisor device series. TPS386596 is designed to assert the /RESET signal following the logic in Table 1. The RESET output remains asserted for a 50ms delay time after the event of reset release. The SENSE1 input has a fixed voltage threshold designed to monitor a 3.3V nominal supply. The trip point, VIT1, for SENSE1 is 2.90 (TYP). Each of the remaining SENSEn inputs (n = 2,3,4) can be set to any voltage threshold above 0.4V using an external resistor divider. An active low manual reset (MR) input is also provided for asserting the RESET signal as desired by the system. RESET OUTPUT In a typical application of TPS386596, the RESET output is connected to the reset input of a processor (DSP, MCU, CPU, FPGA, ASIC, etc.) or connected to the enable input of voltage regulators (DC-DC, LDO, etc.). TPS386596 provides an open drain reset output. Pull-up resistors must be used to hold this line high when RESET is not asserted. By connecting a pull-up resistor to the proper voltage rail (up to 6.5V), the RESET output can be connected to other devices at the right interface voltage level. The pull-up resistor should be no smaller than 10kΩ as a result of the finite impedance of the output transistor. The RESET output is defined for VCC > 0.9V. To ensure that the target processor is properly reset, the VCC supply input should be fed by the power rail which is available as early as possible in the application. Table 1 describes a truth table of how the RESET output is asserted or released. Figure 3 provides a timing diagram that shows how RESET is asserted and de-asserted in relation to MR and the SENSEn inputs. Once the conditions are met, the transitions from the asserted state to the release state are performed after a fixed 50ms delay time. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS386596L33 5 TPS386596L33 SLVSA75 – JULY 2010 www.ti.com VCC 0.9 V t SENSE1 VHYS VIT t MR t RESET td td t Figure 3. Timing Diagram SENSE INPUTS The SENSEn inputs provide terminals at which the system voltages can be monitored. If the voltage at any one of the SENSEn pins drops below their respective VITn, then the RESET output is asserted. The comparators have a built-in hysteresis to ensure smooth RESETtransitions. It is good analog design practice to use a 1nF to 10nF bypass capacitor at the SENSEn input to ground, to reduce sensitivity to transients, layout parasitics, and interference between power rails monitored by this device. A typical connection of resistor dividers is show in Figure 4. SENSE1 is used to monitor a 3.3V nominal power supply voltage with a trip point = 2.90V, and the remaining SENSEn (n=2,3,4) inputs can be used to monitor voltage rails down to 0.4V. Threshold voltages can be calculated using the following equations. VCC2_target = (1 + RS2H/RS2L) × 0.4 (V) VCC3_target = (1 + RS3H/RS3L) × 0.4 (V) VCC4_target = (1 + RS4H/RS4L) × 0.4 (V) 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS386596L33 TPS386596L33 www.ti.com VIN SLVSA75 – JULY 2010 DC-DC LDO DC-DC LDO Sub CPU MSP430 DC-DC LDO VCC __ RSH4 RSH3 RP MR RSH2 DC-DC LDO 3.3V SENSE2 VCC1 ____ ____ TPS386596 RESET RESET SENSE1 SENSE3 VCC2 VCC3 VCC4 DSP CPU FPGA SENSE4 GND RSL4 RSL3 RSL2 Figure 4. Typical TPS386596L33 Application Diagram MANUAL RESET The manual reset MR input allows external logic signal from processors, other logic circuits, and/or discrete sensors to initiate a reset. The typical application of a TPS386596 has its RESET output connected to processor. A logic low at MR causes RESET to assert. After MR returns to a logic high and SENSEn are above their respective voltage thresholds, RESET is released after a fixed 50ms reset delay time. An internal 100kΩ pull-up to VCC is integrated on the MR input. There is also an internal 50ns (typical) deglitch circuit. Table 1. RESET Truth Table CONDITION OUTPUT MR = L SENSEn < VITn RESET = L Reset asserted MR = L SENSEn > VITn RESET = L Reset asserted MR = H SENSE1 < SENSE2 < SENSE3 < SENSE4 < VIT1 OR VIT2 OR VIT3 OR VIT4 RESET = L Reset asserted MR = H SENSE1 > SENSE2 > SENSE3 > SENSE4 > VIT1 AND VIT2 AND VIT3 AND VIT4 RESET = H Reset released IMMUNITY TO SENSE PIN VOLTAGE TRANSIENTS The TPS386596 is relatively immune to short negative transients on the SENSEn pins. Sensitivity to transients is dependent on how much percentage the sense voltage drops below the threshold voltage, as shown in Figure 8. See Figure 5 for the measurement technique. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS386596L33 7 TPS386596L33 SLVSA75 – JULY 2010 www.ti.com PARAMETRIC MEASUREMENT INFORMATION TEST CONDITION SENSE2,3,4 Voltage (V) X1 = (Z1/0.4) *100 (%) X2 = (Z2/0.4) *100 (%) Y1 Z1 Y2 Z2 X1 and X2 are overdrive (%) values calculated from actual SENSE2,3,4 voltage amplitudes measured as Z1 and Z2. YN is the minimum pulse width that gives / RESET transition. Greater ZN produces shorter YN TIME Figure 5. Measurement Technique for Immunity to Sense Pin Voltage Transient TYPICAL CHARACTERISTICS At TA = +25°C, and VCC = 3.3V, unless otherwise noted. 8 Figure 6. Figure 7. Figure 8. Figure 9. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS386596L33 TPS386596L33 www.ti.com SLVSA75 – JULY 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, and VCC = 3.3V, unless otherwise noted. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS386596L33 9 PACKAGE OPTION ADDENDUM www.ti.com 29-Jul-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS386596L33DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples TPS386596L33DGKT ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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