SN65LVPE504 www.ti.com SLLSE46 – SEPTEMBER 2010 Quad Channel (Half X4 Lane) PCIe Redriver/Equalizer Check for Samples: SN65LVPE504 FEATURES 1 • • • • • • • • • DESCRIPTION 4 Identical Channel PCIe Equalizer/Redriver Support for Both PCIe Gen I (2.5Gbps) and Gen II (5.0 Gbps) Speed Selectable Equalization, De-emphasis, and Output Swing Per Channel Receive Detect (Lane Detection) Selectable Receiver Electrical Idle Threshold Control Low Operating Power Modes – Supports Three Low-Power Modes to Enable up to 80% Lower Operating Power Excellent Jitter and Loss Compensation Capability to 50" of 4-mil SL on FR4 Small Foot Print – 42 Pin 9 × 3.5 TQFN Package High Protection Against ESD Transient – HBM: 6,000 V – CDM: 1,000 V – MM: 200 V The SN65LVPE504 is a quad channel, half four lane PCIe redriver and signal conditioner supporting data rates of up to 5.0Gbps. The device complies with PCIe spec revision 2.1, supporting electrical idle and power management modes. Programmable EQ, De-Emphasis and Amplitude Swing The SN65LVPE504 is designed to minimize the signal degradation effects such as crosstalk and inter-symbol interference (ISI) that limits interconnect distance between two devices. The input stage of each channel offers selectable equalization settings that can be programmed to match loss in the channel. The differential outputs provide selectable de-emphasis to compensate for the anticipated distortion PCIe signal will experience. Both equalization and de-emphasis levels for all 4 channels are controlled by the setting of signal control pins EQ, DE and OS. See Table 1 for EQ, DE and OS setting details. spacer APPLICATIONS • PC MB, Docking Station, Server, Communication Platform, Backplane and Cabled Application PS1 PS2 RST# EN_RXD RX 1-4+ RX 1-4- Dual Termination Low Power Controller E Q U Receiver/ A Equalizer RX L I Z E R Detect TX 1-4+ CHANNEL 1-4 Receiver/ Equalizer Driver TX TX 1-4- OS Loss of Signal Detector VBB_TX EQ DE SQ_TH OS Figure 1. Data Flow Block Diagram 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated SN65LVPE504 SLLSE46 – SEPTEMBER 2010 www.ti.com DEVICE OPERATION Device PowerOn Device initiates internal power-on reset after Vcc has stabilized. External reset can also be applied at anytime by toggling RST pin. External reset is recommended after every device power-up. After 50µs (MAX) from the application of RST, device samples the state of EN_RXD, if it is set H device will enter Rx.Detect state where each of the four channels will perform Rx.Detect function (as described in PCIe spec). If EN_RXD is set L, automatic RX detect function is disabled and all channels are enabled with their termination set to ZRX_DC. Receiver Detection While EN_RXD pin is H and device is not in reset state (RST is H), LVPE504 performs RX.Detect on all its 4 channels indefinitely until remote termination is detected on at least one channel. When termination is detected on ≥ 1 CH, RX.Detect cycle is limited to 5 more tries on the other channels. At the end of 5th try those channels which failed to detect remote termination will be turned off to save power and their Rx termination is set to ZRX-HIGH. In the event device detects only three channels, all four channels are enabled. Automatic Rx detection feature on all four channels can be forced off by driving EN_RXD low. In this state all four channels input termination are set to ZRX_DC. Standby Mode This is low power state triggered by RST = L. In standby mode receiver termination resistor for each of the four channels is switched to ZRX-HIGH of >50 kΩ and transmitters are pulled to Hi-Z state. Device power is reduced to <10mW (TYP). To get device out of standby mode RST is toggled L-H. Electrical Idle Support A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode voltage. LVPE504 detects an electrical idle state when RX± input voltage of the associated channel falls below VEID_TH min and stays in this state for at least 20ns. After detection of an electrical idle state in a given channel the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds VEID_TH max, normal operation is restored and output start passing input signal. Electrical idle exit and entry time is specified at < 8 ns (MAX). Electrical idle support is independent for each channel, however to lower active power it is possible to slave electrical idle function from channel 1 to CH2-CH4. This mode is selected by driving PS2 to H. Power Save Features Device supports three power save modes as below: 1. Standby Mode This mode can be enabled from any state (Rx detect or active) by driving RST L. In this state all 4 channels have their termination set to ZRX-HIGH and outputs are at Hi-Z. Device power is 10mW (MAX). 2. Auto Low Power Mode This mode is enabled when PS1 pin is tied H and device has been in active mode, i.e., past Rx detect state for >250ms (TYP). In this mode anytime Vindiff_p-p falls below selected VEID_TH for a given channel and stays below VEID_TH for >1µs, the associated CH enters auto low power (ALP) mode where power/CH is reduced by >80% of normal operating power/CH. A CH will exit ALP mode whenever Vindiff_p-p exceeds max VEID_TH for that channel. Exit latency from ALP state is 30ns max. To use this mode link latency will need to account for the ALP exit time for N_FTS. ALP mode is handled by each channel independently based on its input differential signal level, unless slave mode is activated (PS2=H) when CH1 controls SQ detect of other channels based on its signal level. 3. Slave Power Mode This mode is activated by driving PS2 high. Under normal operation squelch detection is handled by each channel independently. In slave mode SQ detection for CH2, CH3 and CH4 are turned off and squelch function is slaved to that of CH1. By turning off squelch detection circuitry for three of the four channels device saves power. To use this feature user must ensure all channels operate simultaneously 2 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 SN65LVPE504 www.ti.com SLLSE46 – SEPTEMBER 2010 Squelch Control Controls electrical idle detect threshold level. Three levels are supported as shown in Table 1. Beacon Support With its broadband design, the SN65LVPE504 supports low frequency Beacon signal (as defined by PCIe 2.1 spec) used to indicate wake-up event to the system by a downstream device when in L2 power state. All requirements for a beacon signal as specified in PCI Express specification 2.1 must be met for device to pass beacon signals. PCIe compliant cable Instrumentation Chassis/ I/O expansion box/ Docking Station Server/PC/Notebook Cabled Midplane Mainboard Tx Rx I/O Module R R x4 I/O Hub I/O Module Tx Rx R R x4 uP I/O Module Tx Rx R R R x4 SN75LVPE504 Backplane Figure 2. LVPE504 Typical Applications Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 3 SN65LVPE504 SLLSE46 – SEPTEMBER 2010 www.ti.com DEVICE INFORMATION PS2 OS EN_RXD RST 42 41 40 39 RUA Package (Top View) 1 38 VCC NC 2 37 NC RX1+ 3 36 TX1+ RX1– 4 35 TX1– GND 5 34 GND RX2+ 6 33 TX2+ RX2– 7 32 TX2– GND 8 31 GND VCC 9 30 VCC 29 GND 28 TX3+ RX3– 12 27 TX3– GND 13 26 GND RX4+ 14 25 TX4+ RX4– 15 24 TX4– NC 16 23 NC VCC 17 22 VCC EQ 19 PS1 18 RX3+ 11 DE 21 GND 10 SQ_TH 20 SN65LVPE504 VCC Figure 3. Flow-Through Pin-Out PIN FUNCTIONS PIN NO. NAME I/O TYPE DESCRIPTION HIGH SPEED DIFFERENTIAL I/O PINS 3 4 RX1+ 4 RX1– 6 RX2+ 7 RX2– 11 RX3+ 12 RX3– 14 RX4+ 15 RX4– 36 TX1+ 35 TX1– 33 TX2+ 32 TX2– I, CML Non-inverting and inverting CML differential input for CH 1 and CH 4. These pins are tied to an internal voltage bias by dual termination resistor circuit O, CML Non-inverting and inverting CML differential output for CH 1 and CH 4. These pins are internally tied to voltage bias by termination resistors Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 SN65LVPE504 www.ti.com SLLSE46 – SEPTEMBER 2010 PIN FUNCTIONS (continued) PIN NO. I/O TYPE NAME DESCRIPTION HIGH SPEED DIFFERENTIAL I/O PINS (continued) 28 TX3+ 27 TX3– 25 TX4+ 24 TX4– Non-inverting and inverting CML differential output for CH 1 and CH 4. These pins are internally tied to voltage bias by termination resistors O, CML DEVICE CONTROL PIN 40 EN_RXD I, LVCMOS Sets device operation modes per Table 1. Internally pulled to VCC 42 PS2 I, LVCMOS Tying pin to VCC slaves CH2-4 electrical idle and Rx.Detect function to CH1. Internally pulled to GND 18 PS1 I, LVCMOS Select auto-low power save mode per Table 1. Internally pulled to GND 20 SQ_TH (1) I, LVCMOS Squelch threshold level select pin for electrical idle detect per Table 1 Internally pulled to VCC/2 39 RST I, LVCMOS Reset device, input active Low. Internally pulled to VCC SIGNAL CONDITIONING PINS (1) 21 DE I, LVCMOS Selects de-emphasis settings for CH 1-CH 4 per Table 1. Internally pulled to Vcc/2 19 EQ I, LVCMOS Selects equalization settings for CH 1-CH 4 per Table 1. Internally pulled to Vcc/2 41 OS I, LVCMOS Selects output amplitude for CH 1-CH 4 per Table 1. Internally pulled to Vcc/2 1,9,17,22,30,38 VCC Power Positive supply should be 3.3V ± 10% 5,8,10,13, 26,29,31,34û GND Power Supply ground POWER PINS (1) Internally biased to Vcc/2 with >200kΩ pull-up/pull-down. When 3-state pins are left as NC, board leakage at the pin pad must be < 1 µA otherwise drive to Vcc/2 to assert mid-level state. Table 1. Control Pin Settings OUTPUT SWING (CH1-CH4) at 5Gbps SQUELCH THRESHOLD (CH1-CH4) OS TRANSITION BIT AMPLITUDE (TYP mVpp) SQ_TH MIN DIFFERENTIAL INPUT (CH1-CH4) 0 800 0 47 mVpp NC (default) 929 NC (default) 61 mVpp 1 1047 1 83 mVpp OUTPUT DE-EMPHASIS (CH1-CH4) at 5Gbps INPUT EQUALIZATION (CH1-CH4) DE OS = NC OS = 0 OS = 1 EQ NC (default) –3.4dB –2.1dB –4.6dB 0 0 0 –6.2dB –4.9dB –7.2dB NC 7 (default) 1 –10.3dB –9.2dB –11dB 1 15 EN_RXD DEVICE FUNCTION 0 Set input termination to Rx_DC 1 Perform Rx detect after power up RST DEVICE FUNCTION 0 Device in standby state, inputs set to Hi-Z 1 Device in active mode PS1 DEVICE FUNCTION 0 Auto-low power mode disabled (default) 1 Auto-low power mode enabled PS2 Equalization dB (at 5Gbps) DEVICE FUNCTION 0 Electrical Idle and Rx Detect independent for CH1-CH4 (default) 1 CH2-CH4 Electrical Idle and Rx Detect slaved to CH1 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 5 SN65LVPE504 SLLSE46 – SEPTEMBER 2010 www.ti.com ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE SN65LVPE504RUAR LVPE504 42-pin RUA Reel (large) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage range (2) Voltage range VALUE UNIT VCC –0.5 to 4 V Differential I/O –0.5 to 4 V –0.5 to VCC + 0.5 V Control I/O Human body model Electrostatic discharge (3) ±6000 V Charged-device model (4) ±1000 V Machine model (5) ±200 V Continuous power dissipation (1) (2) (3) (4) (5) See Thermal Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method C101-A Tested in accordance with JEDEC Standard 22, Test Method A115-A THERMAL INFORMATION THERMAL METRIC SN65LVPE504 UNITS TQFN (42 PINS) qJA Junction-to-ambient thermal resistance 30 qJCtop Junction-to-case (top) thermal resistance 12 qJB Junction-to-board thermal resistance 10 yJT Junction-to-top characterization parameter 0.5 yJB Junction-to-board characterization parameter 9 qJCbot Junction-to-case (bottom) thermal resistance 4.7 °C/W RECOMMENDED OPERATING CONDITIONS VCC Supply voltage CCOUPLING AC Coupling capacitor Operating free-air temperature 6 Submit Documentation Feedback MIN TYP 3 3.3 MAX UNITS 3.6 V 75 200 nF –40 85 °C Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 SN65LVPE504 www.ti.com SLLSE46 – SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS under recommended operating conditions PARAMETER CONDITIONS MIN TYP MAX UNITS DEVICE PARAMETERS ICC RST, DEx, EQx, OS = NC, EN_RXD = NC, K28.5 pattern at 5 Gbps, VID = 1000mVp-p 174 190 ICCSlave PS2 = Vcc; RST, DEx, EQx, OS = NC, EN_RXD = NC, K28.5 pattern at 5 Gbps, VID = 1000mVp-p 161 175 When auto-low power conditions are met, PS1 = VCC 27 32 PS1, PS2 = VCC and link in EID state 14 18 ICCNO_CONNECT EN_RXD = 1 No termination detected on any CH 2.5 ICCstdby RST = GND Supply current ICCALP ICCALP _Slave 0.1 Maximum data rate 5 AutoLPENTRY Auto low power entry time Electrical idle at input, Refer to Figure 7 AutoLPEXIT Auto low power exit time After first signal activity, Refer to Figure 7 tENB Device enable time RST 0 → 1 tDIS Device disable time RST 1 → 0 Rx.Detect start event EN_RXD = 1, Time to start Rx Detect after power up TRX.Detect mA Gbps 1 µs 30 ns 5 50 µs 0.1 2 µs 6 µs CONTROL LOGIC VIH High level Input Voltage 1.4 Vcc VIL Low Level Input Voltage –0.3 0.5 VHYS Input Hysteresis IIH High Level Input Current IIL Low Level Input Current V V 150 OS, EQ, DE, SQ_TH, PS1, PS2 = VCC mV 30 EN_RXD, RST = VCC µA 1 PS1, PS2 = GND –1 OS, EQ, DE, SQ_TH, EN_RXD, RST = GND –30 100 µA RECEIVER AC/DC Vindiff_p-p RX1-RX4 Input voltage swing AC coupled differential signal (5Gbps) TRX_TJ Max Rx total timing error At device pin (5Gbps) 0.4 UI TRX_DJ Max Rx deterministic timing error At device pin (5Gbps) 0.3 UI VCM_RX RX1-RX4 Common mode voltage 3.6 V VinCOM_P RX1-RX4 AC peak common mode voltage 150 mVP ZRX_DC DC single ended impedance 40 55 60 Ω ZRX_Diff DC Differential input impedance 80 98 120 Ω ZRX_High DC Input high impedance 50 75 VEID_TH Electrical idle detect threshold 0 Device in standby mode. Rx termination not powered measured with respect to GND over 200 mV max Measured at receiver pin: SQ_TH = NC SQ_TH = 1 Differential return loss RLRX-CM Common mode return loss mVp-p kΩ 61 58 SQ_TH = 0 RLRX-DIFF 1200 83 107 mVpp 47 50 MHz – 1.25 GHz 10 15 1.25 GHz – 2.5 GHz 8 11 50 MHz – 2.5 GHz 9 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 dB dB 7 SN65LVPE504 SLLSE46 – SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) under recommended operating conditions PARAMETER CONDITIONS MIN TYP MAX 866 929 1031 UNITS TRANSMITTER AC/DC RL = 100Ω ±1%, OS = NC, transition Bit VTXDIFF_P-P Differential peak-to-peak output voltage De-emphasis level RL = 100Ω ±1%, OS = GND transition Bit 800 RL = 100Ω ±1% OS = VCC transition Bit 1047 RL = 100Ω ±1%, DE=NC, OS = 0,1,NC on-transition bit 620 RL = 100Ω ±1%, DE=OS = 0,1,NC on-transition bit 456 RL = 100Ω ±1%, DE=OS = 0,1,NC on-transition bit 288 OS = NC (Figure 9) for OS = 1 and NC see Table 1) –3.0 –3.4 –5.5 –6.2 –6.5 –9.0 –10.3 –10.6 TDE De-emphasis width At 5 Gbps ZTX_diff DC Differential impedance Defined during signaling 80 100 f = 50 MHz – 1.25 GHz 10 20 f = 1.25 GHz – 2.5 GHz 8 13 6 12 RLdiff_TX Differential return loss RLCM_TX Common mode return loss f = 50 MHz – 2.5 GHz ITX_SC TX short circuit current TX± shorted to GND VTX_CM_DC mV –4.0 0.9 dB UI 120 Ω dB dB 44 90 mA Transmitter DC common-mode Allowed DC CM voltage at TX pins voltage 1.8 2.2 V VTX_CM_AC2 TX AC common mode voltage at Gen II speed Max(Vd+ + Vd–) /2 – Min(Vd+ + Vd–)/2 30 100 mVpp VTX_CM_AC1 TX AC common mode voltage at Gen I speed RMS(Vd+ + Vd–)/2 – DCAVG(Vd+ + Vd–)/2 3 20 mV VTX_CM_DeltaL0- Absolute Delta DC CM voltage |VTX_CM_DC [L0] – VTX_CM_DC [L0s] | during active and idle states 0 100 mV Absolute delta of DC CM voltage between D+ and D– |VTX_CM_DC–D+ [L0] – VTX_CM_DC–D– [L0] | 0 25 mV VTX_idle_diff-AC-p Electrical idle differential peak output voltage |VTX-Idle-D+ – VTX-Idle-D–|, LP filtered to remove any DC component 0 20 mVpp VTX_idle_diff-DC DC electrical idle differential output voltage |VTX_idle-D+ – VTX_idle-D–|, LP filtered to remove any AC component Vdetect Voltage change to allow receiver detect Positive voltage to sense receiver tR,tF Output rise/fall time De-Emphasis = 0 dB, OS = NC (CH 0 and CH 1) 20%-80% of differential voltage at the output tRF_MM Output rise/fall time mismatch De-Emphasis = 0dB, OS = NC (CH 0 and CH 1) 20%-80% of differential voltage at the output Tdiff_LH, Tdiff_HL Differential propagation delay De-Emphasis = 0dB (CH 0 and CH 1). Propagation delay between 50% level at input and output TINTRA_SKEW Output skew (same lane) 5 Gbps TINTER_SKEW Lane to lane skew 5 Gbps tidleEntry, tidleExit Idle entry and exit times See Figure 5 Ttx_EID_min Minimum time in EID L0s VTX_CM-DC-LineDelta 1 1.9 30 55 280 –25 mV 600 mV 70 ps 20 ps 350 ps 15 ps 25 ps 8 ns 20 ns Tx EQUALIZATION AT GEN II SPEED TXDJ (1) Residual deterministic jitter TXRJ (1) 8 Residual random jitter At point A1 in Figure 8, EQ/DE=NC, OS=HIGH 25 60 At point A2 in Figure 8, EQ/DE=NC, OS=LOW 26 60 At point B in Figure 8, EQ/DE=NC, OS=HIGH 27 60 D24.3 pattern at point A1/A2/B in Figure 8 0.1 ps p-p psrms Refer to Figure 8 with ±K28.5 pattern, –3.5dB DE from source AWG Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 SN65LVPE504 www.ti.com SLLSE46 – SEPTEMBER 2010 IN Tdiff_HL Tdiff_LH OUT Figure 4. Propagation Delay IN+ VEID_TH Vcm INtidleEntry tidleExit OUT+ Vcm OUT- Figure 5. Idle Mode Exit and Entry Delay 80 % 20 % tr tf Figure 6. Output Rise and Fall Times RX_1-4+ VCMRX RX_1-4tidleEntry AutoLPEXIT TX_1-4+ VCMTX TX_1-4AutoLP ENTRY Power Saving Mode Figure 7. Auto Low Power Mode Timing (when enabled) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 9 SN65LVPE504 SLLSE46 – SEPTEMBER 2010 www.ti.com A1 X = 40", 4mil SL on FR4 2" AWG* CH 2" Jitter Measurement Y = 8", 5mil SL on FR4 5 Gbps Signal Gen. K28.5 pattern, 800mVpp B A2 X = 25", 4mil SL on FR4 2" AWG* CH 2" Jitter Measurement Y = 23", 5mil SL on FR4 5 Gbps Signal Gen. K28.5 pattern, 800mVpp Figure 8. Jitter Measurement Setup 1-bit 1 to N bits tDE 1-bit 1 to N bits DEx/OSx = NC -3.4dB -6.2dB DEx = 0; OSx = NC -10.3dB Vcm DiffVppTX DEx = 1; OSx = NC DiffVppTX_DE tDE Figure 9. Output De-Emphasis Levels 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 SN65LVPE504 www.ti.com SLLSE46 – SEPTEMBER 2010 TYPICAL CHARACTERISTICS TYPICAL EYE DIAGRAM AND PERFORMANCE CURVES • • • • Input Signal Characteristics – VID = 1000mVpp, DE = –3.5 dB, Pattern = K28.5 Device Operating Conditions: VCC = 3.3 V, Temp = 25°C All trace are 4 mils PCIe Gen I and Gen II compliance mask shown AT GEN II SPEED Input Trace = 4", Output Trace = 8" EQ = 0 dB, OS = 833 mVpp, DE = - 1.9 dB Input Trace = 4", Output Trace = 16" EQ = 0 dB, OS = 1166 mVpp, DE = - 4.9 dB Figure 10. Figure 11. Input Trace = 4", Output Trace = 28" EQ = 0 dB, OS = 1166 mVpp, DE = - 7.4 dB Input Trace = 16", Output Trace = 4" EQ = 0 dB, OS = 833 mVpp, DE = - 1.9 dB Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 11 SN65LVPE504 SLLSE46 – SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Input Trace = 28", Output Trace = 4" EQ = 7 dB, OS = 833 mVpp, DE = - 1.9 dB Input Trace = 36", Output Trace = 4" EQ = 7 dB, OS = 833 mVpp, DE = - 1.9 dB Figure 14. Figure 15. Input Trace = 48", Output Trace = 4" EQ = 15 dB, OS = 833 mVpp, DE = - 1.9 dB Figure 16. AT GEN I SPEED Input Trace = 4", Output Trace = 8" EQ = 7 dB, OS = 833 mVpp, DE = - 1.9 dB Input Trace = 4", Output Trace = 16" EQ = 7 dB, OS = 1166 mVpp, DE = - 4.9 dB Figure 17. 12 Figure 18. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 SN65LVPE504 www.ti.com SLLSE46 – SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) Input Trace = 4", Output Trace = 28" EQ = 7 dB, OS = 1166 mVpp, DE = - 7.4 dB Input Trace = 16", Output Trace = 4" EQ = 7 dB, OS = 833 mVpp, DE = - 1.9 dB Figure 19. Figure 20. Input Trace = 28", Output Trace = 4" EQ = 15 dB, OS = 833 mVpp, DE = - 1.9 dB Input Trace = 36", Output Trace = 4" EQ = 15 dB, OS = 833 mVpp, DE = - 1.9 dB Figure 21. Figure 22. Input Trace = 48", Output Trace = 4" EQ = 15 dB, OS = 833 mVpp, DE = - 1.9 dB Figure 23. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN65LVPE504 13 PACKAGE OPTION ADDENDUM www.ti.com 4-Oct-2010 PACKAGING INFORMATION Orderable Device SN65LVPE504RUAR Status (1) ACTIVE Package Type Package Drawing WQFN RUA Pins Package Qty 42 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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