LMX2377U PLLatinum™ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications 2.5 GHz/1.2 GHz General Description Features The LMX2377U device is a high performance frequency synthesizer with integrated dual modulus prescalers. The LMX2377U device is designed for use as a local oscillator for the first and second RF of a dual conversion radio transceiver. A 16/17 or a 32/33 prescale ratio can be selected for the Main synthesizer. An 8/9 or a 16/17 prescale ratio can be selected for the Aux synthesizer. Using a proprietary digital phase lock technique, the LMX2377U device generates very stable, low noise control signals for UHF and VHF voltage controlled oscillators. Both the Main and Aux synthesizers include a two-level programmable charge pump. The Main synthesizer has dedicated Fastlock circuitry. Serial data is transferred to the devices via a three-wire interface (Data, LE, Clock). The low voltage logic interface allows connection to 1.8V devices. Supply voltages from 2.7V to 5.5V are supported. The LMX2377U features ultra low current consumption, typically 3.5 mA at 3.0V. The LMX2377U devices are available in 20-Pin TSSOP, 24-Pin CSP, and 20-Pin UTCSP surface mount plastic packages. n n n n n Thin Shrink Small Outline Package (MTC20) n n n n n n Ultra Low Current Consumption Upgrade and Compatible to the LMX2370 2.7V to 5.5V Operation 1.8V to 5.0V MICROWIRE Logic Interface Selectable Synchronous or Asynchronous Powerdown Mode: ICC-PWDN = 1 µA typical Selectable Dual Modulus Prescaler: Main: 16/17 or 32/33 Aux: 8/9 or 16/17 Selectable Charge Pump TRI-STATE ® Mode Programmable Charge Pump Current Levels Main and Aux: 0.95 or 3.8 mA Selectable Fastlock™ Mode for the Main Synthesizer Open Drain Analog Lock Detect Output Available in 20-Pin TSSOP, 24-Pin CSP, and 20-Pin UTCSP Applications n Mobile Handsets (GSM, GPRS, W-CDMA, CDMA, PCS, AMPS, PDC, DCS) n Cordless Handsets (DECT, DCT) n Wireless Data n Cable TV Tuners Chip Scale Package (SLB24A) Ultra Thin Chip Scale Package (SLE20A) 20022695 20022680 20022681 PLLatinum™ is a trademark of National Semiconductor Corporation. © 2002 National Semiconductor Corporation DS200226 www.national.com LMX2377U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications November 2002 LMX2377U Functional Block Diagram 20022604 www.national.com 2 LMX2377U Connection Diagrams Thin Shrink Small Outline Package (TM) (Top View) Chip Scale Package (SLB) (Top View) 20022602 20022603 Ultra Thin Chip Scale Package (SLE) (Top View) 20022696 Pin Descriptions Pin Name Pin No. 20-Pin UTCSP Pin No. 24-Pin CSP Pin No. 20-Pin TSSOP I/O Description VCC 20 24 1 — Power supply bias for the Main PLL analog and digital circuits. VCC may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. VP Main 1 2 2 — Main PLL charge pump power supply. Must be ≥ VCC. Do Main 2 3 3 O Main PLL charge pump output. The output is connected to the external loop filter, which drives the input of the VCO. GND 3 4 4 — Ground for the Main PLL digital circuitry. fIN Main 4 5 5 I Main PLL prescaler input. Small signal input from the VCO. 3 www.national.com LMX2377U Pin Descriptions (Continued) Pin Name Pin No. 20-Pin UTCSP Pin No. 24-Pin CSP Pin No. 20-Pin TSSOP I/O Description fIN Main 5 6 6 I Main prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX2377U Main PLL can be driven differentially when the bypass capacitor is omitted. GND 6 7 7 — OSCin 7 8 8 I Reference oscillator input. It has an approximate VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. GND 8 10 9 — Ground for the Aux PLL digital circuitry, MICROWIRE, FoLD, and oscillator circuits. FoLD 9 11 10 O Programmable multiplexed output pin. Functions as a general purpose CMOS TRI-STATE output, Main/Aux PLL open drain analog lock detect output, N and R divider output or Fastlock output, which connects a parallel resistor to the external loop filter. Clock 10 12 11 I MICROWIRE Clock input. High impedance CMOS input. Data is clocked into the 22-bit shift register on the rising edge of Clock. Data 11 14 12 I MICROWIRE Data input. High impedance CMOS input. Binary serial data. The MSB of Data is shifted in first. The last two bits are the control bits. LE 12 15 13 I MICROWIRE Latch Enable input. High impedance CMOS input. When LE transitions HIGH, Data stored in the shift register is loaded into one of 4 internal control registers. Vµc 13 16 14 — Power supply bias for the MICROWIRE circuitry. Must be ≤ VCC. Typically connected to the same supply level as the microprocessor or baseband controller to enable programming at low voltages. GND 14 17 15 — Ground for the Aux PLL analog circuitry. fIN Aux 15 18 16 I GND 16 19 17 — Ground for the Aux PLL digital circuitry, MICROWIRE, FoLD, and oscillator circuits. Do Aux 17 20 18 O Aux PLL charge pump output. the output is connected to an external loop filter, which drives the input of the VCO. VP Aux 18 22 19 — Aux PLL charge pump power supply. Must be ≥ VCC. VCC 19 23 20 — Power supply bias for the Aux PLL analog and digital circuits, FoLD, and oscillator circuits. VCC may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. NC — 1, 9, 13, 21 — — No Connect www.national.com Ground for the Main PLL analog circuitry. Aux PLL prescaler input. Small signal input from the VCO. 4 Model Temperature Range Package Description Packing NS Package Number LMX2377USLEX −40˚C to +85˚C Ultra Thin Chip Scale Package (UTCSP) Tape and Reel 2500 Units Per Reel SLE20A LMX2377USLBX −40˚C to +85˚C Chip Scale Package (CSP) Tape and Reel 2500 Units Per Reel SLB24A LMX2377UTM −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) 73 Units Per Rail MTC20 LMX2377UTMX −40˚C to +85˚C Thin Shrink Small Outline Package (TSSOP) Tape and Reel 2500 Units Per Reel MTC20 5 www.national.com LMX2377U Ordering Information LMX2377U Detailed Block Diagram 20022608 Notes: 1. VCC supplies power to the Main and Aux prescalers, Main and Aux feedback dividers, Main and Aux reference dividers, Main and Aux phase detectors, the OSCin buffer, and FoLD circuitry. 2. Vµc supplies power to the MICROWIRE circuitry. 3. VP Main and VP Aux supply power to the charge pumps. They can be run separately as long as VP Main ≥ VCC and VP Aux ≥ VCC. www.national.com 6 Recommended Operating Conditions (Note 1) (Notes 1, 2, 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage VCC to GND Power Supply Voltage VCC to GND −0.3V to +6.5V VP Main to GND −0.3V to +6.5V VP Aux to GND −0.3V to +6.5V VI must be < +6.5V −65˚C to +150˚C TSSOP θJA Thermal Impedance CSP θJA Thermal Impedance VCC to +5.5V VP Aux to GND VCC to +5.5V −40˚C to +85˚C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, refer to the Electrical Characteristics section. The guaranteed specifications apply only for the conditions listed. −0.3V to VCC+0.3V Lead Temperature (solder 4 s) (TL) +2.7V to +5.5V VP Main to GND Operating Temperature (TA) Voltage on any pin to GND (VI) Storage Temperature Range (TS) LMX2377U Absolute Maximum Ratings Note 2: This device is a high performance RF integrated circuit with an ESD rating < 2 kV and is ESD sensitive. Handling and assembly of this device should only be done at ESD protected work stations. +260˚C 114.5˚C/W Note 3: GND = 0V 112˚C/W Electrical Characteristics VCC = VP Main = VP Aux = Vµc = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units ICC PARAMETERS ICCMain + Aux Power Supply Current, Main + Aux Synthesizers Clock, Data and LE = GND OSCin = GND PWDN Main Bit = 0 PWDN Aux Bit = 0 3.5 4.6 mA ICCMain Power Supply Current, Main Synthesizer Only Clock, Data and LE = GND OSCin = GND PWDN Main Bit = 0 PWDN Aux Bit = 1 2.3 3.0 mA ICCAux Power Supply Current, Aux Synthesizer Only Clock, Data and LE = GND OSCin = GND PWDN Main Bit = 1 PWDN Aux Bit = 0 1.0 1.6 mA ICC-PWDN Powerdown Current Clock, Data and LE = GND OSCin = GND PWDN Main Bit = 1 PWDN Aux Bit = 1 1.0 10.0 µA 500 2500 MHz Prescaler = 16/17 (Note 4) 48 131087 Prescaler = 32/33 (Note 4) 96 262143 2 32767 MAIN SYNTHESIZER PARAMETERS fIN Main Main Operating Frequency NMain Main N Divider Range RMain Main R Divider Range FφMain Main Phase Detector Frequency PfIN Main Main Input Sensitivity 10 MHz 2.7V ≤ VCC ≤ 3.0V (Note 5) −15 0 dBm 3.0V < VCC ≤ 5.5V (Note 5) −10 0 dBm 7 www.national.com LMX2377U Electrical Characteristics (Continued) VCC = VP Main = VP Aux = Vµc = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units MAIN SYNTHESIZER PARAMETERS IDo Main SOURCE IDo Main SINK Main Charge Pump Output Source Current Main Charge Pump Output Sink Current VDo Main = VP Main/2 IDo Main Bit = 0 (Note 6) -0.95 mA VDo Main = VP Main/2 IDo Main Bit = 1 (Note 6) -3.80 mA VDo Main = VP Main/2 IDo Main Bit = 0 (Note 6) 0.95 mA VDo Main = VP Main/2 IDo Main Bit = 1 (Note 6) 3.80 mA 0.5V ≤ VDo Main ≤ VP Main - 0.5V (Note 6) IDo Main TRI-STATE Main Charge Pump Output TRI-STATE Current IDo Main SINK Vs IDo Main SOURCE Main Charge Pump Output Sink Current VDo Main = VP Main/2 Vs Charge Pump Output Source Current TA = 25˚C (Note 7) Mismatch IDo Main Vs VDo Main Main Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage IDo Main Vs TA Main Charge Pump Output Current Magnitude Variation Vs Temperature -2.5 2.5 nA 3 10 % 0.5V ≤ VDo Main ≤ VP Main - 0.5V TA = 25˚C (Note 7) 10 15 % VDo Main = VP Main/2 (Note 7) 10 % AUX SYNTHESIZER PARAMETERS fIN Aux Aux Operating Frequency NAux Aux N Divider Range RAux Aux R Divider Range FφAux Aux Phase Detector Frequency PfIN Aux Aux Input Sensitivity www.national.com 45 1200 Prescaler = 8/9 (Note 4) 24 65559 Prescaler = 16/17 (Note 4) 48 131087 2 32767 2.7V ≤ VCC ≤ 5.5V (Note 5) 8 -10 MHz 10 MHz 0 dBm (Continued) VCC = VP Main = VP Aux = Vµc = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units AUX SYNTHESIZER PARAMETERS IDo Aux SOURCE IDo Aux SINK Aux Charge Pump Output Source Current Aux Charge Pump Output Sink Current VDo Aux = VP Aux/2 IDo Aux Bit = 0 (Note 6) -0.95 mA VDo Aux = VP Aux/2 IDo Aux Bit = 1 (Note 6) -3.80 mA VDo Aux = VP Aux/2 IDo Aux Bit = 0 (Note 6) 0.95 mA VDo Aux = VP Aux/2 IDo Aux Bit = 1 (Note 6) 3.80 mA 0.5V ≤ VDo Aux ≤ VP Aux - 0.5V (Note 6) IDo Aux TRI-STATE Aux Charge Pump Output TRI-STATE Current IDo Aux SINK Vs IDo Aux SOURCE Aux Charge Pump Output Sink Current VDo Aux = VP Aux/2 Vs Charge Pump Output Source Current TA = 25˚C (Note 7) Mismatch IDo Aux Vs VDo Aux Aux Charge Pump Output Current Magnitude Variation Vs Charge Pump OutputVoltage IDo Aux Vs TA Aux Charge Pump Output Current Magnitude Variation Vs Temperature -2.5 2.5 nA 3 10 % 0.5V ≤ VDo Aux ≤ VP Aux - 0.5V TA = 25˚C (Note 7) 10 15 % VDo Aux = VP Aux/2 (Note 7) 10 % OSCILLATOR PARAMETERS FOSC Oscillator Operating Frequency VOSC Oscillator Sensitivity (Note 8) IOSC Oscillator Input Current VOSC = VCC = 5.5V VOSC = 0V, VCC = 5.5V 9 2 40 MHz 0.5 VCC VPP 100 µA -100 µA www.national.com LMX2377U Electrical Characteristics LMX2377U Electrical Characteristics (Continued) VCC = VP Main = VP Aux = Vµc = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units DIGITAL INTERFACE (Data, LE, Clock, FoLD) VIH High-Level Input Voltage 1.72V ≤ Vµc ≤ 5.5V VIL Low-Level Input Voltage 1.72V ≤ Vµc ≤ 5.5V 0.2 Vµc V IIH High-Level Input Current VIH = Vµc = 5.5V −1.0 1.0 µA IIL Low-Level Input Current VIL = 0V, Vµc = 5.5V −1.0 1.0 µA VOH High-Level Output Voltage IOH = −500 µA VOL Low-Level Output Voltage IOL = 500 µA 0.8 Vµc V VCC − 0.4 V 0.4 V MICROWIRE INTERFACE tCS Data to Clock Set Up Time (Note 9) 50 tCH Data to Clock Hold Time (Note 9) 20 ns tCWH Clock Pulse Width HIGH (Note 9) 50 ns tCWL Clock Pulse Width LOW (Note 9) 50 ns tES Clock to Load Enable Set Up Time (Note 9) 50 ns tEW Latch Enable Pulse Width (Note 9) 50 ns www.national.com 10 ns (Continued) VCC = VP Main = VP Aux = Vµc = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol Parameter Conditions Value Min Typ Max Units PHASE NOISE CHARACTERISTICS LN(f) Main Main Synthesizer Normalized Phase Noise Contribution (Note 10) TCXO Reference Source IDo Main Bit = 1 -212.0 dBc/ Hz L(f) Main Main Synthesizer Single Side Band Phase Noise Measured fIN Main = 2450 MHz f = 1 kHz Offset FφMain = 200 kHz Loop Bandwidth = 7.5 kHz N = 12250 FOSC = 10 MHz VOSC = 0.632 VPP IDo Main Bit = 1 PWDN Aux Bit = 1 TA = 25˚C (Note 11) -77.24 dBc/ Hz LN(f) Aux Aux Synthesizer Normalized Phase Noise Contribution (Note 10) TCXO Reference Source IDo Aux Bit = 1 -212.0 dBc/ Hz L(f) Aux Aux Synthesizer Single Side Band Phase Noise Measured fIN Aux = 900 MHz f = 1 kHz Offset FφAux = 200 kHz Loop Bandwidth = 12 kHz N = 4500 FOSC = 10 MHz VOSC = 0.632 VPP IDo Aux Bit = 1 PWDN Main Bit = 1 TA = 25˚C (Note 11) -85.94 dBc/ Hz Note 4: Some of the values in this range are illegal divide ratios (B < A). To obtain continuous legal division, the Minimum Divide Ratio must be calculated. Use N ≥ P * (P−1), where P is the value of the prescaler selected. Note 5: Refer to the LMX2377U fIN Sensitivity Test Setup section Note 6: Refer to the LMX2377U Charge Pump Test Setup section Note 7: Refer to the Charge Pump Current Specification Definitions for details on how these measurements are made. Note 8: Refer to the LMX2377U OSCin Sensitivity Test Setup section Note 9: Refer to the LMX2377U Serial Data Input Timing section Note 10: Normalized Phase Noise Contribution is defined as : LN(f) = L(f) − 20 log (N) − 10 log (Fφ), where L(f) is defined as the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL’s loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. N is the value selected for the feedback divider and Fφ is the Main/Aux phase detector comparison frequency.. Note 11: The synthesizer phase noise is measured with the LMX2370TMEB/LMX2370SLBEB/LMX2370SLEEB Evaluation boards and the HP8566B Spectrum Analyzer. 11 www.national.com LMX2377U Electrical Characteristics LMX2377U Typical Performance Characteristics Sensitivity LMX2377U fIN Main Input Power Vs Frequency VCC = VP Main = Vµc = 3.0V 20022642 LMX2330U fIN Main Input Power Vs Frequency VCC = VP Main = Vµc = 5.5V 20022643 www.national.com 12 LMX2377U Typical Performance Characteristics Sensitivity (Continued) LMX2377U fIN Aux Input Power Vs Frequency VCC = VP Aux = Vµc = 3.0V 20022646 LMX2377U fIN Aux Input Power Vs Frequency VCC = VP Aux = Vµc = 5.5V 20022647 13 www.national.com LMX2377U Typical Performance Characteristics Sensitivity (Continued) LMX2377U OSCin Input Voltage Vs Frequency VCC = Vµc = 3.0V 20022652 LMX2377U OSCin Input Voltage Vs Frequency VCC = Vµc = 5.5V 20022653 www.national.com 14 LMX2377U Typical Performance Characteristics Charge Pump LMX2377U Main Charge Pump Sweeps −40˚C ≤ TA ≤ +85˚C, Vµc = VCC 20022660 15 www.national.com LMX2377U Typical Performance Characteristics Charge Pump (Continued) LMX2377U Aux Charge Pump Sweeps −40˚C ≤ TA ≤ +85˚C, Vµc = VCC 20022661 www.national.com 16 LMX2377U Typical Performance Characteristics Input Impedance LMX2377U TSSOP fIN Main and fIN Aux Input Impedance VCC = Vµc = 5.5V, TA = +25˚C LMX2377U TSSOP fIN Main and fIN Aux Input Impedance VCC = Vµc = 3.0V, TA = +25˚C 20022666 20022667 LMX2377U CSP fIN Main and fIN Aux Input Impedance VCC = Vµc = 5.5V, TA = +25˚C LMX2377U CSP fIN Main and fIN Aux Input Impedance VCC = Vµc = 3.0V, TA = +25˚C 20022668 20022669 17 www.national.com www.national.com 18 LMX2377U TSSOP and LMX2377U CSP fIN Main and fIN Aux Input Impedance Table Typical Performance Characteristics Input Impedance (Continued) 20022670 LMX2377U LMX2377U Typical Performance Characteristics Input Impedance (Continued) LMX2377U UTCSP fIN Main and fIN Aux Input Impedance VCC = Vµc = 5.5V, TA = +25˚C LMX2377U UTCSP fIN Main and fIN Aux Input Impedance VCC = Vµc = 3.0V, TA = +25˚C 20022697 20022697 19 www.national.com www.national.com 20 LMX2377U UTCSP fIN Main and fIN Aux Input Impedance Table Typical Performance Characteristics Input Impedance (Continued) 20022698 LMX2377U LMX2377U Typical Performance Characteristics Input Impedance (Continued) LMX2377U TSSOP OSCin Input Impedance Vs Frequency TA = +25˚C 20022676 LMX2377U CSP OSCin Input Impedance Vs Frequency TA = +25˚C 20022677 21 www.national.com www.national.com 22 LMX2377U TSSOP and LMX2377U CSP OSCin Input Impedance Table Typical Performance Characteristics Input Impedance (Continued) 20022678 LMX2377U LMX2377U Typical Performance Characteristics Input Impedance (Continued) LMX2377U UTCSP OSCin Input Impedance Vs Frequency TA = +25˚C 200226A1 23 www.national.com www.national.com 24 Typical Performance Characteristics Input Impedance (Continued) LMX2377U UTCSP OSCin Input Impedance Table 200226A2 LMX2377U LMX2377U Charge Pump Current Specification Definitions 20022637 I1 = Charge Pump Sink Current at VDo = VP − ∆V I2 = Charge Pump Sink Current at VDo = VP/2 I3 = Charge Pump Sink Current at VDo = ∆V I4 = Charge Pump Source Current at VDo = VP − ∆V I5 = Charge Pump Source Current at VDo = VP/2 I6 = Charge Pump Source Current at VDo = ∆V ∆V = Voltage offset from the positive and negative rails. Dependent on the VCO tuning range relative to VCC and GND. Typical values are between 0.5V and 1.0V. VP refers to either VP Main or VP Aux VDo refers to either VDo Main or VDo Aux IDo refers to either IDo Main or IDo Aux Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage 20022663 Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch 20022664 Charge Pump Output Current Magnitude Variation Vs Temperature 20022665 25 www.national.com LMX2377U Test Setups LMX2377U Charge Pump Test Setup 20022650 The block diagram above illustrates the setup required to measure the LMX2377U device’s Main charge pump sink current. The same setup is used for the LMX2370TMEB/ LMX2370SLEEB Evaluation Boards. The Aux charge pump measurement setup is similar to the Main charge pump measurement setup. The purpose of this test is to assess the functionality of the Main charge pump. This setup uses an open loop configuration. A power supply is connected to Vcc and swept from 2.7V to 5.5V. The MICROWIRE power supply, Vµc, is tied to Vcc. By means of a signal generator, a 10 MHz signal is typically applied to the fIN Main pin. The signal is one of two inputs to the phase detector. The 3 dB pad provides a 50 Ω match between the PLL and the signal generator. The OSCin pin is tied to Vcc. This establishes the other input to the phase detector. Alternatively, this input can be tied directly to the ground plane. With the Do Main pin connected to a Semiconductor Parameter Analyzer in this way, the sink, source, and TRI-STATE currents can be measured by simply toggling the Phase Detector Polarity and Charge Pump State states in Code www.national.com Loader. Similarly, the LOW and HIGH currents can be measured by switching the Charge Pump Gain’s state between 1X and 4X in Code Loader. Let Fr represent the frequency of the signal applied to the OSCin pin, which is simply zero in this case (DC), and let Fp represent the frequency of the signal applied to the fIN Main pin. The phase detector is sensitive to the rising edges of Fr and Fp. Assuming positive VCO characteristics; the charge pump turns ON and sinks current when the first rising edge of Fp is detected. Since Fr has no rising edge, the charge pump continues to sink current indefinitely. Toggling the Phase Detector Polarity state to negative VCO characteristics allows the measurement of the Main charge pump source current. Likewise, selecting TRI-STATE (TRI-STATE IDo Main Bit = 1) for Charge Pump State in Code Loader facilitates the measurement of the TRI-STATE current. The measurements are repeated at different temperatures, namely TA = -40˚C, +25˚C, and +85˚C. 26 LMX2377U Test Setups (Continued) LMX2377U fIN Sensitivity Test Setup 20022640 Output word (FoLD Word = 6 or 14) in Code Loader. A Universal Counter is connected to the FoLD pin and tied to the 10 MHz reference output of the signal generator. The output of the feedback divider is thus monitored and should be equal to fIN Main/ N. The fIN Main input frequency and power level are then swept with the signal generator. The measurements are repeated at different temperatures, namely TA = -40˚C, +25˚C, and +85˚C. Sensitivity is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz. The power attenuation from the cable and the 3 dB pad must be accounted for. The feedback divider will actually miscount if too much or too little power is applied to the fIN Main input. Therefore, the allowed input power level will be bounded by the upper and lower sensitivity limits. In a typical application, if the power level to the fIN Main input approaches the sensitivity limits, this can introduce spurs and degradation in phase noise. When the power level gets even closer to these limits, or exceeds it, then the Main PLL loses lock. The block diagram above illustrates the setup required to measure the LMX2377U device’s Main input sensitivity level. The same setup is used for the LMX2370TMEB/ LMX2370SLEEB Evaluation Boards. The Aux input sensitivity test setup is similar to the Main input sensitivity test setup. The purpose of this test is to measure the acceptable signal level to the fIN Main input of the PLL chip. Outside the acceptable signal range, the feedback divider begins to divide incorrectly and miscount the frequency. The setup uses an open loop configuration. A power supply is connected to Vcc and the bias voltage is swept from 2.7V to 5.5V. The MICROWIRE power supply, Vµc, is tied to Vcc. The Aux PLL is powered down (PWDN Aux Bit = 1). By means of a signal generator, an RF signal is applied to the fIN Main pin. The 3 dB pad provides a 50 Ω match between the PLL and the signal generator. The OSCin pin is tied to Vcc. The N value is typically set to 10000 in Code Loader, i.e. Main N_CNTRB Word = 312 and Main N_CNTRA Word = 16 for PRE Main Bit = 1. The feedback divider output is routed to the FoLD pin by selecting the Main PLL N Divider 27 www.national.com LMX2377U Test Setups (Continued) LMX2377U OSCin Sensitivity Test Setup 20022641 The block diagram above illustrates the setup required to measure the LMX2377U device’s OSCin buffer sensitivity level. The same setup is used for the LMX2370TMEB/ LMX2370SLEEB Evaluation Boards. This setup is similar to the fIN sensitivity setup except that the signal generator is now connected to the OSCin pin and both fIN pins are tied to VCC. The 51 Ω shunt resistor matches the OSCin input to the signal generator. The R counter is typically set to 1000, i.e. Main R_CNTR Word = 1000 or Aux R_CNTR Word = 1000. The reference divider output is routed to the FoLD pin by selecting the Main PLL R Divider Output word (FoLD Word = 2 or 10) or the Aux PLL R Divider Output word (FoLD Word = 1 or 9) in Code Loader. Similarly, a Universal www.national.com Counter is connected to the FoLD pin and is tied to the 10 MHz reference output from the signal generator. The output of the reference divider is monitored and should be equal to OSCin/ Main R_CNTR or OSCin/ Aux R_CNTR. Again, VCC is swept from 2.7V to 5.5V. The MICROWIRE power supply, Vµc, is tied to Vcc. The OSCin input frequency and voltage level are then swept with the signal generator. The measurements are repeated at different temperatures, namely TA = -40˚C, +25˚C, and +85˚C. Sensitivity is reached when the frequency error of the divided input signal is greater than or equal to 1 Hz. 28 LMX2377U Test Setups (Continued) LMX2377U fIN Impedance Test Setup 20022679 The block diagram above illustrates the setup required to measure the LMX2377U device’s Main input impedance. The Aux input impedance and reference oscillator impedance setups are very much similar. The same setup is used for the LMX2370TMEB/ LMX2370SLEEB Evaluation Boards. Measuring the device’s input impedance facilitates the design of appropriate matching networks to match the PLL to the VCO, or in more critical situations, to the characteristic impedance of the printed circuit board (PCB) trace, to prevent undesired transmission line effects. Before the actual measurements are taken, the Network Analyzer needs to be calibrated, i.e. the error coefficients need to be calculated. Therefore, three standards will be used to calculate these coefficients: an open, short and a matched load. A 1-port calibration is implemented here. To calculate the coefficients, the PLL chip is first removed from the PCB. The Network Analyzer port is then connected to the RF1 OUT connector of the evaluation board and the desired operating frequency is set. The typical frequency range selected for the LMX2377U device’s Main synthesizer is from 100 MHz to 2500 MHz. The standards will be located down the length of the RF1 OUT transmission line. The transmission line adds electrical length and acts as an offset from the reference plane of the Network Analyzer; therefore, it must be included in the calibration. Although not shown, 0 Ω resistors are used to complete the RF1 OUT transmission line (trace). To implement an open standard, the end of the RF1 OUT trace is simply left open. To implement a short standard, a 0 Ω resistor is placed at the end of the RF1 OUT transmission line. Last of all, to implement a matched load standard, two 100 Ω resistors in parallel are placed at the end of the RF1 OUT transmission line. The Network Analyzer calculates the calibration coefficients based on the measured S11 parameters. With this all done, calibration is now complete. The PLL chip is then placed on the PCB. A power supply is connected to VCC and swept from 2.7V to 5.5V. The MICROWIRE power supply, Vµc, is tied to Vcc. The OSCin pin is tied to the ground plane. Alternatively, the OSCin pin can be tied to VCC. In this setup, the complementary input (fIN Main) is AC coupled to ground. With the Network Analyzer still connected to RF1 OUT, the measured fIN Main impedance is displayed. Note: The impedance of the reference oscillator is measured when the oscillator buffer is powered up (PWDN Main Bit = 0 or PWDN Aux Bit = 0), and when the oscillator buffer is powered down (PWDN Main Bit = 1 and PWDN Aux Bit = 1). 29 www.national.com LMX2377U Test Setups (Continued) LMX2377U Serial Data Input Timing 20022610 Notes: 1. Data is clocked into the 22-bit shift register on the rising edge of Clock 2. The MSB of Data is shifted in first. www.national.com 30 flip-flops in a dual modulus configuration. The output of the prescaler is used to clock the subsequent feedback dividers. The Main PLL complementary inputs can be driven differentially, or the negative input can be AC coupled to ground through an external capacitor for single ended configuration. A 16/17 or a 32/33 prescale ratio can be selected for the LMX2377U Main synthesizer. On the other hand, the Aux PLL is only intended for single ended operation. An 8/9 or a 16/17 prescale ratio can be selected for the LMX2377U Aux synthesizer. The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer such as the National Semiconductor LMX2377U, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, programmable reference R and feedback N frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the reference divider to obtain a comparison reference frequency. This reference signal, Fr, is then presented to the input of a phase/frequency detector and compared with the feedback signal, Fp, which was obtained by dividing the VCO frequency down by way of the feedback divider. The phase/frequency detector measures the phase error between the Fr and Fp signals and outputs control signals that are directly proportional to the phase error. The charge pump then pumps charge into or out of the loop filter based on the magnitude and direction of the phase error. The loop filter converts the charge into a stable control voltage for the VCO. The phase/frequency detector’s function is to adjust the voltage presented to the VCO until the feedback signal’s frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency will be N times that of the comparison frequency, where N is the feedback divider ratio. 1.4 PROGRAMMABLE FEEDBACK DIVIDERS (N COUNTERS) The programmable feedback dividers operate in concert with the prescalers to divide the input signal fIN by a factor of N. The output of the programmable reference divider is provided to the feedback input of the phase detector circuit. The divide ratio should be chosen such that the maximum phase comparison frequency (FφMain or FφAux) of 10 MHz is not exceeded. The programmable feedback divider circuit is comprised of an A counter (swallow counter) and a B counter (programmble binary counter). The Main N_CNTRA and the Aux N_CNTRA counters are both 5-bit CMOS swallow counters, programmable from 0 to 31. The Main N_CNTRB and Aux N_CNTRB counters are both 13-bit CMOS binary counters, programmable from 3 to 8191. A continuous integer divide ratio is achieved if N ≥ P * (P−1), where P is the value of the prescaler selected. Divide ratios less than the minimum continuous divide ratio are achievable as long as the binary programmable counter value is greater than the swallow counter value (N_CNTRB ≥ N_CNTRA). Refer to Sections 2.5.1, 2.5.2, 2.7.1 and 2.7.2 for details on how to program the N_CNTRA and N_CNTRB counters. The following equations are useful in determining and programming a particular value of N: N = (P x N_CNTRB) + N_CNTRA fIN = N x Fφ Definitions: Fφ: Main or Aux phase detector comparison frequency Main or Aux input frequency fIN: N_CNTRA: Main or Aux A counter value N_CNTRB: Main or Aux B counter value P: Preset modulus of the dual moduIus prescaler Main synthesizer: P = 16 or 32 Aux synthesizer: P = 8 or 16 1.1 REFERENCE OSCILLATOR INPUT The reference oscillator frequency for both the Main and Aux PLLs is provided from an external reference via the OSCin pin. The reference buffer circuit supports input frequencies from 2 to 40 MHz with a minimum input sensitivity of 0.5 VPP. The reference buffer circuit has an approximate VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. Typically, the OSCin pin is connected to the output of a crystal oscillator. 1.2 REFERENCE DIVIDERS (R COUNTERS) The reference dividers divide the reference input signal, OSCin, by a factor of R. The output of the reference divider circuits feeds the reference input of the phase detector. This reference input to the phase detector is often referred to as the comparison frequency. The divide ratio should be chosen such that the maximum phase comparison frequency (FφMain or FφAux) of 10 MHz is not exceeded. The Main and Aux reference dividers are each comprised of 15-bit CMOS binary counters that support a continuous integer divide ratio from 2 to 32767. The Main and Aux reference divider circuits are clocked by the output of the reference buffer circuit which is common to both. 1.3 PRESCALERS The fIN Main and fIN Main input pins drive the input of a bipolar, differential-pair amplifier. The output of the bipolar, differential-pair amplifier drives a chain of ECL D-type 31 www.national.com LMX2377U 1.0 Functional Description LMX2377U 1.0 Functional Description (Continued) 1.5 PHASE/FREQUENCY DETECTORS The Main and Aux phase/frequency detectors are driven from their respective N and R counter outputs. The maximum frequency for both the Main and Aux phase detector inputs is 10 MHz. The phase/frequency detector outputs control the respective charge pumps. The polarity of the pump-up or pump-down control signals are programmed using the PD_POL Main or PD_POL Aux control bits, de- pending on whether the Main or Aux VCO characteristics are positive or negative. Refer to Sections 2.4.2 and 2.6.2 for more details. The phase/frequency detectors have a detection range of −2π to +2π. The phase/frequency detectors also receive a feedback signal from the charge pump in order to eliminate dead zone. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS 20022611 Notes: 1. 2. The minimum width of the pump-up and pump-down current pulses occur at the Do Main or Do Aux pins when the loop is phase locked. The diagram assumes positive VCO characteristics, i.e. PD_POL Main or PD_POL Aux = 1. 3. Fr is the phase detector input from the reference divider (R counter). 4. Fp is the phase detector input from the programmable feedback divder (N counter). 5. Do refers to either the Main or Aux charge pump output. 1.6 CHARGE PUMPS The charge pump directs charge into or out of an external loop filter. The loop filter converts the charge into a stable control voltage which is applied to the tuning input of the VCO. The charge pump steers the VCO control voltage towards VP Main or VP Aux during pump-up events and towards GND during pump-down events. When locked, Do Main or Do Aux are primarily in a TRI-STATE mode with small corrections occuring at the phase comparator rate. The charge pump output current magnitude can be selected by toggling the IDo Main or IDo Aux control bits. 1.8 MULTI-FUNCTION OUTPUTS The LMX2377U device’s FoLD output pin is a multi-function output that can be configured as the Main synthesizer FastLock output, an open drain analog lock detect output, counter reset, or used to monitor the output of the various reference divider (R counter) or feedback divider (N counter) circuits. The FoLD control word is used to select the desired output function. When the PLL is in powerdown mode, the FoLD output is pulled to a LOW state. A complete programming description of the multi-function output is provided in Section 2.8 FoLD. 1.7 MICROWIRE SERIAL INTERFACE The programmable register set is accessed via the MICROWIRE serial interface. The supply for the MICROWIRE circuitry is separate from the rest of the IC to allow direct connection to 1.8V devices. The interface is comprised of three signal pins: Clock, Data and LE (Latch Enable). Serial data is clocked into the 22-bit shift register on the rising edge of Clock. The last two bits decode the internal control register address. When LE transitions HIGH, data stored in the shift register is loaded into one of four control registers depending on the state of the address bits. The MSB of Data is loaded in first. The synthesizers can be programmed even in power down mode. A complete programming description is provided in Section 2.0 Programming Description. 1.8.1 Open Drain Analog Lock Detect Output An analog lock detect status generated from the phase detector is available on the FoLD output pin if selected. The lock detect output goes to a high impedance state when the charge pump is inactive. It goes low when the charge pump is active during a comparison cycle. When viewed with an oscilloscope, and when a pull-up resistor is used, narrow negative pulses are observed when the charge pump turns on. The lock detect output signal is an open drain configuration. Three separate lock detect signals are routed to the multiplexer. Two of these monitor the ‘lock’ status of the individual synthesizers. The third detects the condition when both the Main and Aux synthesizers are in a ‘locked state’. External circuitry however, is required to provide a steady DC signal to indicate when the PLL is in a locked state. Refer to Section 2.8 FoLD for details on how to program the different lock detect options. www.national.com 32 (Continued) 1.8.2 Open Drain FastLock Output 1.9 POWER CONTROL Each synthesizer in the LMX2377U device is individually power controlled by device powerdown bits. The powerdown word is comprised of the PWDN Main (PWDN Aux) bit, in conjuction with the TRI-STATE IDo Main (TRI-STATE IDo Aux) bit. The powerdown control word is used to set the operating mode of the device. Refer to Sections 2.4.4, 2.5.4, 2.6.4, and 2.7.4 for details on how to program the Main or Aux powerdown bits. When either the Main synthesizer or the Aux synthesizer enters the powerdown mode, the respective prescaler, phase detector, and charge pump circuit are disabled. The Do Main (Do Aux), fIN Main (fIN Aux), and fIN Main pins are all forced to a high impedance state. The reference divider and feedback divider circuits are held at the load point during powerdown. The oscillator buffer is disabled when both the Main and Aux synthesizers are powered down. The OSCin pin is forced to a HIGH state through an approximate 100 kΩ resistance when this condition exists. When either synthesizer is activated, the respective prescaler, phase detector, charge pump circuit, and the oscillator buffer are all powered up. The feedback divider, and the reference divider are held at load point. This allows the reference oscillator, feedback divider, reference divider and prescaler circuitry to reach proper bias levels. After a finite delay, the feedback and reference dividers are enabled and they resume counting in ‘close’ alignment (the maximum error is one prescaler cycle). The MICROWIRE control register remains active and capable of loading and latching data while in the powerdown mode. The LMX233xU Fastlock feature allows faster loop response time during lock aquisition. The loop response time (lock time) can be approximately halved if the loop bandwidth is doubled. In order to achieve this, the same gain/ phase relationship at twice the loop bandwidth must be maintained. This can be achieved by increasing the charge pump current from 0.95 mA (IDo Main Bit = 0) in the steady state mode, to 3.8 mA (IDo Main Bit = 1) in Fastlock. When the FoLD output is configured as a FastLock output, an open drain device is enabled. The open drain device switches in a parallel resistor R2’ to ground, of equal value to resistor R2 of the external loop filter. The loop bandwidth is effectively doubled and stability is maintained. Once locked to the correct frequency, the PLL will return to a steady state condition. Refer to Section 2.8 FoLD for details on how to configure the FoLD output to an open drain Fastlock output. 1.8.3 Counter Reset Three separate counter reset functions are provided. When the FoLD is programmed to Reset Aux PLL Counters, both the Aux feedback divider and the Aux reference divider are held at their load point. When the Reset Main PLL Counters is programmed, both the Main feedback divider and the Main reference divider are held at their load point. When the Reset All Counters mode is enabled, all feedback dividers and reference dividers are held at their load point. When the device is programmed to normal operation, both the feedback divider and reference divider are enabled and resume counting in ‘close’ alignment to each other. Refer to Section 2.8 FoLD for more details. 1.8.4 Reference Divider and Feedback Divider Output The outputs of the various N and R divders can be monitored by selecting the appropriate FoLD word. This is essential when performing OSCin or fIN sensitivity measurements. Refer to the Test Setups section for more details. Refer to Section 2.8 FoLD for details on how to route the appropriate divder output to the FoLD pin. Synchronous Powerdown Mode In this mode, the powerdown function is gated by the charge pump. When the device is configured for synchronous powerdown, the device will enter the powerdown mode upon completion of the next charge pump pulse event. Asynchronous Powerdown Mode In this mode, the powerdown function is NOT gated by the completion of a charge pump pulse event. When the device is configured for asynchronous powerdown, the part will go into powerdown mode immediately. TRI-STATE IDo PWDN 0 0 PLL Active, Normal Operation Operating Mode 1 0 PLL Active, Charge Pump Output in High Impedance State 0 1 Synchronous Powerdown 1 1 Asynchronous Powerdown Notes: 1. TRI-STATE IDo refers to either the TRI-STATE IDo Main or TRI-STATE IDo Aux bit . 2. PWDN refers to either the PWDN Main or PWDN Aux bit. 33 www.national.com LMX2377U 1.0 Functional Description LMX2377U 2.0 Programming Description 2.1 MICROWIRE INTERFACE The 22-bit shift register is loaded via the MICROWIRE interface. The shift register consists of a 20-bit Data[19:0] Field and a 2-bit Address[1:0] Field as shown below. The Address Field is used to decode the internal control register address. When LE transitions HIGH, data stored in the shift register is loaded into one of 4 control registers depending on the state of the address bits. The MSB of Data is loaded in first. The Data field assignments are shown in Section 2.3 CONTROL REGISTER CONTENT MAP. MSB LSB Data[19:0] Address[1:0] 21 2 1 0 2.2 CONTROL REGISTER LOCATION The address bits Address[1:0] decode the internal register address. The table below shows how the address bits are mapped into the target control register. Address[1:0] Target Field Register 0 0 0 1 Aux R Aux N 1 0 Main R 1 1 Main N 2.3 CONTROL REGISTER CONTENT MAP The control register content map describes how the bits within each control register are allocated to specific control functions. www.national.com 34 PWDN Aux Aux N TRISTATE IDo Aux 19 IDo Aux 18 Main PWDN PRE N Main Main IDo Main FoLD1 FoLD3 TRISTATE Main R IDo Main PRE Aux FoLD0 FoLD2 20 Aux R 21 Reg. Most Significant Bit PD_ POL Main PD_ POL Aux 17 2.0 Programming Description 16 15 (Continued) 13 11 Data Field 12 Main N_CNTRB[12:0] 9 8 Main R_CNTR[14:0] Aux R_CNTR[14:0] 10 SHIFT REGISTER BIT LOCATION Aux N_CNTRB[12:0] 14 Control Register Content Map 7 6 4 3 Main N_CNTRA[4:0] Aux N_CNTRA[4:0] 5 2 0 1 1 0 0 1 0 1 0 Address Field 1 Least Significant Bit LMX2377U 35 www.national.com LMX2377U 2.0 Programming Description (Continued) 2.4 AUXILIARY R REGISTER The Aux R register contains the Aux R_CNTR, PD_POL Aux, IDo Aux, and TRI-STATE IDo Aux control words, in addition to two bits that compose the FoLD control word. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit 21 20 19 18 SHIFT REGISTER BIT LOCATION 17 16 15 14 13 12 11 10 9 8 Least Significant Bit 7 6 5 4 3 2 1 Data Field Aux R FoLD0 FoLD2 TRISTATE IDo PD_ Aux POL IDo 0 Address Field Aux R_CNTR[14:0] 0 0 Aux Aux 2.4.1 Aux R_CNTR[14:0] AUXILIARY SYNTHESIZER PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) Aux R[2:16] The Aux reference divider (Aux R_CNTR) can be programmed to support divide ratios from 2 to 32767. Divide ratios less than 2 are prohibited. Divide Ratio Aux R_CNTR[14:0] 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 • • • • • • • • • • • • • • • • 32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2.4.2 PD_POL Aux AUXILIARY SYNTHESIZER PHASE DETECTOR POLARITY Aux R[17] The PD_POL Aux bit is used to control the Aux synthesizer’s phase detector polarity based on the VCO tuning characteristics. Control Bit Register Location Description Function 0 PD_POL Aux Aux R[17] Aux Phase Detector Polarity 1 Aux VCO Negative Tuning Characteristics Aux VCO Positive Tuning Characteristics Aux VCO Characteristics 20022609 2.4.3 IDo Aux AUXILIARY SYNTHESIZER CHARGE PUMP CURRENT GAIN The IDo Aux bit controls the Aux synthesizer’s charge pump gain. Two current levels are available. Control Bit Register Location IDo Aux Aux R[18] www.national.com Description Aux Charge Pump Current Gain 36 Aux R[18] Function 0 1 LOW 0.95 mA HIGH 3.80 mA (Continued) 2.4.4 TRI-STATE IDo Aux AUXILIARY SYNTHESIZER CHARGE PUMP TRI-STATE CURRENT Aux R[19] The TRI-STATE IDo Aux bit allows the charge pump to be switched between a normal operating mode and a high impedance output state. This happens asynchronously with the change in the TRI-STATE IDo Aux bit. Furthermore, the TRI-STATE IDo Aux bit operates in conjuction with the PWDN Aux bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description Function 0 TRI-STATE IDo Aux Aux R[19] Aux Charge Pump TRI-STATE Current 1 Aux Charge Pump Normal Operation Aux Charge Pump Output in High Impedance State 2.5 AUXILIARY N REGISTER The Aux N register contains the Aux N_CNTRA, Aux N_CNTRB, PRE Aux, and PWDN Aux control words. The Aux N_CNTRA and Aux N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit 21 20 19 18 SHIFT REGISTER BIT LOCATION 17 16 15 14 13 12 11 10 9 8 7 Least Significant Bit 6 5 4 3 2 1 Data Field Aux PWDN N Aux PRE 0 Address Field Aux N_CNTRB[12:0] Aux N_CNTRA[4:0] 0 1 Aux 2.5.1 Aux N_CNTRA[4:0] AUXILIARY SYNTHESIZER SWALLOW COUNTER (A COUNTER) Aux N[2:6] The Aux N_CNTRA control word is used to setup the Aux synthesizer’s A counter. The A counter is a 5-bit swallow counter used in the programmable feedback divider. The Aux N_CNTRA control word can be programmed to values ranging from 0 to 31. Divide Ratio Aux N_CNTRA[4:0] 4 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 1 • 31 • 1 • 1 • 1 • 1 1 2.5.2 Aux N_CNTRB[12:0] Aux N[7:19] • AUXILIARY SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER) The Aux N_CNTRB control word is used to setup the Aux synthesizer’s B counter. The B counter is a 13-bit programmable binary counter used in the programmable feedback divider. The Aux N_CNTRB control word can be programmed to values ranging from 3 to 8191. Divide Ratio 12 11 10 9 8 7 Aux N_CNTRB[12:0] 6 5 4 3 2 1 0 3 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 1 0 0 • 8191 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 37 www.national.com LMX2377U 2.0 Programming Description LMX2377U 2.0 Programming Description 2.5.3 PRE Aux (Continued) AUXILIARY SYNTHESIZER PRESCALER SELECT Aux N[20] The Aux synthesizer utilizes a selectable dual modulus prescaler. Control Bit Register Location Description Function 0 PRE Aux Aux N[20] 2.5.4 PWDN Aux Aux Prescaler Select 1 8/9 Prescaler Selected 16/17 Prescaler Selected AUXILIARY SYNTHESIZER POWERDOWN Aux N[21] The PWDN Aux bit is used to switch the Aux PLL between a powered up and powered down mode. Furthermore, the PWDN Aux bit operates in conjuction with the TRI-STATE IDo Aux bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description Function 0 PWDN Aux Aux N[21] Aux Powerdown 1 Aux PLL Active Aux PLL Powerdown 2.6 MAIN R REGISTER The Main R register contains the Main R_CNTR, PD_POL Main, IDo Main, and TRI-STATE IDo Main control words, in addition to two bits that compose the FoLD control word. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit 21 20 19 18 SHIFT REGISTER BIT LOCATION 17 16 15 14 13 12 11 10 9 8 Least Significant Bit 7 6 5 4 3 2 1 Data Field Main FoLD1 FoLD3 TRIR STATE IDo PD_ Main POL IDo 0 Address Field Main R_CNTR[14:0] 1 0 Main Main 2.6.1 Main R_CNTR[14:0] MAIN SYNTHESIZER PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) Main R[2:16] The Main reference divider (Main R_CNTR) can be programmed to support divide ratios from 2 to 32767. Divide ratios less than 2 are prohibited. Divide Ratio Main R_CNTR[14:0] 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 • • • • • • • • • • • • • • • • 32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 www.national.com 38 2.6.2 PD_POL Main (Continued) MAIN SYNTHESIZER PHASE DETECTOR POLARITY Main R[17] The PD_POL Main bit is used to control the Main synthesizer’s phase detector polarity based on the VCO tuning characteristics. Control Bit Register Location Description Function 0 PD_POL Main Main R[17] Main Phase Detector Polarity 1 Main VCO Negative Tuning Characteristics Main VCO Positive Tuning Characteristics Main VCO Characteristics 20022682 2.6.3 IDo Main MAIN SYNTHESIZER CHARGE PUMP CURRENT GAIN The IDo Main bit controls the Main synthesizer’s charge pump gain. Two current levels are available. Control Bit IDo Main Register Location Main R[18] Description Main Charge Pump Current Gain Main R[18] Function 0 1 LOW 0.95 mA HIGH 3.80 mA 2.6.4 TRI-STATE IDo Main MAIN SYNTHESIZER CHARGE PUMP TRI-STATE CURRENT Main R[19] The TRI-STATE IDo Main bit allows the charge pump to be switched between a normal operating mode and a high impedance output state. This happens asynchronously with the change in the TRI-STATE IDo Main bit. Furthermore, the TRI-STATE IDo Main bit operates in conjuction with the PWDN Main bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description Function 0 TRI-STATE IDo Main Main R[19] Main Charge Pump TRI-STATE Current 39 Main Charge Pump Normal Operation 1 Main Charge Pump Output in High Impedance State www.national.com LMX2377U 2.0 Programming Description LMX2377U 2.0 Programming Description (Continued) 2.7 MAIN N REGISTER The Main N register contains the Main N_CNTRA, Main N_CNTRB, PRE Main, and PWDN Main control words. The Main N_CNTRA and Main N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit 21 20 19 18 SHIFT REGISTER BIT LOCATION 17 16 15 14 13 12 11 10 9 8 Least Significant Bit 7 6 5 4 3 2 1 Data Field Main PWDN N Main PRE 0 Address Field Main N_CNTRB[12:0] Main N_CNTRA[4:0] 1 1 Main 2.7.1 Main N_CNTRA[4:0] MAIN SYNTHESIZER SWALLOW COUNTER (A COUNTER) Main N[2:6] The Main N_CNTRA control word is used to setup the Main synthesizer’s A counter. The A counter is a 5-bit swallow counter used in the programmable feedback divider. The Main N_CNTRA control word can be programmed to values ranging from 0 to 31. Divide Ratio Main N_CNTRA[4:0] 4 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 1 • 31 • 1 • 1 • 1 • 1 • 1 2.7.2 Main N_CNTRB[12:0] Main N[7:19] MAIN SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER) The Main N_CNTRB control word is used to setup the Main synthesizer’s B counter. The B counter is a 13-bit programmable binary counter used in the programmable feedback divider. The Main N_CNTRB control word can be programmed to values ranging from 3 to 8191. Divide Ratio Main N_CNTRB[12:0] 12 11 10 9 8 7 6 5 4 3 2 1 0 3 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 1 0 0 • 8191 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 2.7.3 PRE Main MAIN SYNTHESIZER PRESCALER SELECT The Main synthesizer utilizes a selectable dual modulus prescaler. Control Bit Register Location Main N[20] Description Function 0 PRE Main Main N[20] Main Prescaler Select 16/17 Prescaler Selected 1 32/33 Prescaler Selected 2.7.4 PWDN Main MAIN SYNTHESIZER POWERDOWN Main N[21] The PWDN Main bit is used to switch the Main PLL between a powered up and powered down mode. Furthermore, the PWDN Main bit operates in conjuction with the TRI-STATE IDo Main bit to set a synchronous or an asynchronous powerdown mode. Control Bit Register Location Description Function 0 PWDN Main www.national.com Main N[21] Main Powerdown 40 Main PLL Active 1 Main PLL Powerdown (Continued) 2.8 FoLD[3:0] MULTI-FUNCTION OUTPUT SELECT [Main R[20], Aux R[20], Main R [21], Aux R[21]] The FoLD control word is used to select which signal is routed to the FoLD pin. FoLD3 FoLD2 FoLD1 FoLD0 0 0 0 0 LOW Logic State Output FoLD Output State 0 0 0 1 Aux PLL R Divider Output, Push-Pull Output 0 0 1 0 Main PLL R Divider Output, Push-Pull Output 0 0 1 1 Open Drain Fastlock Output 0 1 0 0 Aux PLL Analog Lock Detect, Open Drain Output 0 1 0 1 Aux PLL N Divider Output, Push-Pull Output 0 1 1 0 Main PLL N Divider Output, Push-Pull Output 0 1 1 1 Reset Aux PLL Counters, LOW Logic State Output 1 0 0 0 Main PLL Analog Lock Detect, Open Drain Output 1 0 0 1 Aux PLL R Divider Output, Push-Pull Output 1 0 1 0 Main PLL R Divider Output, Push-Pull Output 1 0 1 1 Reset Main PLL Counters, LOW Logic State Output 1 1 0 0 Main and Aux Analog Lock Detect, Open Drain Output 1 1 0 1 Aux PLL N Divider Output, Push-Pull Output 1 1 1 0 Main PLL N Divider Output, Push-Pull Output 1 1 1 1 Reset All Counters, LOW Logic State Output 41 www.national.com LMX2377U 2.0 Programming Description LMX2377U Physical Dimensions inches (millimeters) unless otherwise noted 20-Pin Thin Shrink Small Outline Package (TM) NS Package Number MTC20 www.national.com 42 LMX2377U Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Pin Chip Scale Package (SLB) NS Package Number SLB24A 43 www.national.com LMX2377U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Pin Ultra Thin Chip Scale Package (SLE) NS Package Number SLE20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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