NSC ADC1242

ADC1242
12-Bit Plus Sign Sampling A/D Converter
General Description
Key Specifications
The ADC1242 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter. On request, the
ADC1242 goes through a self-calibration cycle that adjusts
positive linearity error to less than g 1 LSB full-scale error to
less than g 3 LSB, and zero error to less than g 2 LSB. The
ADC1242 also has the ability to go through an Auto-Zero
cycle that corrects the zero error during every conversion.
The analog input to the ADC1242 is tracked and held by the
internal circuitry, and therefore does not require an external
sample-and-hold. A unipolar analog input voltage range (0V
to a 5V) or a bipolar range ( b5V to a 5V) can be accommodated with g 5V supplies.
The 13-bit word on the outputs of the ADC1242 gives a 2’s
complement representation of negative numbers. The digital inputs and outputs are compatible with TTL or CMOS
logic levels.
Y
Y
Y
Y
Y
Y
Resolution
Conversion Time
Linearity Error
Zero Error
Positive Full Scale Error
Power Consumption
12 Bits plus Sign
13.8 ms (max)
g 1 LSB ( g 0.0244%) (max)
g 2 LSB (max)
g 3 LSB (max)
70 mW (max)
Features
Y
Y
Y
Y
Y
Y
Self-calibrating
Internal sample-and-hold
Bipolar input range with g 5V supplies and single
a 5V reference
No missing codes over temperature
TTL/MOS input/output compatible
Standard 28-pin ceramic DIP
Applications
Y
Y
Y
Digital Signal Processing
High Resolution Process Control
Instrumentation
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
Simplified Schematic
Connection Diagram
Dual-In-Line Package
TL/H/11735 – 2
Top View
Order Number ADC1242CIJ
See NS Package Number J28A
TL/H/11735 – 1
C1995 National Semiconductor Corporation
TL/H/11735
RRD-B30M115/Printed in U. S. A.
ADC1242 12-Bit Plus Sign Sampling A/D Converter
February 1995
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC e DVCC e AVCC)
6.5V
b 6.5V
Negative Supply Voltage (Vb)
b 0.3V to (VCC a 0.3V)
Voltage at Logic Control Inputs
Voltage at Analog Input (VIN) (Vb b0.3V) to (VCC a 0.3V)
AVCC-DVCC (Note 7)
0.3V
g 5 mA
Input Current at any Pin (Note 3)
g 20 mA
Package Input Current (Note 3)
875 mW
Power Dissipation at 25§ C (Note 4)
b 65§ C to a 150§ C
Storage Temperature Range
ESD Susceptability (Note 5)
2000V
Soldering Information
J Package (10 seconds)
300§ C
Operating Ratings (Notes 1 and 2)
Temperature Range
ADC1242CIJ
DVCC and AVCC Voltage
(Notes 6 and 7)
Negative Supply Voltage (Vb)
Reference Voltage
(VREF, Notes 6 and 7)
TMINsTAsTMAX
b 40§ C s TA s a 85§ C
4.5V to 5.5V
b 4.5V to b 5.5V
3.5V to AVCC a 50 mV
Converter Electrical Characteristics
The following specifications apply for VCC e DVCC e AVCC e a 5.0V, Vb e b5.0V, VREF e a 4.096V, and fCLK e 2.0 MHz
unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. (Notes
6, 7 and 8)
Symbol
Parameter
Conditions
Typical
Limit
(Note 9) (Notes 10, 18)
Units
(Limit)
STATIC CHARACTERISTICS
Positive Integral
Linearity Error
After Auto-Cal
(Notes 11 and 12)
g1
LSB(max)
Differential Linearity
After Auto-Cal (Notes 11 and 12)
12
Bits(min)
Zero Error
After Auto-Zero or Auto-Cal
(Notes 12 and 13)
g2
LSB(max)
Positive and Negative Full-Scale Error
After Auto-Cal (Note 12)
g3
LSB(max)
CREF
VREF Input Capacitance
80
CIN
Analog Input Capacitance
65
VIN
Analog Input Voltage
Power Supply
Sensitivity
pF
pF
Vb b
0.05
VCC a 0.05
Zero Error (Note 14) AVCC e DVCC e 5V g 5%,
e 4.75V, V b e b 5V g 5%
V
Full-Scale Error REF
Linearity Error
V(min)
V(max)
g (/8
LSB
g (/8
LSB
g (/8
LSB
DYNAMIC CHARACTERISTICS
S/(N a D) Unipolar Signal-to-Noise a Distortion
Ratio (Note 17)
fIN e 1 kHz, VIN e 4.85 Vp-p
72
dB
fIN e 10 kHz, VIN e 4.85 Vp-p
72
dB
fIN e 1 kHz, VIN e g 4.85 Vp-p
76
dB
fIN e 10 kHz, VIN e g 4.85 Vp-p
76
dB
Unipolar Full Power Bandwidth (Note 17)
VIN e 0V to 4.85V
32
kHz
Bipolar Full Power Bandwidth (Note 17)
VIN e g 4.85 Vp-p
25
kHz
S/(N a D) Bipolar Signal-to-Noise a Distortion
Ratio (Note 17)
tAp
Aperture Time
100
ns
Aperture Jitter
100
psrms
2
Digital and DC Electrical Characteristics
The following specifications apply for VCC e DVCC e AVCC e a 5.0V, Vb e b5.0V, VREF e a 4.096V, and fCLK e 2.0 MHz
unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C.
(Notes 6 and 7)
Symbol
Parameter
Condition
Typical
(Note 9)
Limit
(Notes 10, 18)
Units
(Limits)
VIN(1)
Logical ‘‘1’’ Input Voltage for
All Inputs except CLK IN
VCC e 5.25V
2.0
V(min)
VIN(0)
Logical ‘‘0’’ Input Voltage for
All Inputs except CLK IN
VCC e 4.75V
0.8
V(max)
IIN(1)
Logical ‘‘1’’ Input Current
VIN e 5V
0.005
1
mA(max)
IIN(0)
Logical ‘‘0’’ Input Current
VIN e 0V
b 0.005
b1
mA(max)
VT a
CLK IN Positive-Going
Threshold Voltage
2.8
2.7
V(min)
VTb
CLK IN Negative-Going
Threshold Voltage
2.1
2.3
V(max)
VH
CLK IN Hysteresis
[VT a (min) b VTb(max)]
0.7
0.4
V(min)
VOUT(1)
Logical ‘‘1’’ Output Voltage
2.4
4.5
V(min)
V(min)
VCC e 4.75V:
IOUT e b360 mA
IOUT e b10 mA
VOUT(0)
Logical ‘‘0’’ Output Voltage
VCC e 4.75V
IOUT e 1.6 mA
IOUT
TRI-STATEÉ Output Leakage
Current
VOUT e 0V
b 0.01
b3
mA(max)
VOUT e 5V
0.01
3
mA(max)
mA(min)
0.4
V(max)
ISOURCE
Output Source Current
VOUT e 0V
b 20
b 6.0
ISINK
Output Sink Current
VOUT e 5V
20
8.0
mA(min)
DICC
DVCC Supply Current
fCLK e 2 MHz, CS e ‘‘1’’
1
2
mA(max)
AICC
AVCC Supply Current
fCLK e 2 MHz, CS e ‘‘1’’
2.8
6
mA(max)
Ib
Vb Supply Current
fCLK e 2 MHz, CS e ‘‘1’’
2.8
6
mA(max)
3
AC Electrical Characteristics
The following specifications apply for DVCC e AVCC e a 5.0V, Vb e b5.0V, tr e tf e 20 ns unless otherwise specified.
Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits TA e TJ e 25§ C. (Notes 6 and 7)
Symbol
fCLK
Parameter
Conditions
Typical
(Note 9)
Limit
(Notes 10, 18)
Units
(Limits)
2.0
MHz
MHz(min)
MHz(max)
Clock Frequency
0.5
4.0
Clock Duty Cycle
tC
50
Conversion Time
Acquisition Time
(Note 15)
tZ
Auto Zero Time
RSOURCE e 50X
fCLK e 2.0 MHz
fCLK e 2.0 MHz
tCAL
Calibration Time
tW(CAL)L
Calibration Pulse Width
tW(WR)L
Minimum WR Pulse Width
tACC
Maximum Access Time
(Delay from Falling Edge of
RD to Output Data Valid)
CL e 100 pF
TRI-STATE Control (Delay
from Rising Edge of RD
to Hi-Z State)
RL e 1 kX,
CL e 100 pF
t0H, t1H
tPD(INT)
%
%(min)
%(max)
27(1/fCLK) a 300 ns
(max)
7(1/fCLK)
3.5
7(1/fCLK) a 300 ns
(max)
ms
26
26
1/fCLK(max)
27(1/fCLK)
fCLK e 2.0 MHz
tA
40
60
13.5
ms
13
ms
1396
1/fCLK
fCLK e 2.0 MHz
698
706
ms(max)
(Note 16)
60
200
ns(min)
60
200
ns(min)
50
85
ns(max)
30
90
ns(max)
100
175
ns(max)
Maximum Delay from Falling Edge of
RD or WR to Reset of INT
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN k Vb or VIN l (AVCC or DVCC), the current at that pin should be limited to
5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power
supply voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX (maximum junction temperature), iJA (package
junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax e (TJmax b
TA)/iJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax e 125§ C, and the typical thermal resistance (iJA) of the
ADC1242 CIJ when board mounted is 47§ C/W.
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 6: Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than
50 mV.
TL/H/11735 – 3
This means that if AVCC and DVCC are minimum (4.75 VDC) and V
b
is maximum ( b 4.75 VDC), full-scale must be s 4.8 VDC.
4
AC Electrical Characteristics
(Continued)
Note 7: A diode exists between AVCC and DVCC as shown below.
TL/H/11735 – 4
To guarantee accuracy, it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin.
Note 8: Accuracy is guaranteed at fCLK e 2.0 MHz. At higher and lower clock frequencies accuracy may degrade. See curves in the Typical Performance
Characteristics Section.
Note 9: Typicals are at TJ e 25§ C and represent most likely parametric norm.
Note 10: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11: Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and
zero. For negative linearity error the straight line passes through negative full scale and zero. (See Figures 1b and 1c ).
Note 12: The ADC1242’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will
result in a repeatability uncertainty of g 0.20 LSB.
Note 13: If TA changes then an Auto-Zero or Auto-Cal cycle will have to be re-started, see the typical performance characteristic curves.
Note 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Note 15: If the clock is asynchronous to the falling edge of WR an uncertainty of one clock period will exist in the interval of tA, therefore making the minimum tA e
6 clock periods and the maximum tA e 7 clock periods. If the falling edge of the clock is synchronous to the rising edge of WR then tA will be exactly 6.5 clock
periods.
Note 16: The CAL line must be high before any other conversion is started.
Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed.
Note 18: A military RETS electrical test specification is available upon request. At time of printing, the ADC1241CMJ/883 RETS specification complies fully with the
boldface limits in this column.
TL/H/11735 – 5
FIGURE 1a. Transfer Characteristic
5
AC Electrical Characteristics (Continued)
TL/H/11735 – 6
FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Cal or Auto-Zero Cycles
TL/H/11735 – 7
FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Cal Cycle
Typical Performance Characteristics
Zero Error Change vs
Ambient Temperature
Zero Error vs VREF
TL/H/11735 – 8
6
Typical Performance Characteristics
(Continued)
Linearity Error vs VREF
Linearity Error vs Clock
Frequency
Full Scale Error Change vs
Ambient Temperature
Bipolar Signal-toNoise a Distortion Ratio vs
Input Frequency
Unipolar Signal-toNoise a Distortion Ratio vs
Input Frequency
Bipolar Signal-toNoise a Distortion Ratio vs
Input Source Impedance
Bipolar Signal-toNoise a Distortion Ratio vs
Input Signal Level
Unipolar Signal-toNoise a Distortion Ratio vs
Input Signal Level
Bipolar Spectral Response
with 10 kHz Sine Wave Input
Bipolar Spectral Response
with 1 kHz Sine Wave Input
Unipolar Spectral Response
with 1 kHz Sine Wave Input
Unipolar Spectral Response
with 10 kHz Sine Wave Input
TL/H/11735 – 9
7
Test Circuits
TL/H/11735 – 11
TL/H/11735–10
TL/H/11735 – 13
TL/H/11735–12
FIGURE 2. TRI-STATE Test Circuits and Waveforms
Timing Diagrams
Auto-Cal Cycle (CS e 1, WR e X, RD e X, AZ e X, X e Don’t Care)
TL/H/11735 – 14
8
Timing Diagrams (Continued)
Normal Conversion with Auto-Zero (CAL e 1, AZ e 0)
TL/H/11735 – 15
Normal Conversion without Auto-Zero (CAL e 1, AZ e 1)
TL/H/11735 – 16
9
1.0 Pin Descriptions
DVCC (28),
AVCC (4)
V
b
(5)
DGND (14),
AGND (3)
VREF (2)
The reference input voltage pin. To maintain
accuracy the voltage at this pin should not
exceed the AVCC or DVCC by more than
50 mV or go below 3.5 VDC.
VIN (1)
The analog input voltage pin. To guarantee
accuracy the voltage at this pin should not
exceed VCC by more than 50 mV or go below
Vb by more than 50 mV.
The Chip Select control input. This input is
active low and enables the WR and RD functions.
CS (10)
RD (11)
WR (7)
CLK (8)
The Auto-Calibration control input. When
CAL is low the ADC1242 is reset and a calibration cycle is initiated. During the calibration cycle the values of the comparator offset
voltage and the mismatch errors in the capacitor reference ladder are determined and
stored in RAM. These values are used to correct the errors during a normal cycle of A/D
conversion.
AZ (6)
The Auto-Zero control input. With the AZ pin
held low during a conversion, the ADC1242
goes into an auto-zero cycle before the actual A/D conversion is started. This Auto-Zero
cycle corrects for the comparator offset voltage. The total conversion time (tC) is increased by 26 clock periods when Auto-Zero
is used.
The End-of-Conversion control output. This
output is low during a conversion or a calibration cycle.
INT (13)
The TRI-STATE output pins. The output is in
two’s complement format with DB12 the sign
bit, DB11 the MSB and DB0 the LSB.
2.0 Functional Description
The ADC1242 is a 12-bit plus sign A/D converter with the
capability of doing Auto-Zero or Auto-Cal routines to minimize zero, full-scale and linearity errors. It is a successiveapproximation A/D converter consisting of a DAC, comparator and a successive-approximation register (SAR). AutoZero is an internal calibration sequence that corrects for the
A/D’s zero error caused by the comparator’s offset voltage.
Auto-Cal is a calibration cycle that not only corrects zero
error but also corrects for full-scale and linearity errors
caused by DAC inaccuracies. Auto-Cal minimizes the errors
of the ADC1242 without the need of trimming during its fabrication. An Auto-Cal cycle can restore the accuracy of the
ADC1242 at any time, which ensures its long term stability.
2.1 DIGITAL INTERFACE
On power up, a calibration sequence should be initiated by
pulsing CAL low with CS, RD, and WR high. To acknowledge the CAL signal, EOC goes low after the falling edge of
CAL, and remains low during the calibration cycle of 1396
clock periods. During the calibration sequence, first the
comparator’s offset is determined, then the capacitive
DAC’s mismatch error is found. Correction factors for these
errors are then stored in internal RAM.
A conversion is initiated by taking CS and WR low. The AZ
(Auto Zero) signal line should be tied high or low during the
conversion process. If AZ is low an auto zero cycle, which
takes approximately 26 clock periods, occurs before the actual conversion is started. The auto zero cycle determines
the correction factors for the comparator’s offset voltage. If
AZ is high, the auto zero cycle is skipped. Next the analog
input is sampled for 7 clock periods, and held in the capacitive DAC’s ladder structure. The EOC then goes low, signaling that the analog input is no longer being sampled and
that the A/D successive approximation conversion has
started.
During a conversion, the sampled input voltage is successively compared to the output of the DAC. First, the acquired input voltage is compared to analog ground to determine its polarity. The sign bit is set low for positive input
voltages and high for negative. Next the MSB of the DAC is
set high with the rest of the bits low. If the input voltage is
greater than the output of the DAC, then the MSB is left
high; otherwise it is set low. The next bit is set high, making
the output of the DAC three quarters or one quarter of full
scale. A comparison is done and if the input is greater than
the new DAC value this bit remains high; if the input is less
than the new DAC value the bit is set low. This process
continues until each bit has been tested. The result is then
stored in the output latch of the ADC1242. Next EOC goes
high, and INT goes low to signal the end of the conversion.
The result can now be read by taking CS and RD low to
enable the DB0 – DB12 output buffers.
The Read control input. With both CS and RD
low the TRI-STATE output buffers are enabled and the INT output is reset high.
The Write control input. The converison is
started on the rising edge of the WR pulse
when CS is low.
The external clock input pin. The clock frequency range is 500 kHz to 4 MHz.
CAL (9)
EOC (12)
DB0 – DB12
(15 – 27)
The digital and analog positive power supply
pins. The digital and analog power supply
voltage range of the ADC1242 is a 4.5V to
a 5.5V. To guarantee accuracy, it is required
that the AVCC and DVCC be connected together to the same power supply with separate bypass filters (10 mF tantalum in parallel
with a 0.1 mF ceramic) at each VCC pin.
The analog negative supply voltage pin. Vb
has a range of b4.5V to b5.5V and needs a
bypass filter of 10 mF tantalum in parallel with
a 0.1 mF ceramic.
The digital and analog ground pins. AGND
and DGND must be connected together externally to guarantee accuracy.
The Interrupt control output. This output goes
low when a conversion has been completed
and indicates that the conversion result is
available in the output latches. Reading the
result or starting a conversion or calibration
cycle will reset this output high.
10
2.0 Functional Description (Continued)
Digital Control Inputs
A/D Function
CS
WR
RD
CAL
AZ
ß
ß
ß
ß
1
0
ß
1
ß
1
X
X
1
ß
1
ß
X
1
1
1
1
1
ß
0
1
1
0
0
X
X
Start Conversion without Auto-Zero
Read Conversion Result without Auto-Zero
Start Conversion with Auto-Zero
Read Conversion Result with Auto-Zero
Start Calibration Cycle
Test Mode (DB2, DB3, DB5 and DB6 become active)
FIGURE 3. Function of the A/D Control Inputs
The table in Figure 3 summarizes the effect of the digital
control inputs on the function of the ADC1242. The Test
Mode, where RD is high and CS and CAL are low, is used by
the factory to thoroughly check out the operation of the
ADC1242. Care should be taken not to inadvertently be in
this mode, since DB2, DB3, DB5, and DB6 become active
outputs, which may cause data bus contention.
3.0 Analog Considerations
3.1 REFERENCE VOLTAGE
The voltage applied to the reference input of the converter
defines the voltage span of the analog input (the difference
between VIN and AGND), over which 4095 positive output
codes and 4096 negative output codes exist. The A-to-D
can be used in either ratiometric or absolute reference applications. The voltage source driving VREF must have a
very low output impedance and very low noise. The circuit in
Figure 4 is an example of a very stable reference that is
appropriate for use with the ADC1242.
In a ratiometric system, the analog input voltage is proportional to the voltage used for the A/D reference. When this
voltage is the system power supply, the VREF pin can be
tied to VCC. This technique relaxes the stability requirement
of the system reference as the analog input and A/D reference move together maintaining the same output code for
given input condition.
2.2 RESETTING THE A/D
All internal logic can be reset, which will abort any conversion in process. The A/D is reset whenever a new conversion is started by taking CS and WR low. If this is done when
the analog input is being sampled or when EOC is low, the
Auto-Cal correction factors may be corrupted, therefore
making it necessary to do an Auto-Cal cycle before the next
conversion. This is true with or without Auto-Zero. The Calibration Cycle cannot be reset once started. On power-up
the ADC1242 automatically goes through a Calibration Cycle that takes typically 1396 clock cycles.
TL/H/11735 – 17
*Tantalum
FIGURE 4. Low Drift Extremely Stable Reference Circuit
11
3.0 Analog Considerations (Continued)
TL/H/11735 – 18
FIGURE 5. Analog Input Equivalent Circuit
ductance tantalum capacitors of 10 mF or greater paralleled
with 0.1 mF ceramic capacitors are recommended for supply
bypassing. Separate bypass capacitors whould be placed
b
close to the DVCC, AVCC and V pins. If an unregulated
voltage source is available in the system, a separate
LM340LAZ-5.0 voltage regulator for the A-to-D’s VCC (and
other analog circuitry) will greatly reduce digital noise on the
supply line.
For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
In general, the magnitude of the reference voltage will require an initial adjustment to null out full-scale errors.
3.2 INPUT CURRENT
A charging current will flow into or out of (depending on the
input voltage polarity) of the analog input pin (VIN) on the
start of the analog input sampling period (tA). The peak value of this current will depend on the actual input voltage
applied.
3.7 THE CALIBRATION CYCLE
On power up the ADC1242 goes through an Auto-Cal cycle
which cannot be interrupted. Since the power supply, reference, and clock will not be stable at power up, this first
calibration cycle will not result in an accurate calibration of
the A/D. A new calibration cycle needs to be started after
the power supplies, reference, and clock have been given
enough time to stabilize. During the calibration cycle, correction values are determined for the offset voltage of the
sampled data comparator and any linearity and gain errors.
These values are stored in internal RAM and used during an
analog-to-digital conversion to bring the overall gain, offset,
and linearity errors down to the specified limits. It should be
necessary to go through the calibration cycle only once after power up.
3.3 INPUT BYPASS CAPACITORS
An external capacitor can be used to filter out any noise due
to inductive pickup by a long input lead and will not degrade
the accuracy of the conversion result.
3.4 INPUT SOURCE RESISTANCE
The analog input can be modeled as shown in Figure 5 .
External RSE will lengthen the time period necessary for the
voltage on CREF to settle to within (/2 LSB of the analog
input voltage. With fCLK e 2 MHz tA e 7 clock periods e
3.5 ms, RSE s 1 kX will allow a 5V analog input voltage to
settle properly.
3.8 THE AUTO-ZERO CYCLE
To correct for any change in the zero (offset) error of the
A/D, the auto-zero cycle can be used. It may be necessary
to do an auto-zero cycle whenever the ambient temperature
changes significantly. (See the curved titled ‘‘Zero Error
Change vs Ambient Temperature’’ in the Typical Performance Characteristics.) A change in the ambient temperature
will cause the VOS of the sampled data comparator to
change, which may cause the zero error of the A/D to be
greater than the amount specified. An auto-zero cycle will
maintain the zero error to the amount specified or less.
3.5 NOISE
The leads to the analog input pin should be kept as short as
possible to minimize input noise coupling. Both noise and
undesired digital clock coupling to this input can cause errors. Input filtering can be used to reduce the effects of
these noise sources.
3.6 POWER SUPPLIES
b
Noise spikes on the VCC and V supply lines can cause
conversion errors as the comparator will respond to this
noise. The A/D is especially sensitive during the auto-zero
or auto-cal procedures to any power supply spikes. Low in
12
4.0 Dynamic Performance
Many applications require the A/D converter to digitize ac
signals, but the standard dc integral and differential nonlinearity specifications will not accurately predict the A/D converter’s performance with ac input signals. The important
specifications for ac applications reflect the converter’s ability to digitize ac signals without significant spectral errors
and without adding noise to the digitized signal. Dynamic
characteristics such as signal-to-noise a distortion ratio
(S/(N a D)), effective bits, full power bandwidth, aperture
time and aperture jitter are quantitative measures of the
A/D converter’s capability.
An A/D converter’s ac performance can be measured using
Fast Fourier Transform (FFT) methods. A sinusoidal waveform is applied to the A/D converter’s input, and the transform is then performed on the digitized waveform. S/(N a D)
is calculated from the resulting FFT data, and a spectral plot
may also be obtained. Typical values for S/(N a D) are
shown in the table of Electrical Characteristics, and spectral
plots are included in the typical performance curves.
The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can
be seen in the S/(N a D) versus frequency curves. These
curves will also give an indication of the full power bandwidth (the frequency at which the S/(N a D) drops 3 dB).
Two sample/hold specifications, aperture time and aperture
jitter, are included in the Dynamic Characteristics table
since the ADC1242 has the ability to track and hold the
analog input voltage. Aperture time is the delay for the A/D
to respond to the hold command. In the case of the
ADC1242, the hold command is internally generated. When
the Auto-Zero function is not being used, the hold command
occurs at the end of the acquisition window, or seven clock
periods after the rising edge of the WR. The delay between
the internally generated hold command and the time that
the ADC1242 actually holds the input signal is the aperture
time. For the ADC1242, this time is typically 100 ns. Aperture jitter is the change in the aperture time from sample to
sample. Aperture jitter is useful in determining the maximum
slew rate of the input signal for a given accuracy. For example, an ADC1242 with 100 ps of aperture jitter operating with
a 5V reference can have an effective gain variation of about
1 LSB with an input signal whose slew rate is 12 V/ms.
Power Supply Bypassing
TL/H/11735 – 19
*Tantalum
Protecting the Analog Inputs
TL/H/11735 – 20
13
ADC1242 12-Bit Plus Sign Sampling A/D Converter
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number ADC1242CIJ
NS Package Number J28A
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